flexxon global limited industrial emmc 4.5...

FLEXXON GLOBAL LIMITED

Industrial eMMC 4.5 Specification (Pseudo SLC)

Version 1.2

ALL RIGHTS ARE STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSLATED TO ANY OTHER FORMS WITHOUT PERMISSION FROM FLEXXON GLOBAL LIMITED.

Address: 13-08, Block E Wah Lok Industrial Centre, Nos. 31-35 Shan Mei Street, Fotan, Shatin, Hong Kong

Tel: +852-2711 5886

Fax : +852-3011 3058

Website: http://www.flxglobal.com

Email: [email protected]

Revision History

Revision Release Date History

1.0 2015/07/01 First release

1.1 2015/08/20 Update package size and operating temperature range

1.2 2015/08/30 Update 16GB

3

TABLE OF CONTENTS

1. Introduction ................................................................................................ 5

1.1. General Description ........................................................................................................... 5

1.2. eMMC Block Diagram ...................................................................................................... 5

1.3. Features Overview ............................................................................................................. 6

1.4. eMMC Functional Descriptions ........................................................................................ 6

1.4.1. Power Management ............................................................................................. 6

1.4.2. Defect and Error Management ............................................................................ 7

1.4.3. MMC Bus and Power Lines ................................................................................... 7

1.5. eMMC 4.5 Features ........................................................................................................... 7

1.5.1. HS200 Bus Speed Mode ........................................................................................ 7

1.5.2. Packed Commands ............................................................................................... 8

1.5.3. Trim ...................................................................................................................... 8

1.5.4. Discard .................................................................................................................. 9

1.5.5. Sanitize ................................................................................................................. 9

1.5.6. Real Time Clock Information ................................................................................ 9

1.5.7. Dynamic Capacity Management .......................................................................... 9

1.5.8. Power Off Notification........................................................................................ 10

2. Product Specifications............................................................................... 11

2.1. Typical eMMC Power Consumption ............................................................................... 11

2.2. Performance ..................................................................................................................... 11

3. Interface Description ................................................................................ 12

3.1. FLEXXON eMMC I/F Ball Array ................................................................................... 12

3.2. Pins and Signal Description ............................................................................................. 14

3.3. FLEXXON eMMC Registers .......................................................................................... 16

3.3.1. OCR Register ....................................................................................................... 16

3.3.2. CID Register ........................................................................................................ 16

3.3.3. CSD Register ....................................................................................................... 17

3.3.4. Extended CSD Register ....................................................................................... 18

4. eMMC Electrical characteristics ................................................................ 26

4.1. General DC Characteristics ............................................................................................. 26

4.2. Bus Signal Levels ............................................................................................................ 26

4.3. Bus Timing....................................................................................................................... 27

4.4. Power Delivery and Capacitor Specifications ................................................................. 32

4.4.1. FLEXXON eMMC Power Domains ....................................................................... 32

4

4.4.2. Capacitor Connection Guidelines ....................................................................... 33

5. Package Specifications .............................................................................. 35

6. Marking ..................................................................................................... 38

7. Ordering Information ................................................................................ 39

5

1. INTRODUCTION

1.1. General Description

FLEXXON eMMC is Embedded Flash Drives (EFD), which is a hybrid device combining an embedded flash

controller and standard MLC NAND flash memory, with industry standard eMMC4.5 interface.

Empowered with a new eMMC4.5 feature set such as HS200 mode, discard, sanitize, packet commands,

RTC (real time clock), dynamic capacity, and power off notification, FLEXXON eMMC is the optimal device

for reliable code and data storage.

In addition to high reliability and high system performance offered by the current FLEXXON eMMC family

of products, eMMC supports for multiple NAND technology transitions, as well as features such as an

advanced power management scheme.

FLEXXON eMMC uses advanced Multi-Level Cell (MLC) NAND flash technology, enhanced by embedded

flash management software running as firmware on the flash controller.

FLEXXON eMMC provides high random access speed, advanced flow control capability, more

powerful computing power. The hardware ECC engine implements intelligent flash management and

improve the NAND flash endurance. With enhanced vendor command support and embedded test

modes, FLEXXON eMMC brings high flexibility for customized usage and failure analysis.

FLEXXON eMMC provides pSLC (pseudo-SLC) NAND flash technology, more longer cell lifetime than MLC

NAND flash, but it is sufficient for many applications including enterprise storage environments.

FLEXXON eMMC is well-suited to meet the needs of small, low power, electronic devices. With JEDEC

form factors measuring 11.5mm x 13mm (153 balls), 12mm x 16mm (169 balls) and 14mm x 18mm (169

balls) compatible with 0.5mm ball pitch, it is fit for a wide variety of portable devices.

1.2. eMMC Block Diagram

Figure 1-1 eMMC block diagram

6

1.3. Features Overview

FLEXXON eMMC MMC interface includes the following features:

Complies with eMMC Specification Ver 4.5

Memory controller and NAND flash

Offered in TFBGA package of eMMC

￭ 11.5 mm x 13 mm x 1.0 mm

￭ 12 mm x 16 mm x 1.0/1.2 mm

￭ 14 mm x 18 mm x 1.2/1.4 mm

Temperature Range

￭ Operation (Diamond Grade) : -40°C ~ 85°C

￭ Operation (Gold Grade) : -25°C ~ 85°C

￭ Storage : -40°C ~ 85°C

eMMC

￭ Core voltage (VCC) : 2.7 ~ 3.6V

￭ I/O (VCCQ) wide range of voltages: 1.1~1.3V, 1.7~1.95V and 2.7~3.6V

￭ Supports three data bus widths: 1 bit (default), 4 bit, 8 bit

￭ Variable clock frequencies of 0~26 MHz (default), 0~52 MHz (high-speed)

￭ Double data rate (DDR) function and HS200 Mode

￭ Correction of memory field errors

1.4. eMMC Functional Descriptions

1.4.1. Power Management

A power saving feature of the eMMC is automatic entrance and exit from Auto-Suspend mode. Upon

completion of an operation, eMMC will enter the Auto-Suspend mode to conserve power if no further

commands are received within specific time period programmed by controller F/W. The host does not

have to take any action for this to occur. The eMMC is in Auto-Suspend mode except when the host is

accessing it, thus conserving power.

Any command issued by the host to the eMMC will cause it to exit Auto-Suspend mode and response

to the master.

When host issue Sleep command (CMD 5), the device will enter Sleep mode. It will be the best power

7

saving mode. Device should not respond to other commands until Awake command received.

1.4.2. Defect and Error Management

FLEXXON eMMC incorporates advanced technology for defect and error management. If a defective

block is identified, it completely replaces the defective block with one of the spare blocks. This process

is invisible to the host and generally does not affect data space allocated for the user.

FLEXXON eMMC also includes a built-in innovative error correction code (ECC) algorithm to ensure that

data integrity is maintained. It could correct up to 72 bits data errors per 1024 bytes data automatically.

1.4.3. MMC Bus and Power Lines

FLEXXON eMMC with MMC interface supports the MMC protocol. For more details regarding these buses,

refer to JEDEC standards No. JESD84-B451.

FLEXXON eMMC bus has the following communication and power lines:

• CMD: Command is a bidirectional signal. The host and eMMC operate in two modes, open drain and

push-pull.

• DAT0-7: Data lines are bidirectional signals. Host and eMMC operate in push-pull mode.

• CLK: Clock input.

• RST_n: Hardware Reset Input.

• VCCQ: VCCQ is the power supply line for the host interface.

• VCC: VCC is the power supply line for internal flash memory.

• VDDi: VDDi is internal power node, not the power supply. Connect 0.1uF capacitor from VDDi to ground.

• VSS, VSSQ: These are the ground lines.

1.5. eMMC 4.5 Features

1.5.1. HS200 Bus Speed Mode

FLEXXON eMMC supports HS200 mode, which offers the following features:

SDR Data sampling method

CLK frequency up to 200MHz data rate – up to 200MB/s

4 or 8-bit bus width supported

Single ended signaling with 4 selectable drive strength

Signaling levels of 1.8V and 1.2V

Tuning concept for Read Operations

8

Figure 1-2 shows a typical HS200 Host and Device system. The host has a clock generator, which supplies

CLK to the Device. For write operations, clock and data direction are the same, write data can be

transferred synchronous with CLK, regardless of transmission line delay. For read operations, clock and

data direction are opposite; the read data received by Host is delayed by round-trip delay, output delay

and and latency of Host and Device. For reads, the Host needs to have an adjustable sampling point to

reliably receive the incoming data.

Figure 1-2 Host and Device block diagram

The Host may use adjustable sampling to determine the correct sampling point. A predefined tuning

block stored in Device may be used by the Host as an aid for finding the optimal data sampling point.

The Host can use CMD21 tuning command to read the tuning block.

1.5.2. Packed Commands

Read and write commands can be packed in groups of commands (either all read or all write) that

transfer the data for all commands in the group in one transfer on the bus, to reduce overheads.

Several read commands or write commands can be packed to transfer all of their data in one operation.

Preliminary analysis shows driver often has more than one pending request in its queue, so packing can

improve IOPs significantly.

For additional information, refer to JESD84-B451 section 6.6.29.

1.5.3. Trim

The Trim function is similar to the Erase command but applies the erase operation to write blocks instead

of erase groups. When TRIM is executed the region shall read as ‘0’. This serves primarily as a data removal

command.

9

For additional information on the Trim function, refer to JEDEC standards No. JESD84-A451.

1.5.4. Discard

The Discard is similar operation to TRIM. The Discard function allows the host to identify data that is

no longer required so that the device can erase the data if necessary during background erase events.

The contents of a write block where the discard function has been applied shall be ‘don’t care’. After

discard operation, the original data may be remained partially or fully accessible to the host dependent

on device. The portions of data that are no longer accessible by the host may be removed or unmapped

just as in the case of TRIM. The device will decide the contents of discarded write block.

The distinction between Discard and TRIM, is that a read to a region that was discarded may return

some or all of the original data. However, in the case of Trim the entire region shall be unmapped or

removed and will return ‘0’ or ‘1’ depending on the memory technology.

1.5.5. Sanitize

The Sanitize operation is a feature, in addition to TRIM and Erase that is used to remove data from

the device. The use of the Sanitize operation requires the device to physically remove data from the

unmapped user address space. While the device is performing the sanitize operation, the busy line is

asserted. The device will continue the sanitize operation, with busy asserted, until one of the following

events occurs:

• Sanitize operation is complete.

• An HPI is used to abort the operation

• A power failure.

• A hardware reset.

After the sanitize operation is completed, no data should exist in the unmapped host address space.

1.5.6. Real Time Clock Information

Providing real time clock information to the device may be useful for internal maintenance operations.

Host may provide either absolute time (based on UTC) if available, or relative time. This feature

provides a mechanism for the host to update both real time clock and relative time updates.

1.5.7. Dynamic Capacity Management

Extensive memory usage and aging of Flash could result in bad blocks. Dynamic Capacity Management

provides a mechanism for the memory device to reduce its reported capacity and extend the device

life time.

10

1.5.8. Power Off Notification

The host should notify the device before it powers the device off. This allows the device to better prepare

itself for being powered off. The power off mode has two notifications: POWER_OFF_LONG and

POWER_OFF_SHORT.

The difference between the two power-off modes is how urgent the host wants to turn power off. The

device should respond to POWER_OFF_SHORT quickly under the generic CMD6 timeout. If more time

is acceptable, POWER_OFF_LONG may be used and the device shall respond to it within the

POWER_OFF_LONG_TIME timeout.

11

2. PRODUCT SPECIFICATIONS

2.1. Typical eMMC Power Consumption

Table 2-1 Power Consumption

Mode Speed Max Value Measurement

Auto

Sleep 350uA 250uA

Sleep 200uA (Max) 100uA

130uA (Typical) 56uA

Read

Default Speed 100mA

High Speed 200mA 73mA

DDR 75mA

HS200 90mA

Write

Default Speed 100mA

High Speed 200mA 30 mA

DDR 35 mA

HS200 35 mA

VCC (ripple: max, 60mV peak-to-peak) 2.7V ~ 3.6V

Notes:

1. Current measurements are averages over 100msecs.

2. Sleep is measured at room temperature.

3. In sleep state, triggered by CMD5, the Flash VCC power supply is switched off.

2.2. Performance

Table 2-2 pSLC eMMC Performance

Density Sequential Read (MB/s) Sequential Write (MB/s)

4GB 83 16

8GB 83 32

16GB 83 48

Notes:

Test condition: Bus width x8, 1.8V I/O, HS200 mode, w/o file system overhead, measured on internal board.

12

3. INTERFACE DESCRIPTION

3.1. FLEXXON eMMC I/F Ball Array

Figure 3-1 illustrates FLEXXON eMMC MMC interface in 153 ball array. Ballout is:

Figure 3-1 153-Ball Array (Top View)

13

Figure 3-2 illustrates FLEXXON eMMC MMC interface in 169 ball array. Ballout is:

Figure 3-2 169-Ball Array (Top View)

14

3.2. Pins and Signal Description

Table 3-1 Function Pin Assignment, 153 balls

eMMC Interface

Ball No. Ball Signal Type Description

A3 DAT0

I/O Data I/O: Bidirectional channel used for data

transfer

A4 DAT1

A5 DAT2

B2 DAT3

B3 DAT4

B4 DAT5

B5 DAT6

B6 DAT7

M5 CMD I/O Command: A bidirectional channel used for device

initialization and command transfers.

M6 CLK Input Clock: Each cycle directs a 1-bit transfer on the

command and DAT lines

K5 RESET Input Hardware Reset

E6 VCC

Supply Flash I/O and memory power supply F5 VCC

J10 VCC

K9 VCC

C6 VCCQ

Supply Memory controller core and MMC I/F I/O power

supply

M4 VCCQ

N4 VCCQ

P3 VCCQ

P5 VCCQ

E7 VSS

Supply Flash I/O and memory ground connection G5 VSS

H10 VSS

K8 VSS

C4 VSSQ

Memory controller core and MMC I/F ground

connection

N2 VSSQ

N5 VSSQ

P4 VSSQ

P6 VSSQ

C2 VDDi Internal power node. Connect 0.1uF capacitor

between VDDi net and ground

15

Table 3-2 Function Pin Assignment, 169 balls

eMMC Interface

Ball No. Ball Signal Type Description

H3 DAT0

I/O Data I/O: Bidirectional channel used for data

transfer

H4 DAT1

H5 DAT2

J2 DAT3

J3 DAT4

J4 DAT5

J5 DAT6

J6 DAT7

W5 CMD I/O Command: A bidirectional channel used for device

initialization and command transfers.

W6 CLKm Input Clock: Each cycle directs a 1-bit transfer on the

command and DAT lines

U5 RST_n Input Hardware Reset

M6 VCC

Supply Flash I/O and memory power supply N5 VCC

T10 VCC

U9 VCC

K6 VCCQ

Supply Memory controller core and MMC I/F I/O power

supply

W4 VCCQ

Y4 VCCQ

AA3 VCCQ

AA5 VCCQ

M7 VSS

Supply Flash I/O and memory ground connection P5 VSS

R10 VSS

U8 VSS

K4 VSSQ

Memory controller core and MMC I/F ground

connection

Y2 VSSQ

Y5 VSSQ

AA4 VSSQ

AA6 VSSQ

K2 VDDi Internal power node. Connect 0.1uF capacitor

between VDDi net and ground

16

3.3. FLEXXON eMMC Registers

3.3.1. OCR Register

For eMMC devices, the OCR response is fixed. The value could be either 0x00FF8080 (for storage capacity

of up to 2GB) or 0x40FF8080 (for storage capacity greater than 2GB) depending on the capacity.

Table 3-2 OCR Register Table

Parameter OCR slice Description Value Width

Access Mode

[30:29] Access mode 00b 2

[23:15] VDD: 2.7 - 3.6 range 111111111b 9

[14:8] VDD: 2.0 - 2.6 range 0000000b 7

[7] VDD: 1.7 - 1.95 range 1b 1

3.3.2. CID Register

Table 3-3 CID Register Table

Parameter CID slice Description Value Width

MID [127:120] Manufacturer ID 4Bh 8

CBX [113:112] Card BGA 01h 2

OID [111:104] OEM/Application ID 08h 8

PNM [103:56] Product name eMMC 48

PRV [55:48] Product revision 00h 8

PSN [47:16] Product serial number Random by Production 32

MDT [15:8] Manufacturing date month, year 8

CRC [7:1] CRC7 checksum xxxxxxb 7

17

3.3.3. CSD Register

The section contains preliminary data and may be updated in a later version.

Table 3-4 CSD Register Table

Name Field Bit Type Slice Value Description

CSD structure CSD_STRUCTURE 2 R [127:126] 3h In EXT_CSD

register System specification

version SPEC_VERS 4 R [125:122] 4h Version 4.4

Reserved - 2 R [121:120] 0h

Data read access-time-1 TAAC 8 R [119:112] 27h 15 ms

Data read access-time-2 in

CLK cycles (NSAC*100) NSAC 8 R [111:104] 01h

1x100 = 100

clock cycles

Max. bus clock frequency TRAN_SPEED 8 R [103:96] 32h 26 MHz

Card command classes CCC 12 R [95:84] F5h Class

0/2/4/5/6/7

Max. read data block

length READ_BL_LEN 4 R [83:80] 9h

512B for low

density.

Partial blocks for read

allowed READ_BL_PARTIAL 1 R [79:79] 0h Not support

Write block misalignment WRITE_BLK_MISALIGN 1 R [78:78] 0h Not support

Read block misalignment READ_BLK_MISALIGN 1 R [77:77] 0h Not support

DSR implemented DSR_IMP 1 R [76:76] 0h Not support

Reserved - 2 R [75:74] 0h

Device size C_SIZE 12 R [73:62] FFFh

Size > 2GB,

see EXT_CSD

for size

Max. read current @ VDD

min VDD_R_CURR_MIN 3 R [61:59] 7h 100 mA

Max. read current @ VDD

max VDD_R_CURR_MAX 3 R [58:56] 7h 200mA

Max. write current @ VDD

min VDD_W_CURR_MIN 3 R [55:53] 7h 100 mA

Max. write current @ VDD

max VDD_W_CURR_MAX 3 R [52:50] 7h 200 mA

Device size multiplier C_SIZE_MULT 3 R [49:47] 7h See C_SIZE

Erase group size ERASE_GRP_SIZE 5 R [46:42] 1Fh Erasable unit

= 32x32x512

= 512KB Erase group size multiplier ERASE_GRP_MULT 5 R [41:37] 1Fh

18

Write protect group size WP_GRP_SIZE 5 R [36:32] Fh 0Fh: 6x512KB

=8MB

Write protect group

enable

WP_GRP_ENABLE 1 R [31:31] 1h Enable

Manufacturer default ECC DEFAULT_ECC 2 R [30:29] 0h None

Write speed factor R2W_FACTOR 3 R [28:26] 2h 4X

Max. write data block

length

WRITE_BL_LEN 4 R [25:22] 9h 512 byte

Partial blocks for write

allowed WRITE_BL_PARTIAL 1 R [21:21] 0h Not support

Reserved - 4 R [20:17] -

Content protection

application CONTENT_PROT_APP 1 R [16:16] 0h

File format group FILE_FORMAT_GROUP 1 R/W [15:15] 0h

Copy flag (OTP) COPY 1 R/W [14:14] 1h

Permanent write

protection

PERM_WRITE_PROTECT 1 R/W [13:13] 0h

Temporary write

protection

TMP_WRITE_PROTECT 1 R/W/E [12:12] 0h

File format FILE_FORMAT 2 R/W [11:10] 0h

ECC code ECC 2 R/W/E [9:8] 0h

CRC CRC 7 R/W/E [7:1] -

Not used, always '1' - 1 - [0:0] 1h

3.3.4. Extended CSD Register

The Extended CSD register defines the additional behavior of eMMC devices due to limited CSD

information. The section contains preliminary data and may be updated in a later version.

Table 3-5 EXT_CID Register Table

Name Field Byte Type Slice Value Description

Reserved - 6 - [511:506] -

Extended Security

Commands Error EXT_SECURITY_ERR 1 R [505] 0h

Supported command sets S_CMD_SET 1 R [504] 1h Standard MMC

HPI features HPI_FEATURES 1 R [503] 3h HPI supported with

CMD12

Background operations

support BKOPS_SUPPORT 1 R [502] 1h

Background

operations supported

19

Max packed read

commands MAX_PACKED_READS 1 R [501] 8h

Max. 8 commands in a

packed command

Max packed write

commands MAX_PACKED_WRITES 1 R [500] 8h

Max. 8 commands in a

packed command

Data Tag Support DATA_TAG_SUPPORT 1 R [499] 1h Data tag supported

Tag Unit Size TAG_UNIT_SIZE 1 R [498] 0h 1 x sector size = 2KB or

16KB

Tag Resources Size TAG_RES_SIZE 1 R [497] 06h Cap Size/1024

Context management

capabilities

CONTEXT_CAPABILITIE

S 1 R [496] 78h

Max Tag Size = 8 x 2

=16MB; Max_Context

ID = 8

Large Unit size LARGE_UNIT_SIZE_M1 1 R [495] 1h 1MB x 2= 2MB

Extended partitions

attribute support EXT_SUPPORT 1 R [494] 3h

Support "System

code"; Support "Non-

persistent"

Reserved - 241 - [493:253] -

Cache size CACHE_SIZE 4 R [252:249] 200h 64KB (Depending on

16KB x CE)

Generic CMD6 timeout GENERIC_CMD6_TIME 1 R [248] 64h

100x10ms=1000ms

(To Sync. With

EXT_CSD[247]

Power off

notification (long) timeout

POWER_OFF_LONG_TI

ME 1 R [247] 64h 100x10ms=1000ms

Background operations

status BKOPS_STATUS 1 R [246] 0h Run Time update

Number of correctly

programmed sectors

CORRECTLY_PRG_SECT

ORS_NUM 4 R [245:242] 0h Run Time update

First initialization time

after partitioning INI_TIMEOUT_AP 1 R [241] 0Ah 10x100ms=1s

Reserved - 1 - [240] -

Power class for 52MHz,

DDR at 3.6V PWR_CL_DDR_52_360 1 R [239] 0h

RMS 100 mA,Peak 200

mA


DDR at 1.95V PWR_CL_DDR_52_195 1 R [238] 0h

RMS 65 mA, Peak 130

mA

20

Power class for 200MHz at

1.95V PWR_CL_200_195 1 R [237] 0h


at 1.3V PWR_CL_200_130 1 R [236] 0h

Minimum Write

Performance for 8bit at

52MHz in DDR mode

MIN_PERF_DDR_W_8_

52 1 R [235] 0h No rating

Minimum Read

Performance for 8bit at

52MHz in DDR mode

MIN_PERF_DDR_R_8_

52 1 R [234] 0h No rating

Reserved - 1 - [233] -

TRIM multiplier TRIM_MULT 1 R [232] 1h 1x300ms=300ms

Secure feature support SEC_FEATURE_SUPPOR

T 1 R [231] 55h

1. Sanitize support

2. Secure/insecure

trim support

3. Secure purge

support

4. Secure purge on

retired defective

portions support

Secure erase multiple SEC_ERASE_MULT 1 R [230] 0Ah 10x1x300ms=3s

Secure trim multiple SEC_TRIM_MULT 1 R [229] 0Ah 10x1x300ms=3s

Boot information BOOT_INFO 1 R [228] 7h

(Other) high

speed/alternative/DD

R boot up supported

Reserved - 1 - [227] -

Boot partition size BOOT_SIZE_MULTI 1 R [226] 20h 128KBx32=4MB

128KBx16=2MB

Access size ACC_SIZE 1 R [225] 6h Super page size = 64 x

512B= 32 KB

21

High-capacity erase unit

size HC_ERASE_GRP_SIZE 1 R [224] 1h

High-capacity erase

group size 1x 512 KB

High-capacity erase

timeout

ERASE_TIMEOUT_MUL

T 1 R [223] 2h 1x300ms=300ms

Reliable write sector count REL_WR_SEC_C 1 R [222] 1h No meaning if

ExtCSD[166].0=1

High-capacity write

protect group size HC_WP_GRP_SIZE 1 R [221] 10h 10h: 16 x 512KB=8MB

Sleep current (VCC) S_C_VCC 1 R [220] 7h VCC <128uA for sleep

Sleep current (VCCQ) S_C_VCCQ 1 R [219] 7h VCC <128uA for sleep

Reserved - 1 - [218] -

Sleep/awake timeout S_A_TIMEOUT 1 R [217] 13h (2^19)x100ns =

52.4288ms

Reserved - 1 - [216] -

Sector count SEC_COUNT 4 R [215:212] TBD Depending on capacity

Reserved - 1 - [211] -

Minimum write

performance for 8bit at 52

MHz

MIN_PERF_W_8_52 1 R [210] 8h

Minimum read

performance for 8 bit at

52 MHz

MIN_PERF_R_8_52 1 R [209] 8h

Minimum write


26 MHz, for 4 bit at 52

MHz

MIN_PERF_W_8_26_4

_52 1 R [208] 8h

Minimum read


26 MHz, for 4 bit at 52

MHz

MIN_PERF_R_8_26_4_

52 1 R [207] 8h

Minimum write


26 MHz

MIN_PERF_W_4_26 1 R [206] 8h

Minimum read


26 MHz

MIN_PERF_R_4_26 1 R [205] 8h

22

Reserved - 1 - [204] -

Power class for 26 MHz at

3.6 V PWR_CL_26_360 1 R [203] 0h

RMS 100 mA /PEAK

200mA


3.6 V PWR_CL_52_360 1 R [202] 0h

RMS 100 mA /PEAK

200mA


1.95 V PWR_CL_26_195 1 R [201] 0h

RMS 65 mA /PEAK

130mA


1.95 V PWR_CL_52_195 1 R [200] 0h

RMS 65 mA /PEAK

130mA

Partition switching timing PARTITION_SWITCH_TI

ME

1 R [199] 3h 3x10ms =30ms

Out-of-interrupt busy

timing

OUT_OF_INTERRUPT_T

IME 1 R [198] 2h 2x10ms =20ms

I/O Driver Strength DRIVER_STRENGTH 1 - [197] 07h

Device type DEVICE_TYPE 1 R [196] 17h

(Chip =3Fh) HS200

Single Data Rate

e.MMC @200MHZ -

1.8V I/O

Reserved - 1 - [195] -

CSD structure version CSD_STRUCTURE 1 R [194] 2h CSD version No. 1.2

Reserved - 1 - [193] -

Extended CSD revision EXT_CSD_REV 1 R [192] 6h EXT_CSD 1.6 (MMC

4.5)

Command set CMD_SET 1 R/W/E_P [191] 0h

Reserved - 1 - [190] -

Command set revision CMD_SET_REV 1 R [189] 0h

Reserved - 1 - [188] -

Power class POWER_CLASS 1 R/W/E_P [187] 0h

Reserved - 1 - [186] 0h

High speed interface

timing

HS_TIMING 1 R/W/E_P [185] 0h

Reserved - 1 - [184] -

Bus width mode BUS_WIDTH 1 W/E_P [183] 0h

Reserved - 1 - [182] -

Erased memory content ERASED_MEM_CONT 1 R [181] 0h

Reserved - 1 - [180] -

Partition configuration PARTITION_CONFIG 1 R/W/E

R/W/E_P [179] 0h

23

Boot configuration

protection BOOT_CONFIG_PROT 1

R/W

R/W/C_P [178] 0h

Boot bus Conditions BOOT_BUS_CONDITIO

NS

1 R/W/E [177] 0h

Reserved - 1 - [176] -

High-density erase group

definition

ERASE_GROUP_DEF 1 R/W/E [175] 0h

Reserved - 1 - [174] -

Boot area write protection

register BOOT_WP 1

R/W

R/W/C_P [173] 0h

Reserved - 1 - [172] -

User area write protection

register USER_WP 1

R/W

R/W/C_P

R/W/E_P

[171] 0h

Reserved - 1 - [170] -

FW configuration FW_CONFIG 1 R/W [169] 0h

RPMB size RPMB_SIZE_MULT 1 R [168] 20h 128KBx32=4MB

128KBx16=2MB

Write reliability setting

register WR_REL_SET 1 R/W [167] 1Fh

Use 1Fh for SPOR; use

00h for performance

Write reliability parameter

register WR_REL_PARAM 1 R [166] 5h

Reserved - 1 - [165] -

Manually start background

operations BKOPS_START 1 W/E_P [164] 0h

Enable background

operations handshake BKOPS_EN 1 R/W [163] 0h

H/W reset function RST_n_FUNCTION 1 R/W [162] 0h RST_n is temporarily

disabled

HPI management HPI_MGMT 1 R/W/E_P [161] 0h HPI is not activated by

the host

Partitioning support PARTITIONING_SUPPO

RT 1 R [160] 7h

Support partitioning;

Support enhanced;

Support Ext_Attr

Max enhanced area size MAX_ENH_SIZE_MULT 3 R [159:157] TBD Depending on

Capacity

Partitions attribute PARTITIONS_ATTRIBUT

E 1 R/W [156] 0h

24

Partitioning setting PARTITION_SETTING_C

OMPLETED 1 R/W [155] 0h

General purpose partition

size GP_SIZE_MULT 12 R/W [154:143] 0h

Enhanced user data area

size ENH_SIZE_MULT 3 R/W [142:140] 0h

Enhanced user data start

address ENH_START_ADDR 4 R/W [139:136] 0h

Reserved - 1 - [135] -

Secure bad block

management

SEC_BAD_BLK_MGMN

T 1 R/W [134] 0h

Reserved - 134 - [133] -

Package Case

Temperature is controlled TCASE_SUPPORT 1 W/E_P [132] 0h

Periodic Wake-up PERIODIC_WAKEUP 1 R/W/E [131] 0h

Program CID/CSD in DDR

mode support

PROGRAM_CID_CSD_D

DR_SUPPORT 1 R [130] 1h

Reserved - 2 - [129:128] -

Vendor Specific Fields VENDOR_SPECIFIC_FIE

LD 64

<vendor

specific> [127:64] TBD

Native sector size NATIVE_SECTOR_SIZE 1 R [63] 1h

Sector size emulation USE_NATIVE_SECTOR 1 R/W [62] 0h

Sector size DATA_SECTOR_SIZE 1 R [61] 0h

1st initialization after

disabling sector size

emulation

INI_TIMEOUT_EMU 1 R [60] 0Ah

Class 6 commands control CLASS_6_CTRL 1 R/W/E_P [59] 0h

Number of addressed

group to be Released DYNCAP_NEEDED 1 R [58] 0h

25

Exception events control EXCEPTION_EVENTS_C

TRL 2 R/W/E_P [57:56] 00h

1. URGENT_BKOPS

status bit is supported.

2. DYNCAP_NEEDED


3. SYSPOOL_EXHAUST

ED status bit is

supported.

4. PACKED_FAILURE


Exception events status EXCEPTION_EVENTS_S

TATUS 2 R [55:54]

0h

Device Run Time

update

Extended Partitions

Attribute

EXT_PARTITIONS_ATTR

IBUTE 2 R/W [53:52] 0h

Context configuration CONTEXT_CONF 15 R/W/E_P [51:36] 0h

Packed command status PACKED_COMMAND_S

TATUS 1 R [36] 0h

Device Run Time

update

Packed command failure

index

PACKED_FAILURE_IND

EX 1 R [35] 0h

Device Run Time

update

Power Off Notification POWER_OFF_NOTIFIC

ATION

1 R/W/E_P [34] 0h

Control to turn the Cache

ON/OFF CACHE_CTRL 1 R/W/E_P [33] 0h

Flushing of the cache FLUSH_CACHE 1 W/E_P [32] 0h

Reserved - 32 - [31:0] -

Notes: The type of the CSD Registry entries in the table is coded as follows.

R: Read only.

W: One time programmable and not readable.

R/W: One time programmable and readable.

W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0reset and

not readable.

R/W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0 reset and

readable.

R/W/C_P: Writable after value cleared by power failure and HW/rest assertion (the value not cleared by

CMD0 reset) and readable.

R/W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset

and readable.

W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset and

not readable.

26

4. EMMC ELECTRICAL CHARACTERISTICS

4.1. General DC Characteristics

Table 4-1 General DC Characteristics for eMMC

Parameter Min Typ Max Unit Remark

Supply voltage for high voltage range 2.7 3.3 3.6 V

Supply voltage for low voltage range 1.7 1.8 1.95 V

Supply voltage for ultra low voltage range 1.1 1.2 1.3 V

Supply voltage for core 1.1 1.2 1.3 V

I/O input leakage current -10 - 10 uA

I/O output leakage current -10 - 10 uA

Programmable pull-up resistor 35 50 70 KOhm VCCQ = 3.3V

Programmable pull-down resistor 35 50 70 KOhm VCCQ = 3.3V

Programmable pull-up resistor - - - KOhm VCCQ = 1.8V

Programmable pull-down resistor - - - KOhm VCCQ = 1.8V

Programmable pull-up resistor - - - KOhm VCCQ = 1.2V

Programmable pull-down resistor - - - KOhm VCCQ = 1.2V

Pre-initial standby current - 300 - uA

Post-initial standby current - 100 - uA VCCQ > 1.65V

Sleep current - 25 - uA

Operating temperature -40 85 °C

Storage temperature -40 85 °C

4.2. Bus Signal Levels

Figure 4-1 Bus Signal Levels

27

Table 4-2 Bus Signals Levels

Parameter Symbol Min Max Unit Remark

Open-drain bus signal level

Output HIGH voltage VOH VCCIO - 0.2 - V

Output LOW voltage VOL - 0.3 V IOL = 2 mA

Push-pull bus signal level (2.7V~3.6V)

Output HIGH voltage VOH 0.75 * VCCIO - V IOH = -100 uA @

VDD min

Output LOW voltage VOL - 0.125 * VCCIO V IOL = 100 uA @

VDD min

Input HIGH voltage VIH 0.625 * VCCIO VCCIO + 0.3 V

Input LOW voltage VIL GNDIO - 0.3 0.25 * VCCIO V


Output HIGH voltage VOH VCCIO - 0.45 - V IOH = -2 mA

Output LOW voltage VOL - 0.45 * VCCIO V IOL = 2 mA




Output HIGH voltage VOH 0.75 * VCCIO - V IOH = -2 mA

Output LOW voltage VOL - 0.25 * VCCIO V IOL = 2 mA



4.3. Bus Timing

Figure 4-2 Bus Timing in Single Data Rate Mode

28

Figure 4-3 Bus Timing in Dual Data Rate Mode

Table 4-3 Backward Compatible Card Interface Timing


Clock frequency data transfer mode fPP 0 26 MHz C-Load ≤ 30 pF

Clock frequency identification mode fOD 0 400 kHz

Clock high time tWH 6.5 - ns C-Load ≤ 30 pF

Clock low time tWL 6.5 - ns C-Load ≤ 30 pF

Clock rise time tTLH - 3 ns C-Load ≤ 30 pF

Clock fall time tTHL - 3 ns C-Load ≤ 30 pF

2.7 ≤ VCCIO ≤ 3.6V

Input set-up time tISU 3 - ns C-Load ≤ 30 pF

Input hold time tIH 3 - ns C-Load ≤ 30 pF

Output set-up time tOSU 11.7 - ns C-Load ≤ 30 pF

Output hold time tOH 8.3 - ns C-Load ≤ 30 pF

1.7 ≤ VCCIO ≤ 1.95V




Output hold time tOH 8.3 - ns C-Load ≤ 3 0 pF

1.1 ≤ VCCIO ≤ 1.3V





29

Table 4-4 High Speed Card Interface Timing


Clock frequency data

transfer mode fPP 0 52 MHz

C-Load ≤ 3 0 pF

Tolerance + 100 KHz

Clock frequency

identification mode fOD 0 400 kHz Tolerance +20 KHz

Clock high time tWH 6.5 - ns C-Load ≤ 30 pF

Clock low time tWL 6.5 - ns C-Load ≤ 30 pF

Clock rise time tTLH - 3 ns C-Load ≤ 30 pF

Clock fall time tTHL - 3 ns C-Load ≤ 30 pF

2.7 ≤ VCCIO ≤ 3.6V

Input set-up time tISU 3 - ns C-Load ≤ 3 0 pF


Output delay time tODLY - 13.7 ns C-Load ≤ 30 pF


Signal rise time tRISE - 3 ns C-Load ≤ 30 pF

Signal fall time tFALL - 3 ns C-Load ≤ 30 pF

1.7 ≤ VCCIO ≤ 1.95V







1.1 ≤ VCCIO ≤ 1.3V







30

Table 4-5 Dual Date Rate Interface Timing


Clock duty cycle - 45 55 % Include jitter, phase noise

2.7 ≤ VCCQ ≤ 3.6V

Input set-up time tISUddr 2.5 - ns C - Load ≤ 30 pF

Input hold time tIHddr 2.5 - ns C - Load ≤ 30 pF

Output delay time tODLYddr 1.5 7 ns C - Load ≤ 30 pF

Signal rise time tRISE - 2 ns C - Load ≤ 30 pF

Signal fall time tFALL - 2 ns C - Load ≤ 30 pF

1.7 ≤ VCCQ ≤ 1.95V






1.1 ≤ VCCQ ≤ 1.3V






Figure 4-4 HS200 Device Input Timing

Notes:

1. tISU and tIH are measured at VIL(max.) and VIH(min.).

2. VIH denote VIH(min.) and VIL denotes VIL(max.).

31

Table 4-6 HS200 Device Input Timing

Symbol Min Max Unit Remark

tISU 1.4 - ns 5pF ≤ CBGA ≤ 12pF

tIH 0.8 ns 5pF ≤ CBGA ≤ 12pF

Figure 4-5 HS200 Device Output Timing

Notes: VOH denotes VOH(min.) and VOL denotes VOL(max.).

32

Table 4-7 HS200 Device Output Timing

Symbol Min Max Unit Remark

tPH 0 2 UI

Device output momentary phase

from CLK input to CMD or DAT lines

output.

Does not include a long term

temperature drift.

ΔTPH -350 (ΔT= -20 deg.C) +1550 (ΔT= -20

deg.C) ps

Delay variation due to temperature

change after tuning.

Total allowable shift of output valid

window (TVW) from last system

Tuning procedure

ΔTPH is 2600ps for ΔT from -25

deg.C to 125 deg.C during

operation.

tvw 0.575 - UI

tVW=2.88ns at 200MHz

Using test circuit including skew

among CMD and DAT lines created

by the Device.

Host path may add Signal Integrity

induced noise, skews, etc. Expected

TVW at Host input is larger than

0.475UI.

4.4. Power Delivery and Capacitor Specifications

4.4.1. FLEXXON eMMC Power Domains

FLEXXON eMMC has three power domains assigned to VCCQ, VCC and VDDi.

Table 4-8 Power Domains

Pin Power Domain Comments

VCCQ eMMC Interface

Supported voltage ranges:

High Voltage Region: 3.3 V (nominal)

Low Voltage Region: 1.8 V (nominal)

VCC Memory Supported voltage ranges:

High Voltage Region: 3.3 V (nominal)

VDDi Internal

VDDi is the internal regulator

connection to an external decoupling

capacitor.

33

4.4.2. Capacitor Connection Guidelines

VDDi Connections

The VDDi ball must only be connected to an external capacitor that is connected to VSS. This signal may not

be left floating. The capacitor’s specifications and its placement instructions are detailed below.

The capacitor is part of an internal voltage regulator that provides power to the controller.

Caution: Failure to follow the guidelines below or connecting the VDDi ball to any external signal or power

supply may cause the device to malfunction.

The trace requirements from the VDDi ball to the capacitor are as follows:

Resistance: < 2 ohm

Inductance: < 5 nH

The capacitor requirements are as follows:

Capacitance: ≥ 0.1 uF

Voltage Rating: ≥ 6.3 V

Dielectric: X7R or X5R

VCC and VCCQ Connections

All VCC/VCCQ balls should be connected either to a 3.3 V or 1.8 V supply. FLEXXON recommends providing

separate bypass capacitors for each power domain as shown in Figure 4-6.

The recommended capacitor and trace characteristics are summarized in Table 4-9.

Table 4-9 Capacitor and Trace Recommendations

Power

Domain

Capacitors Trace Recommendations

Capacitance Technology R[ohm] L[nH]

VCC to VSS 4.7uF + 0.2uF X5R or X7R < 250 m ohm < 10 nH (loop inductance from VCC to VSS)

VCCQ to VSSQ 2.2uF + 0.2uF X5R or X7R < 250 m ohm < 10 nH (loop inductance from VCC to VSS)

Note: Signal routing in the diagram is for illustration purposes only and the final routing depends on your

PCB layout. Also, for clarity, the diagram does not show the VSS connection. All balls marked VSS should be

connected to a ground (GND) plane.

34

Figure 4-6 eMMC Recommended Power Domain Connections

35

5. PACKAGE SPECIFICATIONS

Figure 5-1 11.5x13mm 153B eMMC Package Information

36

Figure 5-2 12x16mm 169B eMMC Package Information

37

Figure 5-3 14x18mm 169B eMMC Package Information

38

6. MARKING

Figure 6-1 Marking Information

First row: FLEXXON Logo

Second row: Part Number

Third row: Date of Working order

Fourth row: 00+Numbers of working order

39

7. ORDERING INFORMATION

Pseudo SLC

Capacity MPN (Diamond Grade) MPN (Gold Grade) Power

System

Pin

Configuration Package Size

4GB FEMC004GMFE5-D12-13 FEMC004GMFG5-D12-13 VCCQ:

2.7V~3.6V

1.7V~1.95V

1.1V~1.3V

VCC:

2.7V~3.6V

169FBGA

12x16x1.0(mm)

8GB FEMC008GMFE5-D12-23 FEMC008GMFG5-D12-23

16GB FEMC016GMFE5-D12-43 FEMC016GMFG5-D12-43 12x16x1.2(mm)

flexxon global limited industrial emmc 4.5...

Documents