flash mcu workshop atmel korea. flash mcu workshop goals detailed architecture knowledge hands on...

Flash MCU

WorkshopAtmel Korea

Flash MCU

Workshop Goals

• Detailed Architecture Knowledge

• Hands on experience with the AVR Tools– IAR Assembler and C-Compiler

– AVR Studio

– AVR Emulator

• Design your own AVR Beer Altimeter

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AVR Presentation

• Architecture

• Instruction set

• Peripherals

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• Highest Performance 8-Bit MCU• Real RISC Architecture• 32 Registers, 2-Address Machine, Single Cycle Execution• Low Power• 8 MB Direct Address Reach• Fast Context Switching• Efficient C Language Code Density

RISC Performance with CISC Code Density

Key Features

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Speed

Code Density

Traditional

CISC

Traditional

RISC

Traditional

Line of Compromise

Breaking Traditions

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AVR Architecture

An introduction to the MCU

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Block Diagram

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Register FileR0R1R2R3

R26R27R28R29R30R31

Register File

X Pointer

Y Pointer

Z Pointer

XLXHYLYHZLZH

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Direct Register - ALU Connection

Register File

ALU

Register operationstake ONE clock pulseon the EXTERNAL clockinput

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Execute 2 Instructions

HC05

‘C51

PIC

1 2

1

1

1

Done!

2

2

Done!

2

Done!

Done!

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A C-Code Example

The following example illustrates how the AVR benefits in terms of:

Code Size

Throughput

Power Consumption

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A Small C Function

/* Return the maximum value of a table of 16 integers */ int max(int *array){ char a; int maximum=-32768; for (a=0;a<16;a++) if (array[a]>maximum) maximum=array[a]; return (maximum);}

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AVR Assembly output

; 7. for (a=0;a<16;a++) LDI R18,LOW(0) LDI R19,128 CLR R22?0001: CPI R22,LOW(16) BRCC ?0000; 8. {; 9. if (array[a]>maximum) MOV R30,R22 CLR R31 LSL R30 ROL R31 ADD R30,R16 ADC R31,R17

LDD R20,Z+0 LDD R21,Z+1 CP R18,R20 CPC R19,R21 BRGE ?0005; 10. maximum=array[a]; MOV R18,R20 MOV R19,R21?0005: INC R22 RJMP ?0001?0000:; 11. }; 12. return (maximum); MOV R16,R18 MOV R17,R19; 13. } RET

Code Size: 46 Bytes, Execution time: 335 cycles

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C51 Assembly Output?C0002: ; SOURCE LINE # 14 MOV R6,maximumMOV R7,maximum+01H ; SOURCE LINE # 15?C0005: RET ; FUNCTION _max (END)?C?ILDOPTR: CJNE R3,#0x01,0x195 MOV A,0x82 ADD A,R1 MOV 0x82,A MOV A,0x83 ADDC A,R2 MOV 0x83,A MOVX A,@DPTR MOV OxF0,A INC DPTR MOVX A,@DPTR RET JNC 0x1A0 MOV A,R1 ADD A,0x82 MOV R0,A MOV 0xF0,@R0 INC R0 MOV A,@R0 RET CJNE R3,#0xFE,0xAD MOV A,R1 ADD A,0X82 MOV R0,A MOV A,@R0 MOV 0xF0,A INC R0 RET MOV A,0X83 ADD A,R2 MOV 0X83,A MOV A,R1 MOVC A,@A+DPTR RET

; FUNCTION _max (BEGIN);---- Variable 'array' assigned to Register 'R1/R2/R3' ---- ; SOURCE LINE # 4 ; SOURCE LINE # 5 ; SOURCE LINE # 7 MOV maximum,#080H MOV maximum+01H,#00H ; SOURCE LINE # 9;---- Variable 'a' assigned to Register 'R5' ---- CLR A MOV R5,A?C0001: ; SOURCE LINE # 10 ; SOURCE LINE # 11 MOV A,R5 MOV R7,A RLC A SUBB A,ACC MOV R6,A MOV A,R7 ADD A,ACC MOV R7,A MOV A,R6 RLC A MOV DPL,R7 MOV DPH,A LCALL ?C?ILDOPTR MOV R7,A MOV R6,B SETB C SUBB A,maximum+01H MOV A,maximum XRL A,#080H MOV R0,A MOV A,R6 XRL A,#080H SUBB A,R0 JC ?C0003 ; SOURCE LINE # 12 MOV maximum,R6 MOV maximum+01H,R7 ; SOURCE LINE # 13?C0003: INC R5 CJNE R5,#010H,?C0001


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HC11 Assembly output; 7. for (a=0;a<16;a++) TSX LDD #-32768 STD 1,X CLR 0,X?0001: LDAA 0,X CMPA #16 BHS ?0000; 8. {; 9. if (array[a]>maximum) PSHY TAB CLRA LSLD TSX ADDD 0,X XGDX LDD 0,X TSX


STD 5,X INS INS CPD 3,X BLE ?0005; 10. maximum=array[a]; STD 3,X?0005: TSX INC 0,X BRA ?0001?0000:; 11. }; 12. return (maximum); LDD 1,X; 13. } PULX PULX INS PULY RTS

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PIC16C74 Assembly output bcf 3,5 movwf ?a_maxnum& (0+127);MAX_MAIN.C: 4: char a;;MAX_MAIN.C: 5: int maximum=-32768; clrf (?a_maxnum+2)& (0+127) movlw 128 movwf (?a_maxnum+3)& (0+127);MAX_MAIN.C: 7: for (a=0;a<16;a++) clrf (?a_maxnum+1)& (0+127)l2;MAX_MAIN.C: 8: {;MAX_MAIN.C: 9: if (array[a]>maximum) bcf 3,5 movf (?a_maxnum+1)& (0+127),w addwf (?a_maxnum+1)& (0+127),w addwf ?a_maxnum& (0+127),w movwf 4 movf 0,w movwf btemp incf 4 movf 0,w movwf btemp+1 movf (?a_maxnum+3)& (0+127),w xorlw 128 movwf btemp+2 movf btemp+1,w xorlw 128 subwf btemp+2,w btfss 3,2 goto u15 movf btemp,w


subwf (?a_maxnum+2)& (0+127),wu15 btfsc 3,0 goto l5;MAX_MAIN.C: 10: maximum=array[a]; bcf 3,5 movf (?a_maxnum+1)& (0+127),w addwf (?a_maxnum+1)& (0+127),w addwf ?a_maxnum& (0+127),w movwf 4 movf 0,w movwf (?a_maxnum+2)& (0+127) incf 4 movf 0,w movwf (?a_maxnum+3)& (0+127)l5;MAX_MAIN.C: 11: } bcf 3,5 incf (?a_maxnum+1)& (0+127) movlw 16 subwf (?a_maxnum+1)& (0+127),w btfss 3,0 goto l2;MAX_MAIN.C: 12: return (maximum); bcf 3,5 movf (?a_maxnum+3)& (0+127),w movwf btemp+1 movf (?a_maxnum+2)& (0+127),w movwf btemp return

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Some Conclusions on THIS Case• The C51 would have to run at 224 MHz to match the 8

MHz AVR.• The HC11 is quite code efficient, but delivers only one

16th of the processing power at more than twice the current consumption

• The PIC is a fast microcontroller, but the AVR delivers more than 3.5 times higher throughput per mW.

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What made the AVR do better?

• Excellent support for 16-bit arithmetic's. (Zero-Flag Propagation on Compare)

• A lot of registers which eliminate move to and from SRAM

• Single Cycle execution

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AVR Microcontrollers

Which AVR Devices are available today?

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Current AVR Product Line

‘S1200 ‘S2323 ‘S2343 ‘S2313 ‘S4414 ‘S8515 ‘mega103

FAMILY Classic Classic Classic Classic Classic Classic Mega

PINS 20 8 8 20 40/44 40/44 64

FLASH 1K 2K 2K 2K 4K 8K 128K

SRAM+REGs 0+32 128+32 128+32 128+32 256+32 512+32 4K+32

EEPROM 64 128 128 128 256 512 4K

UART - - - YES YES YES YES

PWMs - - - 1 2 2 4

ADC(10-bits) - - - - - - 8Ch

AVAILABLE NOW NOW NOW NOW NOW NOW NOW

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AVR Product Line cont.

‘S4434 ‘S8535 ‘S4433 ‘S2333 ‘mega161 ‘mega163 ‘mega603

FAMILY Classic Classic Classic Classic Mega Mega

EgaAVR

Mega

PINS 40/44 40/44 28/32 28/32 40/44 40/44 64


SRAM+REGs 256+32 512+32 256+32 128+32 1K+32 1K+32 4K

EEPROM 256 512 256 128 512 512 2K

UART YES YES YES YES YES YES YES

PWMs 3 3 1 1 4 4 4

ADC(10-bits) 8Ch 8Ch 6Ch 6Ch - 8Ch 8Ch

AVAILABLE NOW NOW NOW NOW 3Q00 3Q00 NOW

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AVR Product Line cont.‘tiny10/11 ‘tiny12 ‘tiny15 ‘tiny19 ‘tiny22 ‘tiny28 ‘tiny26

FAMILY Tiny Tiny Tiny Tiny Tiny Tiny Tiny

PINS 8 8 8 28 8 28 20


SRAM+REGs 32 32 32 32 128+32 32 64+32

EEPROM - 64 64 - 128 - 128

ISP NO YES YES NO YES NO YES

I/O’s 6 6 6 20 5 20 16

T/C 1 1 2 1 1 1 2

PWM - - 1 - - - 2

ADC(10-bits) - - 4Ch - - - 11Ch

AVAILABLE NOW 2Q00 2Q00 2Q00 NOW 2Q00 2Q00

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AT90S1200· World’s Highest Performance 8-bit MCU

· 20-pin Device

· 1 Kbytes ISP Flash

· 64 bytes ISP EEPROM

· 15 Programmable I/O lines

· 8-bit Timer Counter

· 1 External Interrupt

· Analog Comparator

· RC-Oscillator

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AT90S4414 / AT90S8515· 40-pin Device

· 4/8 Kbytes of ISP Flash

· 256/512 bytes of ISP EEPROM

· 256/512 bytes SRAM

· Full Duplex UART

· SPI-Serial Interface

· 8- and 16-bits Timer/Counter

· Dual PWM

· 2 External Interrupts


· Fast start up possibility

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AT90S2313 / AT90LS2313· 20-pin Device

· 2 Kb ISP Flash


· 128 bytes SRAM


· 16-bit Timer Counter with capture/compare

· Full Duplex UART

· Selectable 8, 9 or 10-bit PWM

· 2 External interrupts

· On Chip Analog Comparator

· Fast start up possibility

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AT90S2323 / AT90LS2323

· 8-pin Device



· 128 bytes SRAM

· 8-bit Timer/Counter0

· 1 External Interrupt

· 3 I/O Pins

· External Crystal Oscillator Only

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AT90S2343 / AT90LS2343· 8-pin Package



· 128 bytes SRAM

· 8 bit timer

· 5(4) I/O Pins Int. RC: 5 I/O pins + RESET, VCC and GND Ext. Clock: 4 I/O pins + RESET, XTAL1, VCC and GND

· External Clock or Internal RC Oscillator Selected with fuse

· Fast Wake-up

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AT90S4433/ AT90S2333

· 28 Pins package

· 4/2 Kb ISP Flash


· 256/128 bytes SRAM


· 16-bit Timer Counter with capture/compare/PWM

· Full Duplex UART

· 10-bit ADC with 6 Multiplexed Inputs

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AT90S4434 / AT90LS4434

• 40/44-pin Device• 10-bit ADC with 8 Multiplexed Inputs

• 3.6 - 14.3 ksamples/sec (Single Conversion Mode)

• 3.9 - 15.4 ksamples/sec (Free Running Mode)

• RTC with Separate 32 kHz Oscillator• Power Save Mode: Only RTC running <7 power consumption

• Functionally Equal to AT90S4414• New Pin-out to improve ADC noise immunity

• No External SRAM interface

• Port C pin order swapped

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AT90S8535 / AT90LS8535

• 40/44-pin Device• 10-bit ADC with 8 Multiplexed Inputs

• 3.6 - 14.3 ksamples/sec (Single Conversion Mode)


• RTC with Separate 32 kHz Oscillator• New Power Save Mode: Only RTC Running

• Functionally Equal to AT90S8515• New Pin-out to improve ADC noise immunity

• No External SRAM interface

• Port C pin order swapped

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ATmega103 / ATmega103L• 64-pin Device (48 I/O, 16 Special Function)

• 128 Kbytes ISP Flash

• 4Kbytes SRAM

• 4Kbytes EEPROM

• 10-bit ADC with 8 Multiplexed Inputs• 3.3 - 13.3 ksamples/sec (Single Conversion Mode)


• Separate 32 kHz Oscillator with RTC• Power Save Mode: Only RTC running <7 power consumption

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ATmega603 / ATmega603L• 64-pin Device (48 I/O, 16 Special Function)

• 64 Kbytes ISP Flash

• 4Kbytes SRAM

• 2Kbytes EEPROM




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ATmega161 / ATmega161L• 40/44-pin Device

• 16 Kbytes ISP Flash with Optional Boot Sector for Self-programming of program and data memories.

• 1Kbytes SRAM

• 512bytes EEPROM


• On-Chip 2cycle Multiplier• 4 ch PWM, Dual UART and SPI• Programmable Brown-Out detection circuit

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ATmega163 / ATmega163L• 40/44-pin Device

• 16 Kbytes ISP Flash with Optional Boot Sector for Self-programming of program and data memories.

• 1Kbytes SRAM & 512bytes EEPROM




• On-Chip 2cycle Multiplier • 4 ch PWM, Dual UART and SPI• Programmable Brown-Out detection circuit

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Tiny 10/11

· 8 Pins package

· 1 Kb ISP Flash


· 1 external interrupt



· Wake up on pin change

· Ultra low cost OTP version(Tiny10)

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Tiny 12/12L/12V· 8 Pins package· 1 Kb ISP Flash· 64B On-chip EEPROM· 6 Programmable I/O lines· 1 external interrupt· 8-bit Timer Counter· Analog Comparator· Wake up on pin change· Internal Calibrated RC oscillator

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Tiny 15/15L

· 8 Pins package & 6 Programmable I/O lines

· 1 Kb ISP Flash & 64B On-chip EEPROM

· Two 8-bit Timer Counter & 150KHz High speed PWM

· 4Ch 10bit ADC (One differencial Input with Optional Gain of 20x) & Analog Comparator

· Internal 1.6MHz Tuneable oscillator

· Programmable Brown-Out detection circuit

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Tiny 22/22L

· 8 Pins package

· 2 Kb ISP Flash

· 128B SRAM & EEPROM


· 1 external interrupt


· Wake up on pin change

· Selectable On-chip RC oscillator

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Tiny 26/26L· 20 Pins package

· 2 Kb ISP Flash, 64B SRAM & 128B EEPROM


· 8-bit Timer Counter & 2Ch High speed PWM

· External interrupt & Pin change interrupt on 8 pins

· Internal Calibrated RC oscillator

· Programmable Brown-Out detector

· 10-bits ADC

- 11 single ended, 6 differential ADC channels

- 2 differential ADC Channels with Optional Gain of 20x

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AVR Road Map

What will we see in the near future?

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The Three AVR Families

• megaAVR ATmegaXXX ( 16kB - 128 kB)• Targets complex applications with requirements for large program memories

• classicAVR AT90XXXX ( 1- 8kB )• Targets medium-range applications where high throughput and low power is

important

• tinyAVR ATtinyXX ( 1 - 2kB )• Targets cost-sensitive applications in the very low end of the 8-bit MCU mar

ket

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AVR PRODUCT ROADMAP: 1998

DEVICE COMPLEXITY

FL

AS

H D

EN

SIT

Y

megaAVR FAMILY

16KB TO 128KB

classicAVR FAMILY

1KB TO 8KB

tinyAVR FAMILY

1KB & 2KB

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tinyAVR applications

• Automotive low-end control applications

• Toys

• Games and Game-Cards

• PC Motherboard Connector Control

• Security Controller for mobile Phones (SIS Code)

• Battery Chargers

• Communication IF controllers

• White and Brown Goods

• Smoke Detectors

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classicAVR applications

• PC Modems

• Cable Modems

• Battery Chargers (advanced)

• Smart Cards and Smart Card Readers

• Tool Road Pay Tags

• Set-top Boxes

• Pay-TV Decoders

• Various Industrial Control Applications

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megaAVR applications• Analog Mobile Phones (NMT, ETACS, AMPS, and D-AMPS)

• Digital Mobile Phones (GSM and CDMA)

• Printers and Printer Switches/Controllers

• Fax Controller

• Disk Drive Controllers

• CD-ROM Controllers

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In-System Programmable Flash and EEPROM

Now Offered on an MCU by a technology leader in Non-Volatile

memories

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This is ISP Flash and EEPROM

5-wireserial programminginterface

Your device sits in the application. It is clocked fromthe application clock, and VCC can be as low as 2.7V.

Now, with four logical signals + Ground, you canREPROGRAM THE FLASH AND THE EEPROM

NO +12V PROGRAMMING VOLTAGE REQUIRED!

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Just Imagine...• No OTP parts thrown away

• No 5-minute UV erase time

• No sleepless nights after mask tape-out

• No stocking of multiple system versions

• No surprises in moving from OTP to mask

• No 10-week lead time

… instead ...

• Easy update of new features

• Easy bug fix

• Easy testing

• Easy in-line calibration

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AVR for ASIC

• RTL softcore enables a varity of processes• RTL for Standard I/O modules• AVR ASIC ICE available with reference designs• AVR ASIC handbook• Ready to go NOW !

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…Industry’s Highest 8-bit Performance

…Low Power Consumption

…a broad Family of MCUs

…a Variety of Peripherals

…excellent C Language Code Density

…In-System Programmable Flash and EEPROM

The AVR Offers...

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Instruction Set & Architecture

A Guided Tour Through the

Architecture, Instruction by Instruction

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Instruction Set General Features

• All Instructions (with a few exceptions) are 16 Bits Wide

• Most Instructions are Executed in One Clock Cycle

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Instruction Classes

• Arithmetic/Logic Instructions

• Data Transfer Instructions

• Program Control Instructions

• Bit Set/Test Instructions

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Arithmetic/Logical Instruction

• Add / Increment• Subtract / Decrement• Compare• Logical (AND, OR, XOR)• Shift / Rotate

All True Single Cycle

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Add Instructions

• “ADD” Add Two Registers

• “ADC” Add Two Registers and Carry

• “INC” Increment a Register

• “ADIW” Add Immediate to Word *

* Works on the 4 Uppermost Register Pairs

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Subtract Instructions

• “SUB” Subtract Two Registers• “SBC” Subtract with Carry Two Registers• “SUBI” Subtract Immediate from Register*• “SBCI” Subtract with Carry Immediate

from Register*• “DEC” Decrement Register• “SBIW “ Subtract Immediate From Word**

* Works on Registers R16 - R31** Works on the 4 Uppermost Register Pairs

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Executing “subi r16,k”

Register File

Immediate OperandInstruction

Instruction Word

ALU

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Compare Instructions

• “CP” Compare Two Registers

• ”CPC” Compare with Carry Two Registers

• “CPI” Compare Register and Immediate*

• “CPSE” Compare Two Registers and Skip Next Instruction if Equal

* Works on Registers R16 - R31

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16/32-Bit Data Support

• Single Cycle Execution• A Register File That Holds Several 16/32-Bit Values• Carry and Zero Flag Propagation on Subtract and

Compare

The AVR Supports Code and Time Efficient 16and 32-bit Arithmetic's Through the Following:

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Subtract Two 16-Bit ValuesWithout Zero Flag Propagation

R1:R0 - R3:R2 ($E104 - $E101)

R1 R0

E1sub r0,r2 03

Z

0

sbc r1,r3 0300

E1 04 X

1 Wrong!

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Subtract Two 16-Bit ValuesWith Zero Flag Propagation

R1 R0

E1sub r0,r2 03

Z

0

sbc r1,r3 0300 0

E1 04 X

Correct!

R1:R0 - R3:R2 ($E104 - $E101)

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Compare Two 32-Bit Values

cp r0,r4cpc r1,r5cpc r2,r6cpc r3,r7

At the end, the Status Register Indicates Equal,Higher, Lower, Greater (signed), Less Than (signed).Besides, it takes only 4 instructions and 4 clockcycles to do it...

Example: Compare R3:R2:R1:R0 and R7:R6:R5:R4

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Logical Instructions

• “AND” Logical AND Two Registers

• “ANDI” Logical AND Immediate and Register *

• “OR” Logical OR Two Registers

• “ORI” Logical OR Immediate and Register *

• “EOR” Logical XOR Two Registers

* Works on Registers R16 - R31

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Shift / Rotate Instructions

• “LSL” Logical Shift Left

• “LSR” Logical Shift Right

• “ROL” Rotate Left Through Carry

• “ROR” Rotate Right Through Carry

• “ASR” Arithmetic Shift Right

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Shift / Rotate Operations

LSR

Register Carry

0

MSB LSB

ROR

ASR

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Data Transfer Instruction Types

# of Cycles

• Data SRAM Register File (2)

• Program Memory Register File (1/2)

• I/O Memory Register File (1)

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The 5 Memory Areas

• General Purpose Register File 32 Bytes• Flash Program Memory 8 MB• SRAM Data Memory 8 MB• I/O Memory 64 Bytes• EEPROM Data Memory 8 MB

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Memory InterconnectionsProgram Memory Register File SRAM

I/O Memory EEPROM

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AVR Pointer StructureR0R1R2R3

R26R27R28R29R30R31

Register File

X Pointer

Y Pointer

Z Pointer

XLXHYLYHZLZH

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Data SRAM Register FileInstructions

• “LD Rd,<PTR>” Load Indirect

• “LD Rd,<PTR>+” Load Indirect with Post-Increment

• “LD Rd,-<PTR>” Load Indirect with Pre-Decrement

• “LDD Rd,<PTR>+q”Load Indirect with Displacement (0-63)*

• “LDS Rd,<ADDR>“ Load Direct from SRAM (16-bit ADDR)**

* PTR =X, Y or Z** Parts with SRAM > 64k bytes, memory page selected

using the RAMPZ register

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Data SRAM Register FileInstructions

• “ST <PTR>,Rd” Store Indirect

• “ST <PTR>+,Rd” Store Indirect with Post-Increment

• “ST -<PTR>,Rd” Store Indirect with Pre-Decrement

• “STD <PTR>+q,Rd” Store Indirect with Displacement (0-63) *

• “STS <ADDR>,Rd” Store Direct from SRAM (16-bit ADDR)**

* PTR = X, Y or Z** Parts with SRAM > 64k bytes, memory page selected

using the RAMPZ register

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Move 16 Bytes SRAM RF...

.def temp=r16 ;temporary storage register

.def cnt=r17 ;loop counter

ldi ZH,high(SRAM_LOCATION) ;init Z pointerldi ZL,low(SRAM_LOCATION)clr YH ;init Y pointerclr YLldi cnt,16 ;init loop counter

loop: ld temp,Z+ ;get data from SRAMst Y+,temp ;store data in RFdec cnt ;decrement counterbrne loop ;loop more if not done

Example:

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… and Store Back

ldi cnt,16 ;init loop counterloop: ld temp,-Y ;get data from RF

st Z-,temp ;store data in SRAMdec cnt ;decrement counterbrne loop ;loop more if not done

Example (Continued):

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Data Transfer RF SRAM Stack Instructions

• “PUSH” PUSH a register on the stack

• “POP” POP a register from the stack

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Data Transfer Prog. Memory RF Instructions

• “LDI”Load a Register with an Immediate Value (1 Cycle) *

• “LPM” Transfer a byte from Program Memory@Z to R0 (2 Cycles) **

* Works on R16 - R31, ** Available on parts with SRAM, only

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The LPM Instruction

Z PointerMSB LSB

Selects Program Memory Address SelectsLow/High Byte

The byte pointed to by Z is transferred to R0

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Register File I/O Memory Transfer Instructions

• OUT Transfer a Byte from RF to I/O• IN Transfer a Byte from I/O to RF

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Program Control Instruction Types

• Unconditional Jumps

• Conditional Branches

• Subroutine Call and Returns

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Unconditional Jump Instructions

• “RJMP” Relative Jump *• “JMP” Absolute Jump **• “IJMP” Indirect Jump to Program

Location@Z

* - Reaches 2K instructions from current program location. - Wrap-around** 4-Byte Instruction

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Instruction Fetch/Execution

Fetch

Execute

T1

INSTR n+1

T2

INSTR n+2

INSTR n+1INSTR n

Instructions are Sequential

INSTR n+3

INSTR n+2

T3

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Instruction Fetch/Execution

Fetch

Execute

T1

INSTR n+1

INSTR n

One Instruction is a Jump

T2

INSTR m

INSTR n

Reject

T3

INSTR m+1

INSTR m

(Jump to m)

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Conditional Branch Instructions (Flag Set)

• “BREQ” Branch if Equal

• “BRSH” Branch if Same or Higher

• “BRGE” Branch if Greater or Equal (Signed)

• “BRHS” Branch if Half Carry Set

• “BRCS” Branch if Carry Set

• “BRMI” Branch if Minus

• “BRVS” Branch if Overflow Flag Set

• “BRTS” Branch if T Flag Set

• “BRIE” Branch if Interrupt Enabled

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Conditional Branch Instructions (Flag Clear)

• “BRNE” Branch if Not Equal

• “BRLO” Branch if Lower

• “BRLT” Branch if Less Than (Signed)

• “BRHC” Branch if Half Carry Clear

• “BRCC” Branch if Carry Clear

• “BRPL” Branch if Plus

• “BRVC” Branch if Overflow Flag Clear

• “BRTC” Branch if T Flag Clear

• “BRID” Branch if Interrupt Disabled

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The Status Register - SREG

I

T

H

S

V

N

Z

C

Interrupt Enable

T Flag

Half Carry

Signed Flag

Overflow Flag

Neagative Flag

Zero Flag

Carry Flag

Enables Global Interrupts when Set

Source and Destination for BLD and BST

Set if an Add/Sub. has Carry between Bits 4&3

Set if an Add/Sub Results in Signed Overflow

Set if a Result is Negative

Set if a Result is Zero

Set if an Add/Subtract has Carry

Used for Signed Tests

7

0

TT Flag Source and Destination for BLD and BST

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Branch on SREG Settings

I

T

H

S

V

N

Z

C

BRID

BRTC

BRHC

BRGE

BRVC

BRPL

BRNE

BRSH, BRCC

BRIE

BRTS

BRHS

BRVS

BRMI

BREQ

BRCS, BRLO

BRLT

7

0

Branchesif Bit Set

Branchesif Bit Clear

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Subroutine Call and Return Instructions

• “RCALL” Relative Subroutine Call *• “CALL” Absolute Subroutine Call **• “ICALL” Indirect Subroutine Call to

Routine @Z• “RET” Return from Subroutine• “RETI” Return from Interrupt

Routine

* - Reaches 2K instructions from current program location - Wrap-around** 4-Byte Instruction

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Bit Set and Bit Test Instructions

• “SBR” Set Bit(s) in Register *• “SBI” Set Bit in I/O Register **

• “SBRS” Skip if Bit in Register Set• “SBIS” Skip if Bit in I/O Register Set **

* Works on Registers R16 - R31** Works on I/O Addresses $00 - $1F

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Bit Clear and Bit Test Instructions

• “CBR” Clear Bit(s) in Register *• “CBI”Clear Bit in I/O Register **

• “SBRC” Skip if Bit in Register Clear• “SBIC” Skip if Bit in I/O Register Clear **

* Works on Registers R16 - R31** Works on I/O Addresses $00 - $1F

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Interrupt System and

Sleep Modes

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Interrupt System Features

• Short Response Time (4 Clock Cycles + RJMP to Routine)• Automatic Interrupt Flag Clearing• Automatic Disable of Other Interrupts Inside the Interrupt

Routine

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Interrupt Vector Example

$0000 rjmp RESET ;Reset Vector$0001 rjmp IRQ0 ;IRQ0 Vector$0002 rjmp IRQ1 ;IRQ1 Vector

IRQ0: ;IRQ0 Routine$0003 <opcode>$0004 <opcode>

…$xxxx <opcode>$xxxx reti ;Ret. from Interrupt

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Executing an Interrupt

$0123 mov r16,r0$0124 add r20,r0$0125 adc r21,r1$0126 lsl r0$0127 clc




Interrupt


• “lsl r0” is Completed• $0127 is Pushed onto the Stack• The Interrupt Flag is Cleared• The I-bit in SREG is Cleared• The Program Jumps to the IRQ Vector

Episode 1, Interrupt in the Main Program

4 Clock Cycles

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Executing an Interrupt

$0000 RJMP RESET$0001 RJMP IRQ0$0002 RJMP IRQ1

IRQ0:$0003 in r0,PINB$0004 out PORTD,r0$0005 reti

Episode 2, The Interrupt Vector and Routine






IRQ0:$0003 in r0,PINB$0004 out PORTD,r0$0005 retiReturn



• The I-bit in SREG is Set• $0127 is Popped of the Stack• Program Execution Resumes from $0127

;Reset Vector;IRQ0 Vector;IRQ1 Vector;IRQ0 Routine

;Ret from IRQ0

4 Clock Cycles

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Sleep Modes

• Idle Mode

• Power Down Mode

Sleep Mode is entered by executing the “SLEEP”Instruction with the “SE” Bit in the “MCUCR”Register Set.

If the “SM” Bit in “MCUCR” is set, the MCU enters Power Down Mode when “SLEEP”is executed

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Idle Mode

• CPU is Stopped• XTAL Oscillator Runs• Timer/Counters and other Peripherals Operate• Reset + All Enabled Interrupts Can Wake Up the MCU

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Power Down Mode

• CPU is Stopped• XTAL Oscillator is Stopped• Timer/Counters and Other Peripherals are Stopped• Internal RC Oscillator Runs if the Watchdog is

Enabled. • Reset + External Level Interrupt Can Wake up the

MCU

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Power Save Mode

• CPU is Stopped• XTAL Oscillator is Stopped• Timer 2 is clocked asynchronously

– Optimized for external 32.768 Khz crystal

• Power consumption < 7uA@5V

• Easy Real Time Clock implementation

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Wake-Up from Sleep Mode

• RESET: The MCU Starts Execution from the Reset Vector

• INTERRUPT: The MCU Enters the Interrupt Routine, Runs it and Resumes Execution from the Instruction following “SLEEP”.

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Peripherals

I/O Ports

Timer/Counters

Comparator

Watchdog

UART

A/D converter

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I/O Ports General Features

• Push-Pull Drivers• High Current Drive (sinks up to 40 mA)• Pinwise Controlled Pull-Up Resistors• Pinwise Controlled Data Direction• Fully Synchronized Inputs• Three Control/Status Bits per Bit/Pin• Real Read-Modify-Write

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3 Control/Status Bits per Pin

• DDx Data Direction Control Bit• PORTx Output Data or Pull-Up Control Bit• PINx Pin Level Bit

X = A, B, C, ...

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Default ConfigurationDDx

PORTx

PINx Physical Pin

Pull-Up

Direction: INPUTPull-Up: OFF

??

0

0

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Switch On Pull-UpDDx

PORTx

PINx Physical Pin

Pull-Up

Direction: INPUTPull-Up: ON

??

0

111

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Port is OutputDDx

PORTx

PINx Physical Pin

Pull-Up

Direction: OUTPUTPull-Up: OFF

11

1

11

11

1

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Why Three Addresses?

A Two-address Port means NOREAL Read-Modify-Write

Why not let WRITE PORTx write the LATCHand

READ PORTx read the PINS?(just like Microchip, Hitachi, Motorola...)

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The Two-Address Problem

• I/O Type: PORTx Reads the Pinand Writes the Latch

• Configuration:Some PORTx Pins are Outputs, Others are Inputs,Inputs Have Pull-Ups on

• Software Task: Set One of the Output Pins

PROBLEM!

Example:

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The Two-Address Problem (Continued)

• Setting an I/O Pin is Done Like This:– Read PORTx (Read)– OR With All Zeros Except Bit to be Set (Modify)– Write PORTx (Write)

• If the Signal on an Input Pin is Low When PORTx is Read...

Write Back WILL TURN OFF THE PULL-UP.

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From the PIC16C64 Datasheet:“Reading the PORT register, reads the values of the PORT pins.Writing to the PORT register writes the value to the PORTB latch.When using read modify write instructions (ex. BCF, BSF, etc.) ona PORT, the value of the PORT pins is read, the desired operation isdone to this value, and the value is then written to the PORT latch”.”…

“…care must be exercised if a write followed by a read operation iscarried out on the same I/O port. The sequence of instructions shouldbe such to allow the pin voltage to stabilize (load dependent) before thenext instruction … otherwise, the previous state of that pin may be readinto the CPU rather than the new state … it is better to separate theseinstructions with a NOP or another instruction not accessing this I/O port.”

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From HITACHI’s H8/300 Programming Manual:

“BSET, BCLR, … are read-modify-write instructions. They read abyte of data, modify one bit in the byte, then write the byte back.Care is required when these instructions are applied to registerswith write-only bits and to the I/O port registers.”…

“Programming Solution: The switching of the pull-ups can beavoided by storing the same data both in the port data registerand in a work area in RAM”

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Timer/Counters

• Timer/Counter0 - 8 Bit



Standard AVR Timer/Counter Modules

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General T/C Features

• Clock Prescaling Options: 1, 8, 64, 256, 1024• Can Run at Undivided XTAL Frequency (High Resolution)• Can be Set to Any Value at Any Time• Can be Clocked Externally by Signals with Transition Perio

ds down to XTAL/2• Can be Clocked Externally on both Rising and Falling Edge.

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Timer/Counter0

• 8-Bit

• Overflow Interrupt

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T/C0 Block Diagram

8-Bit Timer/Counter

Timer Interrupt MaskRegister (TIMSK)

Timer Interrupt FlagRegister (TIFR)

Control Logic

Dat

a B

us

T/C0 Control Register(TCCR0)

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Timer/Counter1

• 16-Bit


• Output Compare Function with Interrupt

• Input Capture with Interrupt and Noise Canceler

• 10, 9 or 8-Bit PWM Function

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T/C1 Block Diagram

16-Bit Timer/Counter



Control Logic

Dat

a B

us

T/C0 Control Register B(TCCR1B)

T/C0 Control Register A(TCCR1A)

Timer/Counter1 OutputCompare Reg. (OCR1) 16-Bit Comparator

Input Capture1 Register (ICR1)

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Timer/Counter2

• 8-Bit


• Output Compare Function with Interrupt

• 8-Bit PWM Function

• Real Time Clock function

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T/C2 Block Diagram

8-Bit Timer/Counter



Control Logic

Dat

a B

us

T/C2 Control Register(TCCR2)

Timer/Counter2 OutputCompare Reg. (OCR2)

8-Bit Comparator

Asynch. Status Register(ASSR)

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Output Compare Features

• Compare match can control an external pin (Rise, Fall or Toggle) even if the Interrupt is disabled.

• As an option, the timer can be automatically cleared when a compare match occurs.

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Input Capture Features

• Capture Can Trigger on Rising or Falling Edge (Optional)

• The Input Capture Noise Canceler will not trigger the Capture until 4 Subsequent samples of the same value are seen.

The Noise Canceler is Optional

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PWM Features

• Selectable 10, 9 or 8-Bit Resolution.

• Frequency @ 10 MHz (8-bit): 19 KHz

• Centered Pulses

• Glitch-Free Pulse Width Change

• Selectable Polarity

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PWM OperationTimerValue

CompareValue 1

PWMOutput 1

CompareValue 2

PWMOutput 2

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Analog Comparator Features

• Comparator has its own Interrupt on Output Transitions

• Interrupt has selectable trigger on Rise, Fall or Toggle• The Comparator Output can be Connected to the Input

Capture of Timer/Counter1– Enables Pulse-Width Measurement of Analog Signals

– Enables Easy Implementation of Dual Slope ADC

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A/D Converter• Succesive Approximation A/D

• 10 Bit resolution

• 1/2 LSB Accuracy

• 65-260 uS conversion time

• 8 Multiplexed input channels

• Interrupt on AD conversion complete

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A/D converter

ADC Control and Status Register(ADCSR)

ADC dataregister (ADCH/ADCL)

Succesive approximation logic

Dat

a B

us

ADC multiplexer select(ADMUX)

10-bit DAC

8-Channel

Mux

Analog input

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Watchdog

• Clocked from Internal 1 MHz R-C Oscillator

• Time-Out Adjustable 16 - 2048 ms.

• Watchdog Timer Reset is done by executing the “WDR” instruction

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UART Features• Full Duplex• 8 or 9 Data Bits• Framing Error Detection• False Start Bit Detection• Noise Canceling• High BAUD Rates at low XTAL Frequencies

E.g. 115,200 Baud at 1.8432 MHz• Can run at Practically any Baud Rate• Three Interrupts with Separate Vectors

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Development Tools

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Development Tools Overview• ANSI compliant C Compiler

• Macro-Assemblers

• Linker/Librarian

• Debugger/Simulator

• RTOS

• In-Circuit Emulator

• Evaluation boards

• Programmers

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Easy to use MS-Windows interface Unlimited number of Breakpoints Trace buffer

Logic analyzer interface

External trigger inputs/outputs

Reconfigurable I/O

In-Circuit Emulator

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Event Memory

• Breakpoints– Eight different Breakpoints for each location– Break mask register

• Control– Two bits for trace control– Three bits for external triggers– Three bits for auxillary use

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Trace buffer

• Control in Event memory– Trace on, Trace off, Toggle, No action

• 32K deep

• 96 bit wide

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Connectors

• Two connectors for logic analyzer– Program memory address (20 bit)

– Program memory data (16 bit)

– Clock

• Auxillary connector– Trigger inputs

– Trigger outputs

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AVR Studio

• Easy to Use MS-Windows interface • Controls the AVR In-Circuit Emulator• Uses AVR Simulator if AVR ICE not present• C and Assembly source level debugging• Reads different object formats, including UBROF

from IAR development tools

• Project information

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AVR Studio Source View

• C and Assembly display

• Toggle execution level

• Breakpoints insertion and removal

• Run to cursor

• Module selection

• Source code search

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AVR Studio Symbol Watch

• Maintains scope information

• Binds watches automatically

• Simple variables

• Arrays, Structs, Unions and Pointers

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AVR Studio Register View

• Simple window to view register contents

• Registers can be modified when execution is stopped

• Red colour on active registers

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AVR Studio Memory View

• SRAM, Program Memory, EEPROM and I/O• Various representations• Modifications possible when execution stopped

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AVR Studio Processor View

• Displays essential information about debug target

• Values modifiable when execution stopped

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AVR Studio I/O Views

• Specialized views for I/O devices– Timer

– UART

– Port

– SPI

– Analog Comparator

– EEPROM

– ADC

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Fully ANSI compliant C Compiler

Built-In AT90S specific optimizer

Includes Embedded Workbench

Assembler, Librarian and Linker

C And Assembly level debugger

Windows-95, Win 3.11, Windows NT and DOS

IAR Development Tools for

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Chip Specific Extensions• Initialization function for Hardware setup• Special Function Register (SFR) for I/O access• Interrupt functions • Monitor functions for critical regions• Routines for accessing Flash• Intrinsic functions:

– SEI, CLI, NOP, OPC, LPM, SLEEP, WDR

• EEPROM access routines – EEPUT, EEGET

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Example: SFR / Intrinsics

sfrb MCUCR = 0x35;

sfrb GIMSK = 0x3B;

int __low_level_init(void)

{

GIMSK = 0xC0; /* Enable ext interrupts */ MCUCR = 0x0F; /* Extern int on ris edge */ _SEI();

/* Enable interrupts */

return(1);

}

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Example: Interrupts

interrupt[TIM1_CAPT_vect] void tim1capt(void)

{

int uCapture;

uCapture = ICR1 ;

if(uCapture > CONST)

{

…

}

}

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Example: Monitor functions

monitor int P(char *flag)

{

if(!*flag)

return(*flag = 1);

else

return(0);

}

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AVR Development Tools

• Complete development tools package

• State-of-the-art graphical user interface

• Effective C Compiler and processor core results in compact code

• Compiler well suited for embedded applications

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Hands On Training

Using the AVR Assembler

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Assembly vs. C

• Full control of Resource Usage

• Compact and fast code in small applications

• Inneffecient code in larger applications

• Cryptical code

• Hard to maintain

• Non-portable

• Limited control of Resource usage

• Larger/slower code in small applications

• Efficient code in larger applications

• Structured code

• Easy to maintain

• Portable

Flash MCU

Assembler exercise 1

• Write a assembler program that reads input on the serial port and send it as hex value to the LEDS

• Store the data in SRAM until LF(Line Feed) is pressed (0x0A)

• Convert the data to capital letters and send them on the serial port

• EXTRA: Write “WORKSHOP” on the serial port after RESET (Tip: use LPM)

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Hints and tricks

• Remember to initalize interrupt vectors and stack pointer

• Clear high byte of Z pointer

• Data from PC ends with CR(0x0D) and LF(0x0A)

• Subtract 0x20 to convert to uppercase

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Main ProgramSet up interrupt vectors

Init stack pointer

Set PORTB as output

Set baud rate = 9600 @ 4Mhz crystal

Enable UART receive and interrupt

Init Z pointer to RAM address 0x0060

Enable global interrupt

loop: goto loop

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Interrupt FunctionsUART_RX:

Store status register

Read UART data register

Output data to port B

If data register not = LF

Store data in RAM

Increment Z pointer

Else

Store LF and CR in RAM


Enable UART Transmit and interrupt

Restore status register

Return

UDRE_empty:

Store status register

Read data from RAM

Increment Z pointer

If Z data not = LF

Convert to capitol letters

Send data to UDR

Else

Send LF to UDR


Enable UART Receive and interrupt

Restore status register

Return

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Exercise 2

• Convert the program to the IAR assembler

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AVR assembler IAR assembler.CSEG

.equ label = expression .equ const = 0x50

.def symbol = register .def temp = R16

.include “8515def.inc”

Program address is word

.ORG $0005

NAME routine

#define label expression-#define const 0x50

#define symbol register#define temp R16

#include “io8515.h”

Program address is byte

ORG $0005*2

END

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Optimized for High Level Languages

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High Level Languages• Increased importance for Microcontrollers

– Time to market

– Simplified maintenance

– Portability

– Learning time

– Reusability

– Libraries

• Potential drawbacks– Increased codesize

– Decreased speed

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AVR Architecture and Instruction Set influenced by IAR

• Compiler development project initiated before Architecture / Instruction Set frozen

• Potential Bottlenecks identified and removed • IAR feedback reflected in Hardware• Several iterations• Result of modifications frequently observed in

generated code

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C-like Addressing Modes

C Source

unsigned char *var1, *var2;

*var1++ = *--var2;

Generated code

LD R16,-X

ST Z+,R16

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Indirect with Displacement

• Effective for accessing arrays and structs• Autos placed on Software Stack

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Four memory pointers

• Memory to memory copy

• Minimize pointer reloading

• High functionality

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16 and 32 bit support

• Carry instructions– Addition and Subtraction

– Register with register

– Register with immediate

– Zero flag propagation

SUB R16,R24 SUBI R16,1

SBC R17,R25 SBCI R17,0

All branches can be made based on last result

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16 Bit instructions

• Additions and Subtractions of small values

• Ideal for index variables and pointer manipulations

• Software Stack

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Non-destructive comparison

• Compare with carry instruction

• Zero propagation

• No restoring necessary

• All conditional branches available

CP R16,R24

CPC R17,R25

CPC R18,R26

CPC R19,R27

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Switch Support

• Switches very frequently used by CASE tools

• Straight forward approach inefficient and time differentiating

• Indirect jumps well suited for compact switch constructions

• General library routines manages switches

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Compiler Features

• Fully compatible with the ANSI standard• All required data types supported• Fully reentrant code• General optimizations• AVR specific optimizations• AVR specific extensions

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Optimization• Code and Speed optimization• C and Assembly level optimizations

– Algebraic identities

– Common subexpression elimination

– Removal of branch chains

– Condition reversal

– Constant folding

– Register allocation

– Bit operations

– Peephole optimizations

– Cross jumping and hoisting

– Removal of unreachable code

– Redundant assignment removal

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Summary• AVR Architecture originally designed with High

Level Languages in mind• Cooperation between Atmel and IAR on Architec

ture and Instruction Set tuning• Resulting Compiler generates highly efficient cod

e• Incorporated changes frequently exploited in gene

rated code

flash mcu workshop atmel korea. flash mcu workshop goals detailed architecture knowledge hands on...

Documents

mov r5

h mov maximum

mov dpl

0x195 mov

xad mov

maximum mov r7

r6 mov maximum

h mov r0