finite state machines discussion d8.1 example 36
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Finite State Machines
Discussion D8.1
Example 36
Canonical Sequential Network
Sta
te R
egis
ter
Com
bina
tion
alN
etw
ork
x(t)
s(t+1) s(t)
z(t)clk
init
present state
present input
nextstate
present output
Mealy Machine
Sta
te R
egis
ter
C1
x(t)
s(t+1)
s(t)z(t)
clk
init
present state
present input
nextstate
C2
Moore Machine
Sta
te R
egis
ter
C1
x(t)
s(t+1)
s(t)
z(t)
clk
init
present state
present input
nextstate
C2
VHDLCanonical Sequential Network
Sta
te R
egis
ter
Com
bina
tion
alN
etw
ork
x(t)
s(t+1) s(t)
z(t)clk
init
present state
present input
nextstate
present output
process(clk, init)
process(present_state, x)
VHDLMealy Machine
Sta
te R
egis
ter
C1
x(t)
s(t+1)
s(t)z(t)
clk
init
present state
present input
nextstate
C2
process(clk, init)
process(present_state, x)
process(present_state, x)
VHDLMoore Machine
Sta
te R
egis
ter
C1
x(t)
s(t+1)
s(t)
z(t)
clk
init
present state
present input
nextstate
C2
process(present_state, x) process(present_state)
process(clk, init)
ExampleDetect input sequence 1101
fsm
din
doutclk
clr
dindout
1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 00 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0
Use State DiagramDetect input sequence 1101
S00
S10
S110
S1100
S11011
11
0
1
0 10
0
1
0
CLR
fsm.vhd
fsm
din
doutclk
clr
entity fsm is port (clk: in STD_LOGIC; clr: in STD_LOGIC; din: in STD_LOGIC; dout: out STD_LOGIC); end;
fsm.vhd
architecture fsm_arch of fsm is type state_type is (S0, S1, S11, S110, S1101); signal present_state, next_state: state_type; begin
Sta
te R
egis
ter
C1
x(t)
s(t+1)
s(t)
z(t)
clk
init
presentstate
presentinput
nextstate
C2S
tate
Reg
iste
rC1
x(t)
s(t+1)
s(t)
z(t)
clk
init
presentstate
presentinput
nextstate
C2
clr
doutdin
synch: process(clk, clr) begin if clr = '1' then present_state <= S0; elsif clk'event and clk = '1' then present_state <= next_state; end if; end process;
fsm.vhd
Sta
te R
egis
ter
C1
x(t)
s(t+1)
s(t)
z(t)
clk
init
presentstate
presentinput
nextstate
C2
Sta
te R
egis
ter
C1
x(t)
s(t+1)
s(t)
z(t)
clk
init
presentstate
presentinput
nextstate
C2
clr
doutdin
fsm.vhdcomb1: process(present_state, din) begin case present_state is when S0 => if din = '1' then next_state <= S1; else next_state <= S0; end if; when S1 => if din = '1' then next_state <= S11; else next_state <= S0; end if;
S00
S10
S110
S1100
S11011
1 1
0
1
0 10
0
1
0
CLR
fsm.vhd when S11 => if din = '0' then next_state <= S110; else next_state <= S11; end if; when S110 => if din = '1' then next_state <= S1101; else next_state <= S0; end if; when S1101 => if din = '0' then next_state <= S0; else next_state <= S11; end if; when others => null; end case; end process;
S00
S10
S110
S1100
S11011
1 1
0
1
0 10
0
1
0
CLR
fsm.vhdcomb2: process(present_state) begin if present_state = S1101 then dout <= '1'; else dout <= '0'; end if; end process; end fsm_arch;
Sta
te R
egis
ter
C1
x(t)
s(t+1)
s(t)
z(t)
clk
init
presentstate
presentinput
nextstate
C2
Sta
te R
egis
ter
C1
x(t)
s(t+1)
s(t)
z(t)
clk
init
presentstate
presentinput
nextstate
C2
clr
doutdin
fsmx.vhd
fsm
clk_pulse
btn(3)
btn(1)
ld(0)
ld(7)din
doutclr
clk
fsmx
clkdivmclkcclk
btn(0)bn
ld(1)
fsmx.vhd
entity fsmx is
port(mclk : in STD_LOGIC;sw : in STD_LOGIC_VECTOR(7 downto 0);btn : in STD_LOGIC_VECTOR(3 downto 0);ld : out STD_LOGIC_VECTOR(7 downto 0);a_to_g : out STD_LOGIC_VECTOR(6 downto 0);dp : out STD_LOGIC;an : out STD_LOGIC_VECTOR(3 downto 0)
);
end fsmx;
fsmx.vhd
architecture fsmx of fsmx is component fsm port( clk : in std_logic; clr : in std_logic; din : in std_logic; dout : out std_logic); end component;
fsmx.vhd
component clock_pulseport(
inp : in std_logic;cclk : in std_logic;clr : in std_logic;outp : out std_logic);
end component;
signal clr, clk, cclk, bn: std_logic;
signal clkdiv: std_logic_vector(23 downto 0);
fsmx.vhd bn <= btn(1) or btn(0);
clr <= btn(3);
U0: clk_pulse port map
(inp => bn, cclk => cclk, clr =>clr, clk => clk);
U1: fsm port map
(clr =>clr, clk => clk, din => btn(1), dout => ld(7));
ld(0) <= BTN(0);
ld(1) <= BTN(1);
Detect input sequence 1101Moore Machine
Mealy Machine Sequence DetectorDetect 1101
s0 s1 s2 s31 / 0 1 / 0 0 / 0
0 / 0
0 / 01 / 0
0 / 0
1 / 1
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
egis
ter
C1
C2
Mealy State Machine
-- Example 36b: Detect 1101 with Mealy machinelibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity seqdetb is port (clk: in STD_LOGIC; clr: in STD_LOGIC; din: in STD_LOGIC; dout: out STD_LOGIC);end seqdetb;
architecture seqdetb of seqdetb istype state_type is (s0, s1, s2, s3);signal present_state, next_state: state_type;begin
s0 s1 s2 s31 / 0 1 / 0 0 / 0
0 / 0
0 / 01 / 0
0 / 0
1 / 1
sreg: process(clk, clr)begin if clr = '1' then present_state <= s0; elsif clk'event and clk = '1' then present_state <= next_state; end if;end process;
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
egis
ter
C1
C2
C1: process(present_state, din)begin case present_state is
when s0 => if din = '1' then next_state <= s1; else next_state <= s0; end if;when s1 => if din = '1' then next_state <= s2; else next_state <= s0; end if; when s2 => if din = '0' then next_state <= s3; else next_state <= s2; end if;when s3 => if din = '1' then next_state <= s1; else next_state <= s0; end if; when others => null;
end case;end process;
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
egis
ter
C1
C2
s0 s1 s2 s31 / 0 1 / 0 0 / 0
0 / 0
0 / 01 / 0
0 / 0
1 / 1
Seq2: process(clk, clr)begin if clr = '1' then dout <= '0'; elsif clk'event and clk = '1' then if present_state = s3 and din = '1' then dout <= '1'; else dout <= '0'; end if; end if;end process;end seqdetb;
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
egis
ter
C1
C2
s0 s1 s2 s31 / 0 1 / 0 0 / 0
0 / 0
0 / 01 / 0
0 / 0
1 / 1
Note that dout is a registered output
dout
Detect input sequence 1101Mealy Machine