finite element analysis attacks problems in … element analysis attacks problems in packaging –...
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Finite Element Analysis Attacks Problems in Packaging –
Is Secondary Education Ready?
William G. Daly, Physics TeacherCollins Hill High School
Gwinnett County Public Schools, Georgia
Summer Teacher Experience Program -Utilizing Physics at
Georgia TechJune 3 - July 26, 2013
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Abstract• For over 50 years, Moore’s law has driven an exponential growth in system capability and size reduction,
approximately doubling transistor density every 18 months, from about 1cm in the 1950’s to hundreds of atoms across today. Until recently, this advancement occurred in 2 dimensions, constructing integrated circuits on the top 20mm of silicon, by sometimes obvious and sometimes esoteric means. Along with density increases grew an enormous industry of semiconductor design, analysis and production tools to deal with the ever increasing challenges and complexities of these microscopic devices. At 200 atoms across it is obvious that the end of Moore’s law, at least in 2 dimensions, is not far off. So the drive continues to keep Moore’s law alive. An obvious advancement is to unconstrain the third dimension, stacking the 20mm layer within a single piece of silicon. Although this idea is not new, the challenges of doing so are immense, leaving 2 dimensional solutions an easier, more profitable pursuit. But as industry approaches the end of 2 dimensional densities, grappling with the issues of utilizing the third dimension seem more attractive. One area that must be dealt with is how to “drill” through each 20mm layer, creating Through Silicon Vias (TSVs) to get from one layer to the next. While the tooling to do so is challenging, the ability to create vias exists today, but not without technical hurdles in the finished product, not the least of which is a thermal expansion mismatch among the host semiconductor, insulator and conducting via. Evaluating this mismatch at such a microscopic level presents a challenge in analysis and measurement. One of focus in the Electromagnetic modeling, Packaging, Signal integrity, Integrated components Laboratory fOr Next generation systems (EPSILON) is modeling and analyzing electrical and mechanical interactions using finite element methods. A narrow slice of this effort is to evaluate commercial and open source Finite Element Modeling (FEM) software tools to model electrical and mechanical interactions at both the macroscopic and microscopic levels. The EPSILON group is concerned not only with packaging issues at the microscopic level, but also at the material system boundary, the antenna. Additional work was done to retrace processes for designing microstrip antennae for contemporary frequencies, in the neighborhood of 2GHz. It is hoped that an outgrowth of this effort will be introduction of technical challenges, opportunities, rudimentary analysis tools and projects in a pre-college academic setting.
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Introduction• Finite Element Analysis to Advance
– Antenna Design– Integrated Circuit Design
• A Few Tools of the Trade– COMSOL Multiphysics – proprietary FEA– * CST Microwave Studio – proprietary FEA– * Elmer – open source FEA– MATLAB– * Paraview – open source– * Express Schematic / PCB
* Used as part of my during STEP-UP 2013.
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Theory – Packaging
• How did we get from here (1987) …
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Theory – Packaging
• To here (2011) … Where’s the antenna?!?
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Theory – Packaging
• How do we get from here?Intel Ivy Bridge Proceesor4 Core Processor~ ½” on an edge~1.5 Billion Transistors< $200Feature dimensions ~ 100’s of atoms
Is Moore’s law nearing the end???
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Theory – Packaging
• To here?MotherboardOutline: 14.9” x 11.8” x 3.3” < $350
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Theory – Packaging• All of the Processor circuitry is in the top
layer of the silicon, epitaxial layer.
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Theory – Packaging• But this is a small fraction of the bulk silicon.
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Theory – Packaging• Next we have to put the silicon chip in a “box”.
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Theory – Packaging• Package mount into a ZIF socket.
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Theory – Packaging• Where is this on the motherboard?
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Theory – Packaging• If we scale active layer (epi) to the table top …
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Theory – PackagingIs Moore’s Law at an end?
• Can we increase density 2 . in silicon without changing the motherboard?– Extreme UV 100 atom features in 2015.– Yield issues with planar increase in die size.
• The 3rd Dimension is one answer.– Intels FINFET begins to go vertical– Maybe the chips could be stacked …
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Theory – Packaging3D Integrate Circuits
PCB ~ 1600m
• The epi layer accounts for < 0.2%of the PC board height.
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Theory – Packaging3D Integrate Circuits
PCB ~ 1600m
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Theory – Packaging3D – not without issues
• How do you get out the heat?• How do you interconnect the layers? • Through silicon vias (TSV)
• Drilled with eximer lasers or Deep Reactive Ion Etching• Vias filled with copper
• Copper has over 5X thermal expansion than silicon.
• Solid mechanics modeling of TSV: 𝜌𝜕 �̅�𝜕𝑡 − 𝛻 𝜎 = ̅𝑓
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Theory – PackagingTurn attention to antennas
• Circuit board transmission lines
• Stripline >$, but better containment of fields• But what if you do not want to contain the
fields?
Cu
Cu Ground
Cu Ground
FR4 InsulatorCu
Cu GroundFR4 Insulator
Stripline Microstrip
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Theory – PackagingDimensions for optimal resonance/ radiation
• For 50 impedance:
𝑍𝑜 =120𝜋
𝜖 𝑤𝑑 + 1.393 + 0.667𝑙𝑛 𝑤
𝑑 + 1.44• Rectangular patch dimensions:
𝐿 =1
𝑓 𝜖 𝜇 𝜖 − 2∆𝐿
𝑊 =2
2𝑓 (𝜖 + 1)𝜇 𝜖
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Theory – PackagingDesign Objectives
• Center frequency = 2GHz• Two port RF network – antenna has only one
transmission line port: 𝑠 𝑠𝑠 𝑠
• Minimize reflected power s11
• Return loss: 𝑅𝐿 = 20𝑙𝑜𝑔 𝑠 < -10dB
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Methodology –Optimize / Analyze Design with FEA
• Generic flow Computer Aided Design File (CAD)
Create/Refine Mesh
GMSH.exe
Convert Mesh
ElmerMesh.exe
Set Up Solver Parameters
ElmerGUI
Run Solver
ElmerGUI
Visualization
Paraview
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Methodology –Preliminary Antenna Design
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Methodology –Optimize Return Loss with Electromagnetic FEA
CST Microwave Studio
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Methodology –Model Far Field with Electromagnetic FEA
CST Microwave Studio
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Methodology –Customize Design
CST Microwave Studio
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Methodology –Customize Design
CST Microwave Studio
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Methodology –Return to TSV discussion
CAD Model and Mesh in GMSH (open source)
2D CAD Model Extrude / Define Facets Mesh
Define Cube Physical Volume Define Cylinder Physical Volume
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Methodology –Return to TSV discussion
CAD Model and Mesh in GMSH (open source)
2D CAD Model Extrude / Define Facets Mesh
Define Cube Physical Volume Define Cylinder Physical Volume
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Methodology –Completed Model
Facets Copper Silicon
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Results and Discussion –ELMER / Paraview
Solver Equation, Material Assignment, Boundary Conditions, Initial Conditions
Von Mises Stress with Improper selection of boundary conditions.
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Results and Discussion –ELMER / Paraview
Solver Equation, Material Assignment, Boundary Conditions, Initial Conditions
Simulation of Von Mises Stress for T = 145C
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Results and Discussion –ELMER / Paraview
• Eigen modes of circular membrane• The model
• The demonstration
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Results and Discussion –ELMER / ParaviewAntenna Implementation
• Antenna Fabrication– Requires $26000 VNA to test– Circuit on the right RSSI for
classroom use
• Collaborate with high school students for design and test:
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Results and Discussion –ELMER / Paraview
Return Loss of “Mickey Mouse” Antenna
0 1000000000 2000000000 3000000000 4000000000 5000000000 6000000000-40
-35
-30
-25
-20
-15
-10
-5
0
Return Loss of 2GHz Patch Antenna with Elliptical Pattern
Frequency (Hz)
S11(dB)
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Conclusion• Research objectives
– Succeeded in modeling TSVs with open source finite element software• Next steps
– Explore different geometries– Implement test configuration
– Designed, analyzed and tested 2GHz patch attenna• Next step is to complete RSSI circuit
• Classroom objectives– Discovered open source method of introducing FEA– Constructed “hands on” approach to demonstrating
FEA in project based activities
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Acknowledgements• Prof. Madhavan Swaminathan, John Pippin Chair in
Electromagnetics - Advisor• Mixed Signal Design Group Graduate Students - Mentors
– Munmun Islam– Kyu Hwan Han– Jianyong Xie
• Dr. Leyla Conrad, Outreach Director • Nirvana Edwards, Outreach Coordinator• Georgia Tech for support of the Step-Up Program • National Science Foundation for support of STEM initiative
grant # CMMI-1129918