Faculty of EngineeringGraduate Attributes Workshop 2013

ECE’s Adventures in Outcomes-based Learning

Grad Attributes and Grief

The Five Stages of Grief

1. Denial2. Anger3. Bargaining4. Depression5. Acceptance

ECE’s Coping Strategy

1. Grad Attributes ECE Committee (S. 2012)– End product: assignment of indicators to courses

2. Committee members visit instructors

3. Completion of rubrics

1. Formation of Grad Attributes Cte

• Consists of Departmental “stalwarts”Mohamed Bakr, Steve Hranilovoc, Nicola Nicolici, Tim Davidson, Jim Reilly

• Initially, we had very little idea how to implement this process. End result was:

1. Everyone learned how to construct a rubric• This process was greatly assisted by presentation from Marilyn LIghtstone

2. Mapping of indicators to courses

Topic: How it is measured Final exam, Q2(essay question)“Explain in words why it is desirable to bring the power factor of a load as close as possible to one

Student Numbers

Below Expectations Inadequate use of language to express power factor issues 1710.1%

Marginal

Can express the concept of power factor correction, but has difficulty in doing so. Expressions are unclear, inconcise and/or incomplete 3923.4%

Meets Expectations Is capable of generating a clear explanation of power factor concepts that is understandable to one knowledgeable in the field 9154.5%

Above Expectations Meets expectations +is capable of additional levels of clarity and conciseness

2012.0%

Course: EE2CI5 Introduction to Electrical EngineeringYear/Session: Fall, 2012Instructors: Alex Jeremic and Jim ReillyAttribute: Communication skillsIndicator: Constructs effective written arguments

Topic (used for measurements)

Below expectations

Marginal

MeetsExpectations

Exceeds Expectations

Design of a pipelined RISC CPU using Altera CAD tools

Does not understand the fundamental trade-offs between resource constraints, area and latency, e.g. design a CPU that is inefficient in performance and resource use

Understands the design trade-offs for the basic implementation of the CPU, however struggles with resource usage, constraints and pipelining

Is capable of allocating resources to reduce latency minimize hardware cost, and meet design constraints

“Meets expectations” plus: Is able to analyze and explain how the hardware architecture will scale with multithreading

% 10 did not meet expectations

% 10 were marginal

% 50 met expectations

% 30 exceeded expectations

MEASUREMENT RUBRIC FOR 4DM4 COURSE

Capable of selecting appropriate model and methods and identify

assumptions and constraints