evolution of sic mosfets at creeneil/sic_workshop... · sponsored in part by army research...

Brett Hull :: August 13, 2015

Evolution of SiC MOSFETs at CreePerformance and Reliability

© 2015 Cree, Inc. All rights reserved© 2015 Cree, Inc. All rights reserved

Brett Hull :: August 13, 2015

Dan Lichtenwalner, Vipin Pala, Edward VanBrunt, Sei-Hyung Ryu, Jim Richmond, Leo Wang, Philip Butler, DonGajewski, Scott Allen, John Palmour – Cree, Inc.

Christina DiMarino – CPES, Virginia Tech

2

Sponsored in part by Army Research Laboratory under Cooperative AgreementW911NF-12-2-0064

Acknowledgements

The information, data or work presented herein was funded in part by the Office ofEnergy Efficiency and Renewable Energy (EERE), U.S. Department of Energy, underAward Number DE-EE0006920.

The information, data, or work presented herein was funded in part by the Advanced ResearchProjects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DE-

© 2015 Cree, Inc. All rights reserved

Disclaimer: The information, data, or work presented herein was funded in part by an agency of the United States Government. Neither the United StatesGovernment nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility forthe accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringeprivately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwisedoes not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof. The viewsand opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DE-AR0000218. Also Mr. Lynn Petersen from United States Office of Naval Research, throughsubcontracts from the Pennsylvania State University, Electro-Optics Center (Subcontract #0145-SC-20579-0285), supported the information, data, and work presented herein.

3Cree Commercial SiC MOSFET Portfolio

TO-247 & TO-220

D2PAK-7LGen 2 Platform DC Current

(TC = 100°C)

1200V/280 mW 6A

1200V/160 mW 12.5A

1200V/80 mW 24A

1200V/40 mW 40A

1200V/25 mW 60A

1700V/1 W 2.6A

Gen 3 Platform DC Current


DieGen 3 Platform DC Current

(TC = 100°C)

900V/65 mW 22A (D2PAK-7L)23A (TO-247)

Gen 3 Platform – In Development

900V/10 mW

900V/120 mW

900V/280 mW

1200V/15 mW

4

• Functional MOSFETsdemonstrated from 900V to15kV

• Parasitic resistancesdominate at lower voltages

– Channel Mobility

– Substrate

MOSFET Portfolio – Commercial and R&D

10

100

RO

N,S

P(m

Wc

m2)

15 kV

10 kV

6.5 kV

3.3 kVCree CMF Family


– Substrate

• Improving Low VoltageMOSFETs

– Optimize Cell Layout

– Improve OxidePerformance

– Trench MOSFET

1100 1,000 10,000

Breakdown Voltage (V)

1.7 kV1.2 kV

900 V

Cree C2M Family

5Next Generation SiC MOSFETs – Nearly 5 Years in the Market

Optimized doping

Reduced pitch


Gen 2 DMOS Gen 3 DMOS

Same high reliability DMOS Structure, but optimized to reduce die size

Commercially released in 2013 as “C2M” product family at 1.2-1.7kV

Commercially released in 2015 as “C3M” product family at 0.9kV

DIVIDER SLIDE EXAMPLE

Gen 3 MOSFET Performance: 900V and 1200V


7Industry’s First 900V SiC MOSFETs Released May 2015

900V/65mΩ• TO-220, TO-247, D2PAK-7L, die• Ron,sp = 2.3 mWcm2

• RDS,on is 1.5X lower than Si at 150°C• RDS,on·EOSS is 4-6X better than Si


8Performance Advantages and Cost Competitive

Parameter SiCC3M0065090J

SiIPW90R120C3

Comments

Package 7L D2PAK TO-247

Blocking Voltage 900 V 900V

IDS 100°C 22 A 23 A

RDS (on) 25°C 65 mΩ 100 mΩ 1.5x better than Si

RDS (on) 150°C 90 mΩ 270 mΩ 3x better than Si

QG 30 nC 270 nC 9x better than Si


Ciss 660 pF 6800 pF 10x better than Si

Coss 60 pF 300 pF 5x better than Si

TJmax 150 °C 150 °C

Diode Reverse-RecoveryCharge (Qrr)

131 nC 30,000 nC >200x better than Si

Reverse-Recovery Time(Trr)

16 ns 920 ns >57x better than Si

Cost (Digikey, singleunit, Aug 2015)

$10.31 $15.84 35% lower cost

9

• 1.7x Increase in Ron from 25°C to175°C

• Significantly smaller increase inRDS,on with temperaturecompared to 650V/19 mW SiSuperjunction MOSFET(IPZ65R019C7)

900V/10mW Gen 3 MOSFET

0

5

10

15

20

25

30

35

40

45

ON

Res

ista

nce

(mW

)

300


025 50 75 100 125 150 175

Temperature (C)

4.5 mm x 7.56 mm

0

50

100

150

200

250

0 1 2 3

I DS

/I C

E(A

mp

s)

VDS / VCE

• Lower On-State losses than 650V/100A Si IGBT,especially at light loads (IPZ65R019C7)

10Switching Performance of 900V/10mW Gen 3 MOSFETT

urn

-On

-20

20

60

100

140

-100

0

100

200

300

400

500

600

700

800

1300 1350 1400 1450 1500 1550 1600

Dra

inC

urr

ent(

A)

Dra

in-S

ou

rce

Vo

ltag

e(V

)

Time (ns)

Vds Ids

0.5

1

1.5

2

2.5

3

3.5

Swit

chin

gLo

ss(m

J)


ESW = 1.8 mJ at 100A/400V

ESW = 4.5 mJ at 150°C and 100A/400V for650V/100A Si IGBT (IGZ100N65H5)T

urn

-Off

-20

20

60

100

140

-100

0

100

200

300

400

500

600

700

800

200 250 300 350 400 450 500

Dra

inC

urr

ent(

A)

Dra

in-S

ou

rce

Vo

ltag

e(V

)

Time (ns)

Vds Ids0

0.5

0 20 40 60 80 100 120 140 160

Drain-Source Current, IDS (A)

11ES-CPM3-1200-0015B (Engineering Samples)

Blocking voltage 1200 V

Current rating 75 A (TC < 100°C)

VGS Max (-8) / (+18) V

Typ RDS(on) @ 25˚C 15 mΩ

Ron,sp @ 25˚C 2.7 mΩcm2

Typ RDS(on) @ 150˚C 26 mΩ

Gate charge total 179 nC0

10

20

30

40

50

60

70

80

90

100

0 2 4 6 8 10

Dra

inC

urr

en

t(A

)

VGS = 0, 5, 10, 15V


Chip Dimensions 4.04 mm x 6.44 mm

Gate Pad 800 µm x 500 µm

Source Pads (each x 3) 1020 µm x 4540 µm

Top Side Source/Gate metallization (Al) 4 μm

Bottom Drain metallization (Ni/Ag) 0.8 / 0.6 μm

0 2 4 6 8 10

Drain Bias (V)


Gen 2 MOSFET Quality at 175°C


13

Reasons for Increasing TJ,max

1) Less cooling required

2) Squeeze more performancefrom a given chip in a givensystem

3) Provide additional margin of

Maximum Junction Temperature

100

150

200

250

Max

imu

mA

llo

we

dD

Issi

pat

edP

ow

er

(W)

100

150

200

250

Max

imu

mA

llo

we

dD

Issi

pat

edP

ow

er

(W)


3) Provide additional margin ofsafety for system designers

JC

TR

TP

,

0

50

100

0 50 100 150 200M

axim

um

All

ow

ed

DIs

sip

ated

Po

we

r(W

)

Case Temperature (°C)

0

50

100

0 50 100 150 200M

axim

um

All

ow

ed

DIs

sip

ated

Po

we

r(W

)

Case Temperature (°C)

14

C2M0025120D

• 4.04 mm x 6.44 mm Chip Size

• 1000 Hours, VGS = 22V

• 3 Lots x 75 parts/Lot

Gen 2 MOSFET Qualification at 175°C - HTGB

• All parts pass parametricspecifications

– 0.2V Shift in VT

– No shift in VDS,on


15

C2M0025120D

• 4.04 mm x 6.44 mm Chip Size

• 1000 Hours, VDS = 960V


Gen 2 MOSFET Qualification at 175°C - HTRB



• All parts pass parametricspecifications

16

0

1

2

3

4

5

6

7

8

0 200 400 600 800 1000 1200 1400 1600 1800

Dra

inCu

rren

t(uA

)

VGS = 0V150°C

Gen 2 MOSFET Accelerated Life Testing under High Bias Conditions

VB

D=

16

60

V

Tim

e(H

ou

rs)

C2M0080120D


0 200 400 600 800 1000 1200 1400 1600 1800

Drain Bias (V)

Extrapolated Mean Timeto Failure at 800V

30 Million Hours

3400 Years

Accelerated Life Testing under High TemperatureReverse Bias Conditions (ALT-HTRB)

• 150°C

• Drain Bias Conditions: 1460V, 1540V, 1620V

• Test to Failure

• Collate Failure Time Statistics

17

• DC Body Diode Stress

– 25 MOSFETs

– 75°C Baseplate

– ISD = 15A DC

– TJ ~ 175°C

• All parts show stable Body DiodeV over 1000 hours

Body Diode Stability at TJ = 175°C – C2M0080120D

3.8

3.9

4

4.1

4.2

4.3

4.4

4.5

Bo

dy

Dio

de

Vo

ltag

e(V

)


VSD over 1000 hours

– Parts removed and checked at16 hours and 90 hours

• All parts pass parametricspecifications after 1000 hoursof stress

3.5

3.6

3.7

3.8

0 200 400 600 800 1000

Bo

dy

Dio

de

Vo

ltag

e(V

)Time (Hours)


Gen 3 MOSFET Avalanche Ruggedness duringUnclamped Inductive Switching (UIS) – 900V MOSFETs


Unclamped Inductive Switching (UIS) – 900V MOSFETs

19Non-Repetitive Avalanche Rating

• Defining the Robustness of a MOSFETunder a high-current avalanche faultcondition– Snubberless Circuits

– Improperly Clamped Inductances

– Unexpected Voltage OverstressesVGS,ON

VGS VDS

CurrentSense


• Silicon MOSFETs typically rated such thatTJ does not exceed TJ,max (150 to 175°C)– Depends on Current (IAV), Avalanche Voltage

(VAV), Duration (tAV)/Inductance (L) andThermal Impedance (ZTH)

– Silicon Carbide can handle much highertemperatures

tAV

IAV

VDS,OFF

V(BR)DSS

t

20Avalanche Ruggedness of C3M0065090 MOSFETs

750

1000

1250

1500

3

4

5

6

Dra

inV

olt

ag

e(V

)

Ind

uct

or

Cu

rren

t

Inductor / Avalanche current

Drain Voltage

Breakdown Performance at 25 and 150°C

C3M0065090 – 900V/65mW MOSFETs


Unclamped Inductive Switching (UIS) Event forC3M0065090D MOSFET

0

250

500

750

0

1

2

3

0 200 400 600 800 1000

Dra

inV

olt

ag

e(V

)

Ind

uct

or

Cu

rren

t

Time (μs)

VAv = 1405 VEAv = 191 mJtAv = 68.4 μs

Internal DeviceTemperatures reaching

100’s of °C during avalanche

21

• Avalanche rating determined statistically from the failure of tens ofMOSFETs at several Input Currents (10A, 20A and 30A)

Defining Avalanche Ruggedness – C3M0065090

• Avalanche RuggednessQualification Success

– Applied rated Avalanche Conditions(100 discrete pulses)

– 3 Lots x 25 Parts/Lot x 2 different


– 3 Lots x 25 Parts/Lot x 2 differentcurrents (5A and 30A)

– 1000 hour HTGB and HTRBperformed following AvalancheStress

– All parts passed HTGB and HTRB

– Accelerated HTRB (in Avalanche)under way (see next slide) C3M0065090 – 900V/65mW MOSFETs

22Accelerated HTRB in Avalanche (of Parts subjected to Avalanche Stress)

40

60

80

100

120

140

160

180

200

Dra

inC

urr

en

t(u

A)


C3M0065090D MOSFETs – 900V/65mW

• 3 Lots x 10 Parts per Lot x 2 Avalanche Stress Currents (5A and 30A)

• Parts Running for >1600 hours at 150°C at 1200V+

• Two failures from the population as of 1600 hours

VGS = 0V

VDS = 1360V

0

20

40

0 200 400 600 800 1000 1200 1400 1600 1800

Time (Hours)

23Avalanche Ruggedness at Elevated Temperatures – C3M0065090

100

1000

Sin

gle

Pu

lse

Ava

lan

che

Ener

gy(m

J)

C3M0065090900V/65mW MOSFETs


• MOSFETs are avalanche rugged at TJ,max

– In single pulse UIS, internal temperature of the MOSFET significantlyexceeds TJ,max

– This overhead results in only a small drop in UIS Avalanche ruggednesswith an increased junction temperature

10

1 10Si

ngl

eP

uls

eA

vala

nch

eEn

ergy

(mJ)

Current in Avalanche (A)

24

• Third Generation DMOSFETs inProduction (900V) or Development(900V, 1200V +)

– Significant performance advantageover Si CoolMOS and IGBTs

– 175°C Qualification ongoing

– UIS avalanche ruggednessdemonstrated

Summary

10

100

RO

N,S

P(m

Wc

m2)

15 kV

10 kV

6.5 kV

3.3 kV


demonstrated

• Room for improvement remains inlower voltage MOSFETs

– Further cell pitch optimization

– Oxide improvements1

10

100 1,000 10,000

Breakdown Voltage (V)

3.3 kV

1.7 kV1.2 kV

900 V

Cree C2M Family

Cree CMF Family

evolution of sic mosfets at creeneil/sic_workshop... · sponsored in part by army research...

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