employing rtems and fpgas for beamline applications … · employing rtems and fpgas for beamline...
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EMPLOYING RTEMS AND FPGAS FOR BEAMLINE EMPLOYING RTEMS AND FPGAS FOR BEAMLINE APPLICATIONS AT THE APS*
David M. Kline, Steve K. Ross
PCaPAC2010PCaPAC2010October 5‐8, 2010
*Use of the Advanced Photon Source at Argonne National Laboratory was supported b th U S D t t f E Offi f S i Offi f B i E S iby the U. S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE‐AC02‐06CH11357.
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Overview
“Generic Digital” concept
Hardware
Software
Applications
Conclusions
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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Generic digital concept
Generic digital concept (design pattern)– Abstract to compartmentalize
– Model components• EPICS component
– Arcturus uC5282 (uCDIMM) RTEMS (typical)Arcturus uC5282 (uCDIMM), RTEMS (typical)
– Adapters (optional)
• FPGA component
– Generation I, II, development kits
• IO component• IO component
– Application specific interface
– APS timing signals
– Camera Link
/ ( )
IO
SENSOR/AMPLIFIER– PC/104 adapter (motion, sensor input)
– Others…
FPGA
EPICS/RT
EMS
INSTRUMENTATION
TIMING SIGNALS
MOTION CONTROLS
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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BUS INTERFACES
Model diagram
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Hardware
Generation I base boardEBLOCK/w IO
EBRICK INTERFACE– Steve’s generic digital
– Altera FLEX10K FPGA (5V)
– 64bits buffered TTL IO
IO d ht b d
EBRICK
EBRICK INTERFACE
IO BOARD– IO daughter board
– EPICS Brick (EBRICK) provides EPICS interface
– Parameterize application/w serial link protocol
– 1U housing, rack mountable, desktopU ous g, ac ou tab e, des top
– Applications• Simple logic
• “divide‐by” logic
S l
GEN‐I base board
IO
SENSOR/AMPLIFIER• Scaler
FPGA
EPICS/RT
EMS
INSTRUMENTATION
TIMING SIGNALS
MOTION CONTROLS
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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GEN‐I generic digital/w EBRICK‐II
BUS INTERFACES
Model diagram
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Hardware, cont…
Generation II base board socketLAN interface
uC5282 carrier24bits TTL IO
– Dave’s generic digital– Altera Cyclone‐II (240 Quad)– VME footprint– 24bits buffered TTL IO (configurable)– 40bits LVTTL expansion (daughter board)
VME adapterGEN‐II base board
40bits LVTTL expansion (daughter board)– 58bits external interface
• Option 1: uC5282 (Coldfire) carrier (typical)• Option 2: VME interface• Option 3: socketLAN interface board
– Boot methodsPC104 adapter
COMMER
CIAL
IN‐HOUSE
Boot methods• NFS synApps autosave• Completely standalone, all IOC files• Standalone, IOC image, NFS boot files• Standalone, TFTP image, NFS boot files
– 2U housing, rack mountable, standalone
IO
SENSOR/AMPLIFIER
TTL IO
NIM,ECL, TTL IO
C
g– Applications
• Timing modules, delay generators• Scalers• P0 bunch intensity compensator• Bunch photon counting
FPGA
EPICS/RT
EMS
INSTRUMENTATION
TIMING SIGNALS
MOTION CONTROLS
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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BUS INTERFACES
Model diagram
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Hardware, cont…
Development kitsHSMC Camera‐link
– High‐end applications (detectors)
– On‐board LVDS, LVTTL IO, memory
– EPICS interface (uC5282 carrier)
A li ti Development kit
HSMC uC5282 carrier
– Applications• Fuel spray experiment
• DOE SBIR (Small Business Innovative Research)
– Voxtel, Inc. multi‐pixel array ASIC/Sensor
Development kit
– Radiation Monitoring Devices, Inc. APD arrays
IO
SENSOR/AMPLIFIER
Voxtel ASIC/Sensor
FPGA
EPICS/RT
EMS
INSTRUMENTATION
TIMING SIGNALS
MOTION CONTROLS
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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BUS INTERFACES
Model diagram
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Software
Development– Linux and Windows environment
– Linux: EPICS development
– Windows: FPGA development
EPICSEPICS– Central repository for base, synApps (support, nonsupport)
– Central location for IOC app, boot files, autosave
– synApps EBRICK supports uC5282/RTEMSsynApps EBRICK supports uC5282/RTEMS
FPGA– Altera’s Quartus‐II design software
– uC5282 bridge (AES‐controls)
FPGA application, etc…
g ( )
– SOPC configuration
– FPGA application logic
uC5282 bridge
SOPC PIOs
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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Applications
32‐channel scaler Timing
Flexible CCD shutter timing module
Configurable delay generator
P0 bunch intensity compensator
Scaler
Time‐resolved photon counter (bunch scaler)
FlexLogic prototype
PC104: ADCs, Motion control, sensor input Motion controller
ADC module
Fast ADC (detector development)– Radiation Monitoring Devices, Inc. APD arrays
for x‐ray timing (~100ps), counting
F l i t
controller
Sensor input
– Fuel spray experiment
– Voxtel, Inc. multi‐pixel array detectorSensor testing
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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Voxtel ASIC/Sensor
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Applications32‐channel scaler32 channel scaler– Motivation
• Lower hardware costs
• VME‐less beamlines
IO board
• Mobility
– GEN‐II generic digital
– IO board (LVTTL<‐>TTL)• TTL inputs (scalers,ARMIN,GATEIN)puts (sca e s, ,G )
• TTL outputs (CLKOUT,ARMOUT)
• LED indicators (EPICS,ARMOUT,ARMIN,GATEIN)
– Standalone / mobile enclosure EPICS
EPICS COMPONENT
Standalone / mobile enclosure
– Software development• Scaler record support (synApps STD)
– Standard support (record,MEDM)
k
SCALER RECORD
CONTROLCLKOUTSTATUS ARMOUT
LEDS
T
DEVICE SUPPORT FPGA COMPONENT IO COMPONENT
– Framework
• ASYN driver
– Device support(framework methods)
COLDFIREBRIDGE
SCALERSDATAPRESET
CTR
#
FUN
C
ARMOUTARMIN
SCALER32
IO B
OA
RD
IO B
REA
KO
UT
– Interface to access scalers, status
• MEDM screensArgonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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SCALERSDONEDATA
SCALER1
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Applications, cont…
Flexible CCD shutter control– Delay, stretch signals
– GEN‐II generic digital
– IO board (same as scaler)• TTL IO• TTL IO
• LED indicators (EPICS,MODE,STATE)
– Standalone / mobile enclosure
– Software development EPICS
EPICS COMPONENT
• ASYN driver
• MEDM screens
– User configures• Main modes (CFG,RUN)
ASYN DRIVER
COLDFIRE
CONTROL
AR
D
LEDS
KO
UT
FPGA COMPONENT IO COMPONENT
DELAYS
Main modes (CFG,RUN)
• Sub‐modes (CCD ON/OFF,EXT SYNC)
• Signal delay, duration
COLDFIREBRIDGE
SUBMODES
CTL
INP SIG
OUT SIG
IO B
OA
IO B
REA
K
DA
TA
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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Applications, cont…
Fast ADC – Fuel spray experiment (current)
9222
EROR
kit
IO EPICSFPGA
– Altera Stratix‐IV development kit
– IO boards • 8chan ADC (AD9222 480Mbps/chan)
• Amplifier sensor NK
NG
ADC ‐A
D9
AMPLIFI
(ASIC)
STRIP
DETEC
TO
V de
velopm
ent k
5282/RTEMS
g• Amplifier, sensor
• Camera‐link, APS timing
– Sensor development• Silvaco tools (Schematic,simulation,layout,TSMC)
i i l
CAMER
A LI
APS TIM
I N
Stratix
‐IV uC5
APS
Tim
ing
• University clean room
– Standalone / mobile enclosure
– Software development• ASYN driver
HSMC Camera‐link HSMC uC5282 carrier
• MEDM screens
Development kit
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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p
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Conclusions
Serves as “design pattern” applicable to many applications
Flexible and adaptive, varying configurations and complexities
uC5282/FPGA combination proven reliable
EPICS, synApps modules, RTEMS reduces development time
Focus more on application
APS users benefit
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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Thank You
Comments, questions, reactions?
TEAM MEMBER GROUP PHOTO
!!!REAL TEAM MEMBERS!!!
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Supplemental material follows
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Applications, cont…
P0 bunch intensity compensator– Trigger external DAQ for averaging
– GEN‐II generic digital
– IO board (same as bunch scaler)
St d l / bil l– Standalone / mobile enclosure
– ASYN driver
– User configuration• Bunch window
• # of stages
• Trigger at bunch # for 1uS P0 bunch intensity compensator
Argonne National Laboratory, Advanced Photon Source, Optics and Detector Group
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Applications, cont…
EXTERNAL TRIGGER ……….0 1 N‐2 N‐1
P0
STAGE ENABLE
……….
……….
……….
STAGE 0
STAGE 1 ……….
STAGE 0 ……….
STAGE N‐1 ……….
……
……
OUTPUT TRIGS ……….
STAGE N ……….
TIMING DIAGRAM FOR N 16TIMING DIAGRAM FOR N=16
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