LucaLarcherandPaoloPavanUniversitàdiModenaeReggioEmilia

Emergingmemories:TechnologytrendsandIUNETresearch

contribu9ons

Outline•  Memorylandscape:technologytrends•  IUNETprojectsandresearchcontribuAons

–  Polimi–  Unimore–  Unife–  Unical

•  Conclusions

Memorymarketandtechnology•  StrongmarketconcentraAon

•  NAND(24B$):Micron,Samsung,Hynyx,Toshiba•  DRAM(45B$):Micron,Samsung,Hynyx•  X-point:notclearmarket/applicaAonnow

•  DRAMand2DNANDscalingconAnuesslowly•  3DNANDmoreacAve

DRAMchallenges•  UncleariftheverAcalDRAMstructurecanscalebeyond10nm•  ScalinglimitaAonsovercameby3Dpackaging

NANDchallenges•  3DNANDrampsup,as2Dscalingpushesahead•  Yieldanddevicechallenges

–  Polychannel:defect/chargetrappingeffectsoncurrent–  Thinbody–  Chargetrapping

3DXpointmemory:status•  Technologyexplored:

–  ReRAM–selectorisabigissue,andmanytechopAonsarecurrentlyinvesAgated(OTS,tunneling/Sho]kybarriers)

–  STT–cancombineworkingandNVMstronglyreducingthepowerconsumpAon;suitedforIoT

3DXpointmemory:challenges•  TechnologysAll

inthediscoverypart

•  ResearchneededtofindbestsoluAons

Outline•  Memorylandscape:technologytrends•  IUNETprojectsandresearchcontribuAons

–  Polimi–  Unimore–  Unife–  Unical

•  Conclusions

PCMwithbipolarswitchingforimprovedretenAon

Polimi:emergingmemories

9 IUNET2017

(b)(a)

N" ~ t&'(

(a) (b)

Set

SetReset

Reset

(a) (b) Parallel (P)State

(c) Antiparallel (AP) State

N.Ciocchini,etal.,Sci.Rep.(2016)

STT-RAMmodelsoftransport,switching,endurance R.Carboni,etal.,IEDM(2016)

Polimi:SiOx-basedRRAMdevices

•  Ti/SiOx/CRRAMwith1T1Rstructure,104on-offraAo,108cycles,1h@260°CretenAon

•  ThePCM,STT-RAMandRRAMdevicesdeveloped/studiedinPolimiarecurrentlyusedforin-memoryandneuro-compuAngprojectsRESCUEandDEEPEN

10 IUNET2017

Ti(TE)

SiOx

C(BE)Wplug

VG

A.Bricalli,etal.,IEDM87(2016)

HRS

LRS Ic

Vstop

11

Unimore:modelingofRRAM,FeRAM,PCM•  ModelingfornovelmemoriesandneuromorphiccompuAngdevices•  Structuralmaterialchanges,ion/vacancymigraAon,ferroelectriceffect,

phasechange,…selfconsistentlyaccountedfor–mulAscalekMCapproach•  RRAM,DRAM,FeRAM,selectors

•  AccuratesimulaAonofdeviceoperaAonsanreliabilityincludingstaAsAcs

•  NoisecharacterizaAonandmodeling

F.Puglisietal.,IRPS2015,TED2015,A.Padovanietal.,IMW2012-A.Kalatarianet.al.,IRPS2012

Unimore:RRAMcharacteriza9on&simula9ons

UniFE&UniCal:H2020R2RAMproject

DevelopmentanddesignofaradiaAonhardnon-volaAlememorytechnologybyusingstandardCMOSsiliconprocessing.NewR2RAMapproach:UsingtheResisAverandom-accessmemory(RRAM)technologywww.r2ram.eu

WP# WP9tle

LeadPart.shortname

PMs Startmonth

Endmonth

1 Management IHP 5 1 24

2

RequirementAnalysisandApplicaAonSpecificaAon

RCD 7 1 6

3

RRAMTechnology,ArchitectureandCellDevelopment

IHP 23 1 21

4 D e s i g nE n a b l e m e n tPlaporm

IHP 16 1 15

5 1MbitTestVehicleDesign

RCD 22 1 20

6 RadiaAonTesAngCampaign

IUNET 46 1 24

7 DisseminaAonandExploitaAon

IUNET 12 4 24

TOTAL 131

UniFe:Rad-Hard1T-1RRAMsingledevicen Selectrad-hardtransistor(EnclosedLayoutTransistor)n ELTmanufacturatedina250nmCMOStechnology

n MIMstackn TiN/HfO2/Ti/TiNstackn 150nmTiNtopandbo]omelectroden 7nmTin 9nmHfO2depositedbyChemicalVaporDeposiAon(CVD)

n Area:700x700nm2

1 10 100

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

Voltag

e[V

]

C yc leNumber

DC R es etAC R es et

1 10 100

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

Voltag

e[V

]C yc leNumber

DC S etAC S et

Excellentrad-immunity StablecyclingoperaAon

Unife:radia9ontes9ngon1MbitsRRAMarrays

n BeforeradiaAon,cellshavebeenformedandprogrammedinLRS(50%)andHRS(50%)

n ArerradiaAon,thechipissAllfuncAonalandreprogrammable(datathroughradiaAonarelostcausedbyhighLETdoses)

TwotypesofradiaAon:-  highenergy(LET=60MeV/mg/cm2)Xenonions-  highenergy(LET=50MeV/mg/cm2)proton-  TestVehicle:1MbitRRAMchip

OperaAonUnderRadiaAon

Unical:micromagne9csimula9onframework

FullmicromagneAcsolver+

look-uptable(LUT)-basedVerilog-Amodel

R. De Rose et al., “Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a MicromagneAc-Based SimulaAon Framework,” IEEETransac.onsonNanotechnology,vol.16,no.2,pp.160–168,2017.

AnalysisofwriteaccessAmeandenergyinSTT-MRAMsundervoltagescaling

0.0

0.1

0.2

0.3

1n

5n

10n

0.6 0.7 0.8 0.9 1.0 1.1

100f

120f

140f

160f

MT J s tochas tic va ria tions

C MO S va ria tionsMT J res is tance

va ria tionsG loba lva ria tions

(σ/µ) ts

(d)

(c )

(b)

(a) W =80nmW =160nm

writede

lay(s)

0 .7 0.8 0.9 1.0 1.10

25

50

75

100

C MO S va ria tionsMT J s tocha s tic va ria tionsMT J res is tance va ria tions

(σ/µ)2 ts(%

)

VDD(V )

W =80nmW =160nm

writeen

ergy

(J)

VDD(V )

SimulaAonapproachtoperformavariability-awareanalysisofhybridCMOS/MTJcircuitsconsideringtheimpactofMTJandCMOSprocess

variabilityandtheMTJstochasAcswitchingbehavior

Unical:compactmacrospinVerilog-Amodel•  ComprehensiveanalyAcalmacrospincompactmodelfor

perpendicularSTT-MTJsincludingtheeffectsofvoltage-dependentPMA,temperature-dependentparameters,JouleheaAng,MTJprocessvariaAonsandstochasAcswitching

R.DeRoseetal.,“ACompactModelwithSpin-PolarizaAonAsymmetryforNanoscaledPerpendicularMTJs,”IEEETransac.onsonElectronDevices,inpress,2017,DOI:10.1109/TED.2017.2734967.

BlockdiagramoftheVerilog-Acompactmodel

1.5

2.0

2.5

3.0

1.5

2.0

2.5

3.0

0.68 0.72 0.76 0.80

2.5

5.0

7.5

10.0

0.68 0.72 0.76 0.80

90

120

150

180

(d)

P→AP s witc hing

30-nm25-nm20-nm

I WRITE/I c

(c )

(b)(a)

AP→P s witc hing

30-nm25-nm20-nm

I WRITE/I c

30-nm25-nm20-nm

writede

lay(ns)

VDD(V )

Minimum-energ ypoint(ME P )

30-nm25-nm20-nm

writeen

ergy

(fJ)

VDD(V )

ImpactofthetechnologyscalingonwriteaccessAmeandenergyinSTT-MRAMs

Conclusions•  Ho]esttopicsinthe“memory”field:

•  DRAMscaling•  ReliablesoluAonforselectorsforx-point•  EmbeddedforautomoAve?

•  IUNETacAveinallemergingmemoryfieldsforxpoint:RRAM,PCM,STT-MTJ,FeRAM

•  Issue:leadingindustriesfarfromEurope(Micron,Samsung,Hynyx,Toshiba/Sandisk):accesstofundingcomplex

•  Opportunity:workonembeddedforautomoAveandsmartpowerapplicaAons?ConnecAontoEUindustryforprojects?