electronic design automation (eda) eda · eda vlsi design, physical design automation, design...

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Prof. Dr.-Ing. Reinhard Möller Automatisierungstechnik / Prozessinformatik Bergische Universität Wuppertal

EDA

VLSI Design, Physical Design Automation,

Design Styles

Electronic Design Automation (EDA)

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Outline

• Introduction• VLSI Design Cycle

• Physical Design Cycle and Automation• Design Styles• Packaging

Outline

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• Also known as VLSI CAD.• It refers to the utilization of CAD techniques for VLSI design.


• Complexity of current day electronic design (P4 : 55 million transistors, P4 EE: 178 million transistors).

– Manual design is unrealistic.

• Fewer errors.• Time to market.

Why EDA?

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Industry perspective

• Major EDA tool vendors:– Synopsys, Cadence, Mentor graphics

• Major semiconductor design houses:– Intel, IBM, Motorola, Xilinx, Altera …

Industry perspective

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VLSI Design Cycle

System Specification

Architectural Design

Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication

Packaging andTesting

System specification: High level functional description (informal) of the design with size, speed, and power constraints.

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VLSI Design Cycle



Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication


Architectural design: Micro-architectural specification (informal) of the design with architecture style, number of ALUs, floating point units, number and structure of pipelines, and size of caches. → PCB: Library design.

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VLSI Design Cycle



Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication


Functional design: The functionality of each unit and their interconnection is described by a HDL. The area, power, and time constraints of each unit are identified. → PCB: Logic Blocks, Symbols

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VLSI Design Cycle



Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication


Logic design: Register transfer level (RTL) description of the design in HDL is generated. → It consists of boolean expressions and timing information. → PCB: Cell design

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VLSI Design Cycle



Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication


Circuit design: A circuit description in logic gates (or netlist) is developed. Automated circuit design is called logic synthesis. ..plus Simulation!→ PCB: Logic Design, Analog Design, Schematics

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An Example Netlist

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VLSI Design Cycle



Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication


Physical design: The circuit representation (or netlist) is converted into a geometric representation (the layout). → Automated physical design is called physical synthesis.→ PCB: PCB Design, -Layout and Routing

Backward Annotation

Forward Annotation

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Physical Design Cycle

• Input: A netlist of gates (or blocks) and their interconnections.

• Output: A geometrical layout of the netlist within an area constraints.

• Other goals: Minimize signal delays, interconnection area, power, cross-talk.

Automatic check of design rules


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VLSI Design Cycle



Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication


Fabrication: After a layout is generated the design is ready for actual fabrication or manufacturing.→ PCB: Gerber Files, Production Data, Layout Masks

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VLSI Design Cycle



Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication


Packaging, Testing and Debugging: The fabricated wafer is diced into individual chips that are then packaged, tested, and debugged.→ PCB: This part is integrated in the previous steps, except testing

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Packaging

• Printed Circuit Boards– Packaged chips are soldered on a substrate.– Larger wire delays, lower integration.

• Multichip Modules (MCM)– Un-packaged chips are soldered on a substrate.– Medium wire delays, medium integration.

• Wafer Scale Integration– Multiple chips are fabricated on a single wafer.– High performance, high integration, lower yields.

Packaging

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New Trends in VLSI Design

• Increased interconnect delay: interconnect not scaling at the same pace as the device.

• Increasing interconnect area: Upto 40 % of the area devoted to interconnect.

• Increasing number of metal layers: Upto 5 layers for microprocessors.

• Increasing planning requirements: Physical design early on in the design cycle.

• Automated synthesis: Logic and high-level.

Major requirement: Physical design automation -the computer-aided physical design cycle.

→ PCB: Autoplacement, Autorouting

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An Example Layout

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An Example Layout

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An Example Layout

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• Partitioning: Divide the net-list into sub-sets.

• Floorplanning and placement: Determine the dimensions of the various units and their placement.

• Global routing: Determine the regions through the chip that the wires or net would be routed.

Major Tasks of Physical Design (1)

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• Detailed routing : Determine the actual layout of the nets within each routing region.

• Compaction : Compress the layout to reduce the area.

• Extraction and verification : Design rule checking for ensuring that the layout meets the fabrication constraints. Extraction and simulation against previous specification.

Major Tasks of Physical Design (2)

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Design Styles

• Full Custom– Utilized for large production volume chips such as microprocessors.– No restriction on the placement of functional blocks and their

interconnections.– Highly optimized, but labour intensive.

• Standard Cell– Utilized for smaller production ASICs that are generated by synthesis

tools.– Layout arranged in row of cells that perform computation.– Routing done on “channels” between the rows.

(V)LSI Design Styles (1)

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Design Style

• Gate Arrays– Pre-fabricated array of gates (could be NAND).– Design is mapped onto the gates, and the interconnections are routed.

• Field programmable gate arrays– Pre-fabricated array of programmable logic and interconnections.– No fabrication step required.

• Sea of gates– Pre-fabricated sea of gates with no area for routing.– Simpler gates with very high density.– Routing through gates or by fabricating over the cell routing.

(V)LSI Design Styles (2)

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Design Style Comparisons

LowMediumMediumHighDesign cost

Prog.VariableVariableVariableInterconnections

FixedFixedIn rowVariableCell placement

Prog.FixedVariableVariableCell type

FixedFixedFixed heightVariableCell size

FPGAGate ArrayStandard Cell

Full Custom

STYLE

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Design Style Comparisons

NoneRoutingAll LayersAll LayersFabricate

LowModerateHigh to ModerateHighPerformance

LargeModerateCompact to Moderate

CompactArea

FPGAGate ArrayStandard CellFull Custom

STYLE

electronic design automation (eda) eda · eda vlsi design, physical design automation, design...

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