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Computer Hardware and System Software ConceptsIntroduction to Computer Architecture

2Copyright © 2004, Infosys Technologies Ltd

ER/CORP/CRS/OS09/003

Version No: 2.0

Course Objective

To introduce fundamentals of Computer Architecture

To introduce the concepts of System Software.

To introduce the concepts of Operating Systems.

To introduce the concepts of Computer Networks.



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References

Andrew S. Tanenbaum: Structured Computer

Organization , PHI, 3rd edition, 1991.

Silberschatz and Galvin: Operating System Concepts , 4th

edition, Addison-Wesley Pub, 1995.

Andrew S. Tanenbaum: Computer Networks, PHI, 1991.

Alfred V.Aho, Ravi Sethi, Jeffrey D.Ullman: Compilers -

Principles, Techniques and Tools, Narosa Publishing

House, 1986.



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Session Plan

Day 1

– Create a background

– Main components of computer architecture

– Different addressing modes

Day 2

– Introduce System Software

– Introduce Operating Systems/Memory Management



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Session Plan

Day 3

– Introduce Process Management

– Introduce File Management

Day 4

– Introduce Device Management

– Introduce Computer Networks



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Background

What is a Computer?

– Is an electronic device used to

• Store

• Retrieve and,

• Process data.

– To process data a set of instructions need to be given to the

computer.

What is a Program?

– Is a set of instructions.



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Computer Architecture

Is concerned with the structure and behavior of the

computer as seen by the user/programmer. It includes

attributes such as

– Instruction Formats

– Addressing Modes

– Instruction Sets

– I/O Mechanisms



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Computer Architecture

Main components in a computer system

Hardware

Software

Firmware



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Organization of a simple computer

•Central Processing Unit (CPU)

•Main Memory

•Input / Output devices

•Bus



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CPU (Processor)What is it?

Brain of the computer

Function

– Fetch instructions from memory

– Examine

– Execute

Consists of 3 functional units

– Control Unit (CU)

– ALU

– Registers



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CPU – Functional Units

Control Unit

ALU

Registers

Fetches Instructions from memory

Interprets the instructionsCPU

Performs arithmetic operations

Performs Logical operations

Very high speed memory units in the CPU-for storing very small amount of data.

Examples

•Program Counter (PC)

•Instruction Register (IR)

•Memory Address Register (MAR)

•Memory Buffer Register (MBR)

•Accumulator (A)



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Examples of CPU (Processor)

Intel Processors

8088

80286

80386

80486

Pentium

Motorola Processors

68000

68020

68030



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MemoryMEMORY

Internal

Memory

Main

Memory

Cache

Memory

Secondary

Memory

RAM ROMInternal

Cache

External

Cache



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Memory – Internal Memory

In the form of Registers

Registers are small memory units internally

available within the CPU.

Volatile/Non volatile Memory



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Memory - Primary or main Memory

Volatile/Non volatile Memory

Main Memory

Random Access

MemoryRead Only

Memory



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Memory - Cache Memory

A memory placed between CPU and main memory

Contains a copy of the portion of main memory

Processor when needs some information first checks cache

If not found in cache, the block of memory containing the needed

information is moved to the cache

CPU

Cache

Main Memory



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Memory - Secondary memory devicesType Description Readable Writable

Typical

size Hard disk

These are placed separately along with the CPU (in the

cabinet) and are usually not portable.

Yes Yes 40 GB 80 GB

Floppy disk

The Floppy disks are portable. These come in smaller sizes compared to Hard

Disk.

Yes Yes 1.44 MB

CD ROM Compact Disc, Read Only Memory

(CD-ROMs) are portable. These are typically read-only, meaning they could be used only to read the contents.

Yes No 650-700MB

CD Read/ Write

This is simillar to CD-ROMs except that it is also used to write the information on to the special CD-ROM which are of Read-Write type.

Yes Yes 650-700 MB



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Comparison of different types of memoryStorage type Implementation

FeaturesContents Example Typical Size

Internal Memory

Very high speed devices, located within CPU(chip); expensive, and volatile. Very costly, hence limited in capacity.

Holds instructions under execution and associated data item.

Registers, Internal Cache memory

Registers will be few in number.The internal Cache could be 256 KB or 512 KB

Primary Memory

High speed devices (but slower than the internal CPU registers) located outside the CPU (on the motherboard), Less costlier compared to internal memory. Usually larger in capacity.

Entire (almost) program contents being executed; holds small volume of data.

RAM (volatile), ROM (Non volatile), External Cache Memory

256 MB512 MB

Secondary Memory

Low speed, Non-volatile, low cost.Huge in capacity.

Programs not currently being executed; holds large volume of data

Hard Disk, Compact Disks(CDs), Floppy disks

40GB80 GB



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Memory hierarchy



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Bus

Parallel wires that carry several bits at a time

Carries instructions, data, addresses or commands

Unidirectional or bi-directional

Major Categories

– Data bus

– Address bus

– Control bus

Bus width and Bus speed are the two major components for performance

measure.



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Different types of registersCategories:-

General Purpose Registers

– are those which are used by the programmer to store data.

– all CPUs will have one register called Accumulator.

Special Purpose Registers

– The special purpose registers are used by the CPU for temporary storage of data for

calculations and other purposes.

– Ex.:

• MAR

• MBR

• IR

• PC



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Registers, CPU and the memory



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Harvard Architecture - Data & program stored separately.

The Advantages of this architecture is the clear separation of the data region and the code region. Also the separate data and program busses are used, hence speeding up the process.

Disadvantages could be the separate mechanisms to fetch data and the programs.



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Von Neumann architectureData & Program, both stored in the same place.

The Advantages of this architecture is that it treats data and programs alike meaning the same mechanisms to fetch data and the programs.

The disadvantage is the same bus used for both program as well the data leads to so called Von Neumann bottleneck.



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Von Neumann architecture - characteristics

One processor

Use of stored programs

Sequential processing of instructions

Single Instruction, Single Data stream (SISD) mode



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Execution of the Instructions

The execution process of the instruction stored in the memory happens in

three phases.

Fetch Phase: In this phase the instructions retrieved picked from the memory.

Decode Phase: Once the instructions are retrieved these are decoded by the

CU.

Execute Phase: Once the instructions are decoded, they are executed by the

ALU (in case they are Arithmetic instructions).



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Fetch-decode-execute cycle

Special Registers

CPU

Control Unit .....

.

.

.

Memory

ALU

GPRR3 R4

MAR

ProgramCounter

InstructionRegister

MBR

InstructionDecoder

R2R1

5000 1A

ADD R1,R2



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Fetch-decode-execute cycle

Fetch Phase

Decode Phase

Execute Phase



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Fetch phase

Contents of PC are transferred to MAR

Main memory is accessed and current instruction is fetched into MBR

Instruction is transferred from MBR to IR



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Decode phase

Opcode of the instruction is decoded

Contents of PC are incremented by 1(in case of 1 byte instruction or equal to

the no. of bytes of the instruction currently being executed.)

Execution phase follows ( specific to the given instruction )



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Execute phase

Execute the instruction

Store the results in the proper place (go to the fetch phase to begin executing

the next instruction)



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Fetch-decode-execute cycle-Example 2



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Instruction categories

Arithmetic Instructions

– Ex.: Add, Sub, Mul etc.

Logical instructions

– Instructions doing comparison operations.

Program Control instructions

– Ex.: Jump to some memory location where the code is place & return etc.

I/O instructions

– Ex.: In, Out

Data Transfer instructions

– Register-Memory / Memory-Register

– Register-Register

– Memory-Memory.



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Instruction categories (Cont…)

From Registers toMemory

From Memmory toRegisters

Arithmetic Logic Unit (ALU)

Control Unit

Central Processing Unit (CPU)Mem

ory

Memor

y to

mem

ory

REGISTERS

R1 R2

R3 R4

MAR

IR PC

MBR

Data Transfer instructions

Register-Memory / Memory-Register

Register-Register

Memory-Memory.



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Variations of CPU Architecture

SISD

SIMD

MIMD

MISD



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I/O devices

Why needed?

O/P Devices:

PrinterMonitor



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I/O devices

Input Devices:-

KeyboardMouse



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I/O devices

Input/Output Devices



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Measures of CPU performance

MIPS - is a measure of the speed of the processor.

Clock Speed – is another metric used to measure

performance.

FLOPS – is a measure of the speed of the Floating Point

Unit (FPU) which is a co-processor unit.



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Addressing

A way of accessing memory locations which contain the data for

processing

Modes of addressing

– Implied Addressing

– Immediate Addressing

– Direct or Absolute Addressing

– Relative Addressing

– Indirect addressing



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Implied Addressing

Operands are specified implicitly in the definition of the instruction

Instruction specifies a fixed and unvarying address

Example:- DEC (Decrement A register)

1. The CU decodes the instruction (fetch and decode phase)

2. The CU then fetches the contents of the register A

3. The value of the A will be transferred to the ALU

4. The ALU then decrements this value and updates the register A



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Immediate addressingIn it, data is a part of instruction itself.

Example:- MOVE #100H, R1

• Here the data 100h is moved to R1.

The following steps are involved in the execution of this instruction.

– The CU decodes the instruction (fetch and decode phase)

– The data 100H available with the instruction is sent to Register R1.

Control UnitR1

MOVE #100H R1

2

1



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Direct (Absolute ) addressing

The address where data is available is part of the instruction

Ex.: MOVE 30A4, R1

75

MOVE 30A4H R1

Control Unit R1

1

30A4

2

3



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Problem with Direct Addressing



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Indirect Addressing

Problem of direct addressing :the change in the location of the

program is associated with the change in all absolute memory

references.

Solution : is to represent the address of the data indirectly.

There are two ways to do it:

– 1) Register Indirect Addressing : the address of the data is

stored in a Register.

– 2) Memory Indirect Addressing : the address of the data is stored

in another memory location



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1) Register Indirect Addressing :Ex.: MOVE [R2], R1

Memory

MOVE [R2] R1 R1

Control Unit

17530A4

4

R2

3

2

The register R2 is assumed to be pre- loaded with a value of 30A4



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1) Memory Indirect Addressing :Ex: MOVE [ 7010 ], R1



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Problems with Indirect Addressing



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Base - Indexed AddressingEx.: MOVE [BX] + [Ri], R1.

hold the Base value of the

program. holds the

Offset (relative) address.

Memory

3000

IndexRegister Ri

BaseRegister

(BX)

R1

20A4

MOVE [BX] [Ri] R1

75

+3 3

50A4

4

75

ADDER(ALU)

3000 20A4

21

5



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Problem with usage of shared memory



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Segment Register Addressing



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Segment Register Addressing

MOVE [SR]

Memory

50000

IndexRegister Ri

BaseRegister

(BX)

R1

100

[BX] [Ri] R1

75

+3 3

51100

4

75

ADDER(ALU)

1000 100

21

Segment1(code)

Segment2(Data)

51000

100050000

0

3

SegmentRegister

(SR)

Segment3

5



Version No: 2.0

Summary

Background

Components of a computer system

Von Neumann architecture

Fetch Decode Execute Cycle

Memory

I/O devices

Bus

Addressing Modes



Version No: 2.0

Thank You!

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