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EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019 2

Lecture: Partial Reconfiguration

Prof. Jakub SzeferDept. of Electrical Engineering, Yale University

EENG 428 / ENAS 968Cloud FPGA


Partial Reconfiguration and FPGAs

• Typical FPGAs work flow:• Program the FPGA with bitstream• Run the hardware design to do the computation• Re-program the FPGA with next bitstream

• Partial reconfiguration idea: FPGA reconfiguration is allowed during runtime


The hardware design is static and not changing while

the FPGA is running

User’s Logic

Module 1

FPG

A Ch

ip

…

Module N

Different modules can be loaded into a pre-defined FPGA region at runtime


Partial Reconfiguration

• Reconfiguring part of an FPGA enables changing part of the logic,while the rest remains configured, active, and un-interrupted

• Most FPAG designs are made for full reconfiguration• Partial reconfiguration introduced around 2000

• FPGAs were introduced commercially in 1980s

• Different design style and coding rules for designing partially-reconfigurable designs• More “low-level” than non partially-reconfigurable designs• Designer is very involved in placement of modules and primitives• Unique rules for code structure and components specific to partial

reconfiguration, e.g. ICAP memories

• Many practical challenges• Programmability, FPGA vendor specific designs

• Possible reasons for renaissance: bigger FPGAs and Cloud FPGAs → Multi-tennant FPGAs

4EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019 Background text from [8]


Reconfiguration of FPGA Logic

FPGAs configuration and reconfiguration can be classified based on how often it is performed

5EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019

When is FPGA logic updated?

Configure once and deploy

Effectively replace ASIC for low-volume deployments where making ASIC is not

profitable

Configure or reconfigure multiple times

Configure few times

Configure regularly

Allow configuration few times when device is deployed in the field, e.g. network switches The “usual” use-case

of FPGAs

Reconfigure at runtime

Update part of the FPGA design when the

FPGA is running


Advantages of Partial Reconfiguration

• Partial reconfiguration is useful to allow FPGA to time share the FPGA logic and load different designs when workloads change:

• Reduce required FPGA size if different modules can be loaded/unloaded at different times• Reuse FPGA logic (CLBs, FFs, etc.) for different designs

• Reduce power if different modules are not run at the same time• Adapt to changing computations at runtime if different modules can be loaded based on currently

needed computation• More modular design: basic logic region is fixed, only change the reconfigurable partition

• Disadvantages of partial reconfiguration:• Vendor-specific work flow• FPGA reconfiguration duration• Design complexity to set up

reconfiguration region and develop logic that can interact with the reconfigurable region

6EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019

Reconfiguration typically takes ms to perform; depends on FPGA size and bitstream size, plus

any overhead to activate the logic


Components of Dynamically Reconfigurable Design

• Static partition is the region that is not changing• Contains user’s logic• Additional logic for interfacing with the reconfigurable partition

• Reconfigurable partition is the region that can be configured dynamically at runtime• Configuration memory stores the FPGA configuration for the FPGA partitions defining the

current operation of the FPGA• Often uses SRAM cells• Can be loaded from flash memory as for storing bitstreams• Or load from JTAG

• Partition interface is part of the routing where thereconfigurable partition connects to the static partition

• All modules loaded into the FPGA need to usethe same interface



FPGA Structure Review


Column-based FPGA image from [1],CLB details image from [2]

Col

umn-

base

d FP

GA

desi

gn

CLB and routing matrix configuration registers

• Typical FPGA is designed using column-based style• CLBs are basic blocks that can be configured

• Configuration bitsfor each CLB are stores in SRAM cells

• CLBs are connectedto each other throughrouting matrix

• Configuration bitsfor each matrix arestored in SRAM cells


FPGA Bitstream

EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019 9CLB and bitstream details image from [2]

• FPGA bitstream is a stream of bits that is sent to the FPGA to configure the CLBs, routing matrix and any other elements

• All configuration SRAM cells are connected as a shift register• JTAG connection is used to shift in the configuration data• Similar to a scan-chain

• At configuration time data is shifted in to set the right connections,LUT contents, etc.

CLB

and

rout

ing

mat

rix

conf

igur

atio

n re

gist

ers

Each configurable bit has a position assigned in the

bitstream, often bitstream format is proprietary


Partitioned FPGA Bitstream and Configuration Frames

EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019 10Bitstream detail images from [2]

• If all configurable cells were made into one scan chain, then parts of the FPGAcannot be reconfigured at runtime

• Need to configure whole FPGA at once• Modern FPGAs break up the configurable cells in FPGA into frames

• Bitstream contains the configuration data for the SRAM cells• And address information about which frame to load the configuration into

CLB

and

rout

ing

mat

rix

conf

igur

atio

n re

gist

ers

Con

figur

atio

n re

gist

ers

with

ro

w a

nd c

olum

n de

code

rs fo

r pr

ogra

mm

ing

parts

of t

he

FPG

A

Each frame configures parts of a column


FPGA Bitstreams and Frames

• FPGAs are configures by writing configuration bits into the configuration memory• Configuration memory is organized in small blocks called frames• Multiple frames are required to program the FPGA, typically multiple frames per column• For example, Virtex Series 6 frames:

• Have size of 81 x 32 bits (81 words)• Contain configuration for both routing matrix and CLBs• Meanwhile, typical bitstream has size of 2 to 20MB → 1000s of frames per FPGA

EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019 11Block diagram from [2]

Con

figur

atio

n re

gist

ers

with

ro

w a

nd c

olum

n de

code

rs fo

r pr

ogra

mm

ing

parts

of t

he

FPG

A

Each frame configures parts of a column


Bitstreams, Frames, and Frame Addresses

• Bitstreams are broken down info frames they program• Addressing is done based on location of the tile

in the FPGA


Image from [3], frame addressing image form [4]

Frame address:• Row address• Top/Bottom row• Major Address• Minor Address• Block type

• Logic Blocks• BRAMs• Routing Blocks


Partition Interface: Partition Pins

• Partition pins are used in modern Xilinx FPGAs as an interface between the static partition and the reconfigurable partition

• These are the physical interface points between static and reconfigurable logic • They are anchor points within an interconnect tile through which each IO of the

reconfigurable module must route

EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019 13Figure from [5]

Bus Macro LUT Based Partition Pins


Methods for Reconfiguration

• External reconfiguration• JTAG port

• Internal reconfiguration• Though the Internal Configuration Access Port (ICAP)

using an embedded microcontroller or state machine

• ICAP interface allows:• Read and write the FPGA

configuration at run time• Allows for automated runtime

reconfiguration by changing ICAP memory


Image from [2], table from Xilinx manuals taken from [2], HWICAP image from [6]

ICAP interface used to update reconfigurable partitions logic

Xilinx uses AXI interface for ICAP


Partial Reconfiguration Partitioning Styles

• Different partitioning styles are possible:a. Island Styleb. Slot-basedc. Chunk-based

• Partitioning style affects placement and flexibility of the design• Once selected, a partition defines the smallest area a module can be assigned

• Can have a lot of unused area• May have to reserve area for biggest anticipated module

EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019 15Image from [7]


Example Layout of Partial Reconfiguration Region

• Xilinx uses pblocks to definethe partial reconfiguration regions

• Design is routed within pblock• The blocks are then inserted into

design and connected to the restof FPGA logic

• Example floor plan with a pblockfor AES module

EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019 16Image from [7]


Design Considerations: Power and Timing

Power:• Power reduction, since different modules are loaded at different time• But partial reconfiguration itself requires power• Power during partial reconfiguration is spent in:

• Configuration data access• Spent on the configuration controller • Off/On chip Memory access• Programming interface, ICAP

• Actual configuration of FPGA Resources

Timing:• Reconfiguration takes time, during which the reconfigurable logic cannot be used

• Varies by type of reconfiguration• Size of region affects reconfiguration time

• FPGA maximum frequency may drop due to extra reconfiguration logic

EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019 17Text from [2]


Challenges and Use-Cases of Partial Reconfiguration

Challenges:• Complicated design flow and vendor-specific tools and configuration• Have to re-do for each type of FPGA chip• Potential security issues if bitstream is sensitive and stored in ICAP• Decrease performance as compared to full configuration

Use-cases• Cryptography

• Change algorithm based on current operations (e.g. encryption vs digital signatures)• Networking

• Change packet processing algorithm based on traffic• IoT

• Different signal processing or machine learning modules based on current operation of the Iot device

• Multi-tennant Cloud FPGA

EENG 428 / ENAS 968 – Cloud FPGA© Jakub Szefer, Fall 2019 18Catapult board image from [6]

Allow many users to share the same FPGA, similar to

VMs on regular CPUs


References

1. Chen, Shih-Chun, and Yao-Wen Chang. “FPGA placement and routing.” Proceedings of the International Conference on Computer-Aided Design, 2017.

2. Ali Akoglu. “Partial Reconfiguration Using FPGAs: Architecture.” ECE 506 Reconfigurable Computing course. Slides available at: http://www2.engr.arizona.edu/~ece506/project/2014/PartialReconfiguration/presentation/partial_reconfiguration_architecture.pptx

3. “A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAS.” Proceedings of the International Conference on Field Programmable Logic and Applications, 2009.

4. “Virtex-5 FPGA Configuration User Guide.” Available at: https://www.xilinx.com/support/documentation/user_guides/ug191.pdf.

5. Matthijs van Minnen. “Analysis and Rerouting of Netsfor Partial Reconfigurable FPGADesigns using RapidSmith2.” Available at: https://pdfs.semanticscholar.org/13ec/d96c879c5cc1142e0a2dd4bde948903b5586.pdf.

6. “AXI HWICAP v3.0 LogiCORE IP Product Guide.” Available at: https://www.xilinx.com/support/documentation/ip_documentation/axi_hwicap/v3_0/pg134-axi-hwicap.pdf.

7. Dirk Koch. “Partial Reconfiguration on FPGAs: Architectures, Tools and Applications.” Springer, 2012.


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