ece 477 design review team 7 spring 2007 joe land ben fogle james o’carroll elizabeth strehlow

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ECE 477 Design Review Team 7 Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

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Page 1: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

ECE 477 Design Review Team 7 Spring 2007

Joe Land

Ben Fogle

James O’Carroll

Elizabeth Strehlow

Page 2: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Outline• Project overview • Project-specific success criteria• Block diagram• Component selection rationale• Packaging design• Schematic and theory of operation• PCB layout• Software design/development status• Project completion timeline• Questions / discussion

Page 3: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Project Overview

• Modern active loudspeaker system – Intended for consumers– Replaces audio receiver/passive loudspeaker

combination

• Digital manipulation of sound field– User controlled direction– Allows for non-ideal placement in a room

Page 4: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Project-Specific Success Criteria

1. An ability to receive and act upon command from an IR remote.

2. An ability to delay-steer the wave-front of a loudspeaker array (up/down, left/right).

3. An ability to amplitude-shade the wave-front of a loudspeaker array (adjust effective array length).

4. An ability to perform (third-octave) amplitude equalization.

5. An ability to control loudspeaker settings thorough a user interface.

Page 5: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

ADSP-21262

Analog Switch

Parallel Port

SPI

AD1835A

SRAM

4MB

Audio Pre-A/D Analog Circuit

JTEG Header

L

R

x 2

Audio Inputs

Audio Post D/A Analog Circuit

10W Class D Power AmplifierCODEC

DSP

2” Speaker

55W Class AB Power Amplifier 8” Subwoofer

x 8

FLASH

8MB

25 MHz Oscillator

JTEG Port

Reset PB Control/User Interface Header

DAI

Power Supply

+12V 8A

+ A5V 2A Power Regulation

+5V +3.3V +1.2V

Parallel Port

Active Loudspeaker Unit

ID Switch

Block Diagram

Page 6: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Block Diagram

Control Box

I/O

ATmega16

Touch Button Controller

8 Touch Buttons 8

Program Header

Infrared 36kHz Sensor Int.

Serial to Video ConverterSCI

5.5” LCD TV

SPI

Control/User Interface Header

μC

Power Regulation

+12V +5V +3.3V

Page 7: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Component Selection Rationale

• Microcontroller– ATmega16– Freescale 9S12

• DSP– ADSP-21262 SHARC: Development Environment– TI Aureus™ TMS320DA708

• Audio amplifier – TPA3001D1: Class D– TDA2006: Class AB

Page 8: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Packaging Design

40”

9” 12”

12”

Active Loudspeaker Unit

2” Loudspeaker

8” Subwoofer

Array of 8 Loudspeakers

Enclosure (MDF)

Small Sealed Chamber for each 2” Loudspeaker

Sealed Chamber for each 8” Subwoofer

Power Supply

Subwoofer Amplifier

DSP and 8 Channel Amplifier Board

Dimensioned Drawing Cut-away Drawing

Front View Side View Front View Side View

Page 9: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Packaging Design

Control/User Interface

User Interface

Volume

+

-

Input

CD

TV

7.5”

5.0”

2.0

User Interface

Volume

+

-

Input

CD

TV

Capacitance Touch Buttons

5.5” LCD TV Monitor

Lexan® Cover

Molded Fiberglass Case

Standoff

Prototype Board for User Interface

Touch Button Sensor

Video OUT (TV)

IR Sensor

Page 10: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

DSP/Reset• Major Components:

– DSP: ADSP-21262– Wireless Transceiver: TRF-2.4G

• Other Components:– Supply Voltage Monitor: ADM708SARZ– 25MHz Oscillator: SGR-8002DC-PCC-ND– SPI Header– JTEG Header

Page 11: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

TCK

DAIP16_SPDIF_GPO0

RD

+3.3V_DSP

C4

0.1uF

DSP_CLKIN

TRST

DAIP15_SPDIF_SPI_CS

SPIDS

WE

C51000pF

C10.01uF

TDI

DAIP14_DAC_LRCLK

C61000pF

ALE

C71000pF

DAIP13_DAC_BCLK

C81000pF

DSP_CLKOUT

DAIP12_DAC_D1

R154.7K

DSP_CLKIN

C90.01uF

RESET

DAIP11_DAC_D2

C100.01uF

542

7

810

69

3 1

DataJ61

TRF-2.4G

FLAG1_SW1

+1.2V_DSP

DAIP15_SPDIF_SPI_CSDAIP16_SPDIF_GPO0

DAIP10_DAC_D3

1234

8765

SW1

SW DIP-4/SM

C110.1uF

R510K

MISO

+3.3V

R610K

C120.1uF

R1310K

ADIP9_DAC_D4

R2

0

R3

0

MOSI

C1310uF

DA_SOFT_RESET

RESET

D2LED (RED)

C680.01uF

D3LED (GREEN)

DAIP8_ADC_LRCLK

+3.3V

R53270

R710K

SW10

SWT013/MOMENTARY

MR1

VCC2

PFI4

PFO5

RST8

RST7

U22

ADM708SARZ

R5110 K

+3.3V

R14

33

+3.3V

R52270

EMU

SPICLK

+3.3V

R810K

753

2

68

14

9 1011 1213 14

J41

JTEG HEADER

TCK53

2

6

14

J42

SPI HEADER

TDITRST

TDO

EMU

TMS

+3.3V_DSP

DAIP7_ADK_BCLK

+3.3V

TDO

+1.2V_DSP

+3.3V

+1.2V

DAIP6_AD1835_MCLK

+3.3V

SHUTDOWN

Place R1, C1 and C2as close as possibleto pins 131 and 132of DSP

OE1 OUT

3

GND4VCC

2

Y1

25 MHZ

R7610K

+3.3V_DSP

DAIP5_ADC_DATA

+3.3V

SPICLK

AD0

SIGNAL_IN_BSIGNAL_IN_A

GND16

VDDEXT17

VDDEXT673

VDDEXT793

VDDEXT221

VDDEXT331

VDDEXT445

VDDEXT559

VDDEXT8116

VDDEXT9130

VDDEXT10144

VDDINT623

VDDINT11

VDDINT29

VDDINT311

VDDINT413

VDDINT519

VDDINT727

VDDINT836

VDDINT937

VDDINT1154

VDDINT1260

VDDINT1366

VDDINT1468

VDDINT1572

VDDINT1675

VDDINT1047

VDDINT21101

VDDINT22103

VDDINT25108

GND28

GND310

GND412

GND514

GND618

GND720

GND822

GND928

GND1032

GND1138

GND1244

GND1348

GND1455

GND1558

GND1661

GND1797

GND1869

GND1974

GND2076

GND2285

GND2391

GND2492

GND2595

GND27102

GND28104

GND29106

GND30109

GND32113

GND33115

GND35119

GND36123

VDDINT1783

VDDINT1890

VDDINT1996

VDDINT23105

VDDINT2099

VDDINT24107

VDDINT26110

VDDINT27112

VDDINT28114

VDDINT29118

VDDINT30120

VDDINT31124

VDDINT32129

GND2184

GND31111

GND26100

GND34117

GND37128

GND38133

GND39141

AVSS132

AVDD131

U8A

ADSP-21262

AD1

C141000pF

C151000pF

C161000pF

C171000pF

AD2

C180.01uF

C190.01uF

C200.1uF

C210.1uF

C2210uF

DAIP1/SD0A53

AD034

AD525

AD624

AD133

AD230

AD329

AD426

AD717

AD852

AD951

AD1050

AD1149

AD1246

AD1343

AD1442

AD1541

RD39

WR35

ALE40

EMU135

TMS140

TCK139

TRST138

TDI137

TDO136

CLKOUT134

CLKIN142

XTAL143

RESET121

DAIP2/SD0B56

DAIP3/SCLK057

DAIP4/SFS062

DAIP5/SD1A63

DAIP6/SD1B64

DAIP7/SCLK165

DAIP8/SFS170

DAIP9/SD2A71

DAIP10/SD2B77

DAIP11/SD3A78

DAIP12/SD3B79

DAIP13/SCLK2380

DAIP14/SFS2381

DAIP15/SD4A82

DAIP16/SD4B86

DAIP17/SD5A87

DAIP18/SD5B88

DAIP19/SCLK4589

DAIP20/SFS4594

MISO126

MOSI127

SPICLK125

SPIDS122

FLAG015

FLAG116

FLAG297

FLAG398

BOOTCFG04

BOOTCFG15

CLKCFG02

CLKCFG13

U8B

ADSP-21262

1234

J46

Free I/O

AD3AD4

R110

C20.1uF

AD5

MOSI

R184

1K

+1.2V_DSP

AD6

R410K

AD7AD8

FLAG3_AD1835_SPI_CS

MOSIMISO SPIDS

SPICLK

+3.3V

FLAG2

AD9

C30.1uF

AD10AD11

R91.2K

AD12

R101.2K

AD13AD14

R111.2K

DAIP18_SPDIF_IN

AD15

R121.2KMISO

R185

1K

TMS

DAIP17_AUDIO_OSC

Schematic/Theory of Operation

DSP/Reset

Page 12: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

Memory

• Major Components:– SRAM: CYC1049CV33– Flash: M29W800DB

• Other Components:– Decoder/Demultiplexer: 74LVC138AD– D-type Latch: 74LVC373APW

Page 13: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

Memory

AD1A8

AD8AD9

AD11AD10

AD13AD14AD15

AD2A9

AD12

AD3A10

AD4

A8A9

A10A11

A11

A12A13A14A15

AD5A12

FLASH_CS

AD6A13

RD

AD7

A16A17A18

A19

A14

WE

AD0

AD8

A15

SRAM_CS

SRAM4 Mb (512K x 8-bit)

AD9A16GND

8

Y015

Y114

Y213

Y312

Y411

Y510

Y69

Y77

A1

B2

C3

G2B5 G2A4 G16

VCC16

U9

74LVC138AD

RD

R1610K

AD11

+3.3V

A17

WE

AD12

D110

D213

D314

D431

D532

D635

D736

WE15 OE37

NC944

CE8

VDD111

AD83

AD94

AD105

AD116

AD127

A819

GND34GND12

VDD233

NC422

NC843

NC523

NC624

NC742

NC321

NC11

NC22

D09

AD1316

AD1417

AD1518

A920

A1026

A1127

A1228

A1329

A1430

A1538

A1639

A1740

A1841

NC/A1925

U13

CYC1049CV33

A18AD10A19

+3.3V

AD13

RESET

A21

A20

AD14

A22

A21

AD15

A23

A22

ALE

AD1AD2AD3AD4AD5AD6

FLASH_CS

AD7

AD0

A23

SRAM_CSLED_CSEXP_CS1

DQ131

DQ233

DQ335

DQ438

DQ540

DQ642

DQ744

W11 G28

RP12

E26

VCC37

A025

A124

A223

A322

A421

A88

VSS246VSS127

RB15

NC19

NC210

DQ029

A520

A619

A718

A97

A106

A115

A124

A133

A142

A151

A1648

A1717

A1816

DQ15A-145

BYTE47

NC313

NC414

DQ932

DQ1034

DQ1136

DQ1239

DQ1341

DQ1443

DQ830

U14

M29W800DB

EXP_CS2

AD8AD9

AD11AD10

AD13AD14AD15

AD12

A8A9

A10A11A12A13A14A15

A16A17A18

VCC20

GND10

8D18

1Q2

2D4

3Q6

7Q166D

14 5Q12

1D3

2Q5

3D7

4Q9

4D8

7D17

5D13

LE11

6Q15

OE1

8Q19

74LVC373APW

U11

A19

Flash8 Mb (1M x 8-bit)

VCC20

GND10

8D18

1Q2

2D4

3Q6

7Q166D

14 5Q12

1D3

2Q5

3D7

4Q9

4D8

7D17

5D13

LE11

6Q15

OE1

8Q19

74LVC373APW

U12

AD1AD2AD3AD4AD5AD6

AD0

AD7

+3.3V

+3.3V

ALE

C23

0.01u

C250.01u

C260.01u

C270.1u

C280.01u C29

0.1uC300.01u

+3.3V +3.3V

+3.3V+3.3V

Page 14: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

Audio Path

• Major Components:– Codec: AD1835AASZ– Class-D Audio Power Amplifier: TDA3001D1

• Other Components:– Quad SPST Switch: ADG412BR– Low Noise Op-amps: AD8606ARZ – 12.288MHz Oscillator: SGR-8002CA-PCC-ND

Page 15: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

Audio Input

INPUT SELECT

SIGNAL_IN_B

SIGNAL_IN_A

+12V

C127

100nF

+5V

C128

100nF

IN11

GN

D5

IN48 IN39

VL

12

IN216

D12

D215

D310

D47

S13

S214

S311

S46

VD

DA

13

VS

SA

4

U21

ADG412BR-ND

-12V

C129

100nF

2

1

R1J35

RCA

2

1

R2J36

RCA

+

C90100pF

C91

10uF

L4

600

AUDIO_VREF_ADC

AUDIO_VREF_ADC

+

C92100pF

C93

10uF

L5

600

R46

5.76K

LINE INPUTS

2

1

L1 J31

RCA

2

1

L2J32

RCA

R47

5.76K

R48

750.0K

C60120pF

+

C86100pF

C87

10uF

A5V

L2

600

R43

11.0K

R44

5.49K

R45

5.49K

C85

0.22uF

R49

237.0

R50

237.0

3

21

-

+

U25A

AD8606ARZ

C61

100pF

C621000pF

5

67

84

-

+

U25B

AD8606ARZ

C631000pF

C58

680pF

C59

680pF

+

C88100pF

C89

10uF

L3

600

AUDIO_VREF_ADC

AUDIO_VREF_ADC

R68

5.76K

R69

5.76K

R70

750.0K

C83120pF

A5V

R71

11.0K

R72

5.49K

R73

5.49K

C94

0.22uF

R74

237.0

R75

237.0

3

21

-

+

U26A

AD8606ARZ

C84

100pF

C951000pF

5

67

84

-

+

U26B

AD8606ARZ

C961000pF

C97

680pF

C98

680pF

Page 16: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

Analog Audio AGNDAD1835

AGND

AD1835AD1835

OSCOUTRP1OUTRN1OUTLP1OUTLN1

DAIP5_ADC_DATAOUTRP2OUTRN2OUTLP2OUTLN2

OUTRP3OUTRN3OUTLP3OUTLN3

R2410K

DAC3

DAC2

DAC1

ADC

DAC4

OUTRP4

C350.1uF

OE1 OUT

3VIN

2

GND4

Y2

12.288 MHZ

OUTRN4

R26

33

C360.01uF

OUTLP4OUTLN4

C42

0.1uF

C370.1uF

+3.3V

C380.1uF

C390.1uF

ADC_DATA

MISO

++

C400.1uF

DAIP12_DAC_D1DAIP11_DAC_D2

R23

0 DNP

DAIP10_DAC_D3

1234

8765

SW2

SW DIP-4/SM

DAIP8_ADC_LRCLK

DAIP9_DAC_D4

DAIP5_AD1835_MCLK

MOSI

SPICLK

ADC_BCLK

AD1835_SPI_CS

DAIP7_ADC_BCLK

RESET

+3.3V+3.3V

ADC_LRCLKR2510K

DAIP13_DAC_BCLK

FER1

600

DAIP14_DAC_LRCLK

MASTER_SLAVE

DSDATA141

DVDD239

ADCLN20

ADCLP21

ADCRN22

ADCRP23

OUTRP19

OUTRN18

OUTLP17

OUTLN16

OUTRP215

OUTRN214

OUTLP213

OUTLN212

OUTRP328

OUTRN327

OUTLP326

OUTLN325

CLATCH2

ODVDD48

CCLK51

DVDD11

DSDATA343 DSDATA242

DSDATA444

MCLK47

CIN3

COUT50

DGND140

DGND252

AGND635

AGND424

AGND15

AGND530

AGND210

AGND316

AVDD329

AVDD111

AVDD219

FILTR18FILTD17

PD/RST4

M/S36

DLRCLK37 DBCLK38

ASDATA49 ALRCLK46 ABCLK45

OUTRP434

OUTRN433

OUTLP432

OUTLN431

U15

AD1835AASZ

+5V+3.3V

+3.3V

A5V

AUDIO OSC

1234

8765

SW3

SW DIP-4/SM

DISCONNECTS SIGNALS FROM SPI FLASH AND AD1835

FLAG3_AD1835_SPI_CS

R1910K

A5V

C247

0.22uF

3

21

-

+

U63A

AD8606ARZ

5

67

84

-

+

U63B

AD8606ARZ

FLAG0_SPI_FLASH_CS

AD1835_SPI_CS

+3.3V

SPI_FLASH_CS

A5V

+5V_B

AUDIO_VREF_ADC

A5V

DAIP6_AD1835_MCLK

AUDIO_VREF_DAC

R22

6.04K

R20

6.04K

R21

6.04K

DAIP17_AUDIO_OSC

+3.3V+5V

C3110uF

C3210uF

C3310uF

MASTER_SLAVE

C3410uF

ADC_LRCLK

ADC_DATA

ADCLN

ADC_BCLK

ADCLPADCRNADCRP

Page 17: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

C78

1uF

R6151

C56

0.47uF

L7

2512067007Y3

C57

0.47uF

SHUTDOWN

A5V

C990.22uF

C79 1uF

R65120K

R35

11.0K

R36

5.49K

R37

2.74K

OUTLN1

OUTLP1

R38

1.65K

R395.49K

R40604.0

R4149.9K

C48330pF

C49680pF

C50

100pF

C51220pF C52

2200pF

C53

10uF

R42

3.32K

BSP17

PGND6 SHUTDOWN*5

BSN8

VREF23INP

2

OUTN11

INN1

OUTP15

OUTN10

PGND13OUTP14

PGND12

GAIN14 GAIN03

COSC21

PV_CC9

VCLAMP7

BYPASS22

ROSC20

V_CC24

AGND19

AGND18

PV_CC16

U27ATPA3001D1

12

J43PRE OUT L1

1 2

J44SPK OUT #1

+12V

3

21

84

-

+

U28A

AD8606ARZ

+

+

+

DAC1 LEFT

+ +

+

D4

B130-13

D5

B130-13

AUDIO_VREF_DAC

+

+

+

+

+

+

C1021uF

C8210uF C80

1uF

C100

1uF

+12V

C132

1nF

C134220pF

R189120K

C133

1nF

C77 1uF

R190120K

R63 0 DNP

+12V

L6

2512067007Y3

R64 0 DNP

R6251

C101

0.22uFC810.22uF

R60120K

Audio Out (1 of 8)

Page 18: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

Power• Major Components:

– Voltage Regulator: ADP3336ARMZ– Step-down Regulator: LTC1877– Step-down DC-to-DC Controller: ADP1864– P-channel MOSFET: FDC658P– Power Supply: Commercial Switching Supply

• Other Components– Through holes

Page 19: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

Power

TP2

32 146 5

J60

POWER INPUT HEADER

TP3

PGND

PGND

TP4

C2541000pF

C2551000pF

C25610uF

C2581uF

R186

0

C2570.1uF

ITH2

VFB3

SW5

RUN1

PLL_LFP8

GND4

SYNC_MODE7

VIN6

U24

LTC1877

55

44

66

33

11

22

U49

FDC658P D21SL22

D20

2A

R56

0R57

0 DNP

C7230pF

C7310uF

C741uF

C75220pF

C7610uF

R58124.0K

R59249.0K

+1.2V

C26510uF

C2660.1uF

14

23FER3

190MHz

L22

6.8uH

F1

FUSE

+12V -12V

UNREG_IN

L23

600

R173210.0K

L24

600

R17464.9K

R175

0

L1

10uH

+12V

+5V

IN5

CS4

PGATE6FB

3 COMP1

GND2

U45

ADP3336ARMZ

R178

24.9K

C2621uF

R176210.0K

R17764.9K

+5V_B

C2631uF

C2641uF

IN28 OUT1

1

OUT22

FB5SD

6OUT3

3

GND4

IN17

U44

ADP3336ARMZ

UNREG_IN

R179

80.6K

R1810.05

R180255.0K

UNREG_IN

R182

0

C2591uF

C2601uF

+

C26947uF

+

C26147uF

C267470pF

+

C2702.2uF

IN28 OUT1

1

OUT22

FB5SD

6OUT3

3

GND4

IN17

U43

ADP3336ARMZ

C2711uF

UNREG_IN

UNREG_IN

C26868pF

+3.3V

TP1

A5V

ADP1864

Page 20: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

Control Box

• Major Components:– Microcontroller: ATmega16– Wireless Transceiver: TRF-2.4G– Touch Buttons: E240B– IR Receiver: Radio Shack 276-640– Serial to Video Module: ezVID

Page 21: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Schematic/Theory of Operation

Control Box

PD519

PC325PC426PC527PC628PC729AVCC30GND31AREF32PA733PA634PA535PA436PA337PA238PA139PA040

PD418

PB01

PB12

PB23

PB34

PB45

PB56

PB67

PB78

RESET9

VCC10

GND11

XTAL212

XTAL113

PD014

PD115

PD216

PD620

PD317

PC224

PC123

PC022

PD721

U3

ATmega16

VID6

VID_GND5

VCC1

Tx2

Rx3

GND4

U4

ezVID

VID1

VID_GND2 VCC

4

GND3

U5

TV

+12

+5+5

+5

Out

3

Vs1

GND

2

U6

TSOP1836

+5

GND6 PB1

1

PB22

PB33

PB44

VDD5

U7 E240B

+5

R15K

C10.1m

+5

PA0PA1

SPICLK

MOSI

MISO

FLAG2

321 4

J45PIN HEADER

PA0PA1

DATA6

CLK15

VCC10

GND1

DR17

DR29

CE2

CLK23

DOUT28

CS4

U50A

TRF-2.4G

SPICLK

3.3V

MOSI

R187

1K FLAG2

MISO

R188

1K

+5

Page 22: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

PCB Layout

Page 23: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

PCB LayoutPower Supply

Page 24: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

PCB LayoutDSP/Reset/Memory

Page 25: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

PCB LayoutAudio In

Page 26: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

PCB LayoutAudio Out

Page 27: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Software Design/Development Status

Reset / Power-on

Software Initialization (Peripherals, Enable interrupts)

Command/Button flag set?

Reset flag. Update GUI. Transmit data to speakers.

Shift in packet contents

Process Packet

RTI

IRQ (Wifi)

Yes

No

Page 28: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Software Design/Development Status

Determine bit received and store it.

RTI

IRQ interrupt (IR sensor)

Set button flag

RTI

RTI interrupt

Button pressed?No

Yes

Whole command

recognized?

Set command flag

No

Yes

Page 29: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Software Design/Development Status

Hardware Boot(loads program from Flash)

Software Initialization

“New data” flag set?

Reset “New data” flag.Load new delays, amplitudes, and equalizer

coefficients.

Load new sample into equalizer buffer.

Equalize sample using FIR filter on buffer

Put equalized result into delay line buffer

Load elements with samples from delay line buffer.

RTI

Serial port received interrupt

Yes

No

Page 30: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Software Design/Development Status

Begin SPI DMA transfer of received data into memory

RTI

IRQ interrupt

Check received data for lost packet.

Send retransmit request via SPI DMA transferSet “New data” flag

RTI

SPI transfer complete

Lost packet?

Yes

No

Page 31: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Project Completion Timeline

Group Timeline Success Criteria (GTSC)

GTSC #1: March 2—Final PCB completeGTSC #2: March 19—Enclosures builtGTSC #3: March 30—Components

soldered GTSC #4: April 9—Working boardGTSC #5: April 27—Project completed

Page 32: ECE 477 Design Review Team 7  Spring 2007 Joe Land Ben Fogle James O’Carroll Elizabeth Strehlow

Questions / Discussion