OKAN UNIVERSITY ELECTRICAL AND ELECTRONICS ENGINEERING DEPARTMENT
EEE467 - Advanced Digital Design
Show sound signals on VGA with using PMOD MIC AHMET İLKER ŞİN
070203012
Outlines1 ) Project objective 7) Explain of code 2) Analogue to Digital Converting 8) VGA 3) Microphone SelectionDynamic microphonesCondenser microphonesElectret condenser microphone4) PMOD MICMicrophone Module Pre- amplifierCompandorPMOD MIC Block5) Functional Description TIMING FSM6) Design Procedures (Block Diagrams)
Project objective
The main objective of this project is to display an Audio signals on VGA screen. The initial objective of this project is to compare and evaluate the FPGA prototyping boards readily available in the market and a selection is to be made. The aim of this project will be to capture the sound from an audio signals via PMOD MIC and display the signal to reading on a VGA screen
Analogue to Digital Converting
The audio signal from microphone will be of analogue format. Therefore, a conversion to a digital format is needed as the FPGA is a digital electronic chip. Therefore an Analogue to Digital Converter (ADC) component is needed. This component will convert a continuous signal to discreet digital numbers.
ADCs have resolution which is the number of the discreet values that it can produces over a range of analogue values. For example, For a Full scale measurement range of 0 to 10 volts, if the ADC resolution is 12 bits (212 = 4096 quantization levels (codes)), the ADC voltage resolution will be (10V - 0V) / 4095 steps = 10V / 4095 steps 0.00244 V/step 2.44 mV/step
Microphone Selection
There are three different types of microphones available
Dynamic microphones: An ideal one for general purpose with simple design with few moving parts and is sturdy and resilient to rough handling. This type of microphones are more likely suitable for handling high volume (e.g. from musical instruments or amplifiers). They have no internal amplifier and do not require batteries or external power.
Condenser microphones: This type of Microphones requires power from a battery or external source (called "phantom power"). The audio signal out from the microphone is stronger signal than that from a dynamic. They are also more sensitive and responsive than dynamics, making them well-suited to capturing subtle nuances in a sound. However, they are not ideal for capturing high volume as the high level of sensitivity makes them prone to distortion. A condenser simply means capacitor, where energy is stored in the form of an electrostatic field. This type of microphone, which uses a capacitor to convert acoustical energy into electrical energy.
Microphone Selection
Electret condenser microphone: This microphone uses a special type of capacitor which has a permanent voltage built in during manufacture. Like a permanent magnet, in that it doesn't require any external power for operation. Therefore a power source (e.g. a battery or “phantom Power” is not required. The other feature is the same as a normal condenser microphone
Microphone Selection
The selection of the suitable microphone depends on the Sensitivity and Frequency range criteria
Microphone Selection
Sensitivity: This determines how much voltage is generated per units sound pressure level (mV/Pa). A more sensitive microphone of 50 or 100Mv/Pa normally large) is required if there’s a need to characterize lower level sounds. For louder sound like jet aircraft, a less sensitive microphone is sufficient
Frequency range: the audible range is 20 to 20 kHz and many microphonesextend well beyond this.
PMOD MIC
Knowing and going through all those above selection criteria, the decision to choose the suitable microphone was made simple by DIGILENT as there is a preinstalled microphone a peripheral board for FPGA prototyping boards comes with a very low cost This I/O interface board called PMOD MIC has been specifically designed for use with DIGILENT and XILINX development kits which will work on an SPI interface via 6 accessories header pins I/O peripheral ports
PMOD MIC
This board consists of an analogue microphone, an SA575DTB IC which is a compandor chip and ADCS7476 chip which is an Analogue to Digital Converter (ADC). The Compandor IC is connected as an Automatic Level Configuration (act as a pre-amplifier) and the ADC converts the analogue volts into 12bit digital code
Microphone Module
Pre- amplifier
In order to amplify a low level audio signal such as pickup, microphone, turntable, into line level signals, a pre-amplifier (or pre-amp) is needed. This component provides a voltage gain but not significant current gain
Compandor
Companding is a process in signal processing that mitigates the detrimental effects of a channel with limited dynamic range. There’s an electronic component that can per form this process called a compandor
The Differences of an analogue signal before and after companding
PMOD MIC Block
The block diagram of PMOD microphone can be illustrated as in Figure PMOD MIC Block diagram takes in analog sound through microphone and outputs a digital sound signal
PMOD MIC Block
This block will need to be programmed to accept the analog audio signal from the microphone to go through the pre-amp and finally to convert the Analog signal into a 12 bit digital data signal. The PMOD MIC board needs to be powered with a supply voltage of minimum 2.7 V to maximum 5.25V. From the J1 and J18 peripheral board a 3.3V and GND is pre routed and ready for use without programming. For the ADC, there’s a need to input a 12.5MHz (max. 20MHz) to clock input. This is where the 50 MHz clock supply on FPGA boards will be divided and supply back to the input. Next is the chips select signal (low) which will inform the ADC to perform conversion once there’s logic 0. Those are the physical Input/ output (I/O) connection required
PMOD MIC Block
ADC Connection Diagram (left) and Block Diagram (right).
PMOD MIC BlockThe function of this block is not changed from previous revision. The connection diagram from PMOD MIC board to FPGA are shown in Figure below
PMOD MIC board
FPGA BOARD
B2 A3 MISO SCK
PMOD MIC Block
In this block, the FPGA needs to be programmed to take in the digital ADC codes and perform some averaging in order to determine the average voltage level over the continuous signal . In the case of a set of n values , the RMS value is given by
VRMS Calculation
Functional DescriptionThe input ports are a 50MHz clock, an asynchronous reset button, and the data from the ADCS7476 that is serially shifted-in on each clock cycle (SDATA). The outputs are the SCLK signal, which clocks the PmodMIC at 12.5MHz; a chip select signal (nCS), which enables the ADCS7476 chip on the PmodMIC; and as the 12-bit output vector (labeled DATA) from the ADCS7476 chip, which can be used by any external component. The START signal is used to tell the component when to start a conversion. After a conversion is done, the component activates the DONE signal. A block diagram of the component is shown in Figure
TIMING
The timing diagram in Figure is used to determine the correct timing sequence for the finite state machine that clocks the PmodMIC. It is the timing sequence that is used to generate 16 bits of data using the ADCS7476 chip inside the PmodMIC. The signal nCS must be at a low or zero state while the data is generated on the falling edge of the clock signal. Immediately following the data transfer, the signal nCS must be driven high to signal when a new set of data can be generated
TIMING
Timing Diagram of the ADCS7476 Chip on the PmodMIC
FSMThe logic that created the timing sequence to take in the data input SDATA serially and latch in the 16-bit vector, as well as clock the nCS and SCLK outputs, was designed by creating the finite state machine shown in Figure
FSM of the PmodMIC Reference Component
There are three states: Idle, ShiftIn, and SyncData. During the Idle state, the DONE output signal needs to be high in order to allow a conversion. When the START signal is going high, the state machine goes into the ShiftIn state.
In the ShiftIn state, the DONE signal goes low and the data from the PmodMIC is serially shifted-in from MSB to LSB for 16 clock cycles to ensure that all 16 bits of data have been received from each chip. After shifting is done, the state machine goes into the SyncData state.
In the SyncData state, the effective data received from the PmodMIC is placed on the 12-bit output port DATAIn the SyncData state, the effective data received from the PmodMIC is placed on the 12-bit output port DATA
If the START input signal is low the machine goes back to the Idle state, ready to accept another conversion
No mater what the current state is, the RST input signal resets the state machine and puts it into the Idle state
FSM
Design Procedures (Block Diagrams)
The FPGA needs to be programmed in order to produce the output corresponding to the analogue input level from a microphone During the research period, the block diagram of an Sound Meter using FPGA was proposed. The diagram shows some fundamental concepts in different blocks below in Figure
PMOD MIC
Mıcrophone
Preamp
ADC(12 bit)
Preamp
Clock Converter( 50 to 12.5 MHZ)
Counter 4- bit
FSM
Analog I/O Interface
Fılter
Fılter
Analogue to Dıgıtal Converter
Amplifiers
FPGA Chip
VG
A O
UTPU
T
Keeping in mind that the different in the FPGA chip, the appropriate HDL codes planned to be written to design the FPGA chip to generate the output correctly. As most of the designs using FPGA done we using VGA screen. This project will explore on the display on VGA Screen
Design Procedures (Block Diagrams)
Explain of code
This program incorporates the Moore State Machine and a clock divider.This program has four inputs and outputs. The signals are explained in the Table
FPGA Board
FPGA Board
Signal Naming in PMODMic.vhd program
In this program, the state machine comprises of three states, Idle, Shit-In and Sync DATA. The Idle state is the beginning state where nCS and DONE will be 1. When START signal is set to one, the State will now enter Shift In mode where nCS and DONE will be 1. A counter will count till 15 to serially shift in the 16 bits SDATA information from the microphone through the compandor. When the counter hits 15, the 12 bit information from SDATA signal (MSB to LSB) will be captured into DATA and output from ADC. At this point of time nCS and DONE signals will turn to 1 to disable the ADC and tell the program that a conversion is completed. The START signal will then become 0 and the finite state machine will go into Idle state again. In any point of the state the RST button is pressed, the state will go into Idle
Explain of code
Explain of code This program was designed to meet the timing requirements in the ADC datasheet.
Timing diagram for ADCS7574 ADC chip on PMOB MIC board
In addition, the 12.5MHz clock pulse for ADC was also created using the Digital Clock Module (DCM) .This feature replaces the clock divider process
VGA
Stands for "Video Graphics Array." It is the standard monitor or display interface used in most PCs. Therefore, if a montior is VGA-compatible, it should work with most new computers. The VGA standard was originally developed by IBM in 1987 and allowed for a display resolution of 640x480 pixels. Since then, many revisions of the standard have been introduced. The most common is Super VGA (SVGA), which allows for resolutions greater than 640x480, such as 800x600 or 1024x768. A standard VGA connection has 15 pins and is shaped like a trapezoid
VGA
A VGA signal contains 5 active signalsTwo TTL compatible signals for synchronizationHSYNC – horizontal synchronizationVSYNC – vertical synchronization
VGA In standard VGA format, the screen contains 640x480 pixels
–640 pixels in a row– 480 rows The standard refresh rate for a screen is = 60 Hz– The entire screen is refreshed 60 times per second
VGAEach VGA monitor uses a clock that determines when each pixel is updated This clock operates at the VGA-specified frequency of 25.175 MHz.Basis for the 25.175 MHz clock –Includes pixel processing time, horizontal and vertical synchronization times and guardband times – [640 (pixels/row) + 160 ] x [480 (rows) + 45 ] x 60 (refreshes/second)
