Review for Midterm: CPE 329 Fall 2007Review for Midterm: CPE 329 Fall 2007
•• Lectures 1Lectures 1--7, Chapters 1 & 2, Labs 17, Chapters 1 & 2, Labs 1--22•• Exam Review OutlinesExam Review Outlines•• Homework problemsHomework problems•• ISE/EDK technologyISE/EDK technology•• DigilentDigilent NexysNexys board technologyboard technology
–– Not held accountable for specifics of Not held accountable for specifics of DigilentDigilent D2FTD2FT--DIO5 technology, just principlesDIO5 technology, just principles
•• No coding, just pseudo code (no syntax)No coding, just pseudo code (no syntax)•• One side page of reference notes One side page of reference notes •• CalculatorCalculator
•• Course DescriptionCourse Description•• Course Learning ObjectivesCourse Learning Objectives•• Topics CoveredTopics Covered•• Prerequisite materialPrerequisite material•• Course MaterialCourse Material•• Lab OverviewLab Overview
–– Development Environment (CAD Tools)Development Environment (CAD Tools)–– Lab EquipmentLab Equipment–– ProcessorProcessor
•• Lab ExperimentsLab Experiments–– Experiment 1 HardwareExperiment 1 Hardware--Based Digital ClockBased Digital Clock–– Experiment 2 MicroBlaze Experiment 2 MicroBlaze ““Hello World!Hello World!””–– Experiment 3 MicrocontrollerExperiment 3 Microcontroller--Based Digital ClockBased Digital Clock–– Experiment 4 Function GeneratorExperiment 4 Function Generator–– Experiment 5 Final Design ProjectExperiment 5 Final Design Project
Exam Review Outline: lecture 1Exam Review Outline: lecture 1
•• Taxonomy of Digital SystemsTaxonomy of Digital Systems–– Advantages and Disadvantages of each categoryAdvantages and Disadvantages of each category ((Cost, Cost,
performance, ease of design, customization, configurability, performance, ease of design, customization, configurability, integration, number of transistors)integration, number of transistors)
•• Semiconductor Technology TrendsSemiconductor Technology Trends–– MooreMoore’’s Law Number of transistors per die doubles every s Law Number of transistors per die doubles every
couple of years (historical data) couple of years (historical data) http://www.intel.com/research/silicon/mooreslaw.htmhttp://www.intel.com/research/silicon/mooreslaw.htm
–– ITRS Future ProjectionITRS Future Projection–– Increase in the number of practicing engineers per yearIncrease in the number of practicing engineers per year–– Must work at higher levels of abstractionMust work at higher levels of abstraction
•• Increasing levels of abstraction for HW and SWIncreasing levels of abstraction for HW and SW–– Hardware Software CoHardware Software Co--designdesign
Exam Review Outline: lecture 2Exam Review Outline: lecture 2
HomeworkHomework1. In class we talked about field and factory programmable gate arrays. Which type of gate
array would have better performance? State the two primary reasons given in class that one will perform better than the other.
2. Hardware-based implementations typically have a performance benefit over stored-program digital systems. Explain why this is true?
3. Given that hardware-based implementations typically have a performance benefit over stored-program digital systems give three reasons that most embedded systems use either microprocessors or microcontrollers?
4. VHDL Alarm Clocka. Using the clock you designed for lab 1 we would like to add an alarm function. The system
requirement for the alarm function is to use another pushbutton to enter alarm mode. In alarm mode the alarm time should be displayed on the LCD and the hours and minutes pushbuttons should advance the hours and minutes of the alarm setting just as it did while setting the clock. There will be a module that asserts a logic signal called BUZZ if the current time matches the alarm time.
b. Reusing the modules that you used for lab 1 (Time_Keeper, Arbiter, and HEX2BCD as shown in the figure on the following page) draw a hardware diagram with the additional modules needed to add the alarm function and briefly describe (1-2 sentences / module) how each block should function.
5. In the first lab many students noticed that it was cumbersome to set the clock if the minutes and hours incremented every second during the set function. Determine how to have the set function increment every 0.5 seconds. Assume that you are supposed to minimize the changes to your current design and you can only use one system clock. Be sure to describe the conditions that are needed to increment the seconds, minutes, hours, and am/pm when in timekeeping mode.
6. In the lab we designed a Digital Clock using VHDL that was clocked with a 50MHz Epson oscillator. The frequency tolerance for the oscillator is: ∆f/f = +/- 50x10-6. Explain what are the sources of error in your digital clock and determine the maximum error that the clock would have after running for 1 day.
HomeworkHomework7. VHDL Design: Analyze the following VHDL code to answer the questions below:
entity state_machine isport( clk,S : in std_logic;
z :out std_logic );end state_machinearchitecture design of state_machine issignal NS : std_logic_vector ( 1 downto 0) :=”00”;beginsynch_proc: process (clk, S)
beginif (clk’event and clk=’1’) then
if(S=0) thenif (NS = “00”) then NS <= “01”;elsif(NS = “01”) then NS <= “10”;elsif(NS = “10”) then NS <= “11”;
elsif(NS = “11”) then NS <= “00”;endif;
endif;endif;
end process synch_proc;z <= NS(1);end design;
a. Draw the State Diagram for the VHDL code:_________________________________b. Complete the ModelSim simulated output for the state_machine circuit.______________c. Describe the function of the state_machine circuit? ____________________________
66
HomeworkHomework8. In the “Introduction to Digital Systems” chapter of the supplemental material
digital systems were first divided into two different categories. List the two categories and identify which one generally has higher performance. Also explain why this type of digital system has higher performance?
9. Does a factory programmed gate array or a field programmable gate array typically have better performance? List two factors that contribute to a performance advantage of one over the other.
10.10. You are asked to implement an algorithm using the tools availablYou are asked to implement an algorithm using the tools available to you in the e to you in the CPE 329 lab. The application requires the highestCPE 329 lab. The application requires the highest--performance design that you performance design that you can download into the Digilent D2FT board. You notice that the can download into the Digilent D2FT board. You notice that the algorithm is algorithm is computationally intense but does not have a significant amount ocomputationally intense but does not have a significant amount of inherent f inherent parallelism. Describe which approach and design tool you would parallelism. Describe which approach and design tool you would select. Also, select. Also, explain why you chose this approach.explain why you chose this approach.
11.11. Does a factory programmed gate array or a field programmable gatDoes a factory programmed gate array or a field programmable gate array e array typically use more silicon die area to implement a given VHDL detypically use more silicon die area to implement a given VHDL design? List two sign? List two factors that contribute to a area advantage of one over the othefactors that contribute to a area advantage of one over the other. r.
•• History of Integrated CircuitsHistory of Integrated Circuits•• Advantages of CPLDsAdvantages of CPLDs•• Programmable Elements to connect nets or configure hardware deviProgrammable Elements to connect nets or configure hardware devicesces
–– OneOne--timetime--programmable (OTP) programmable (OTP) –– Fuse/AntifuseFuse/Antifuse–– ReRe--programmableprogrammable
•• Volatile (SRAM)Volatile (SRAM)•• NonNon--Volatile (EEPROM, Flash)Volatile (EEPROM, Flash)
•• CPLD Architecture Functional BlocksCPLD Architecture Functional Blocks–– SPLD like configurable logic SPLD like configurable logic
–– MacroCellMacroCell–– MacroBlockMacroBlock
–– Programmable InterconnectProgrammable Interconnect–– I/O BlocksI/O Blocks
•• FPGA ArchitectureFPGA Architecture–– FPGA Fabric FPGA Fabric
•• Configurable Logic Block (Programmable MUX, Look Up Table, Pass Configurable Logic Block (Programmable MUX, Look Up Table, Pass Transistor)Transistor)•• Programmable InterconnectProgrammable Interconnect•• I/O BlocksI/O Blocks•• Block RAM MemoryBlock RAM Memory•• Hardcore blocks (ie Multipliers, PowerPC)Hardcore blocks (ie Multipliers, PowerPC)
–– System on Chip (Soc) using Hardcore or Softcore ProcessorsSystem on Chip (Soc) using Hardcore or Softcore Processors
Exam Review Outline Exam Review Outline –– lecture 3lecture 3
•• Programmable Interconnect (6Programmable Interconnect (6--transistor junction)transistor junction)–– Direct Direct –– CLB to CLBCLB to CLB–– LocalLocal–– GlobalGlobal–– Timing Timing –– Clock networksClock networks
•• Propagation delay timing for interconnect 1st order modelPropagation delay timing for interconnect 1st order model–– Wired interconnect tWired interconnect tPLHPLH–– Programmable interconnect tProgrammable interconnect tPLHPLH
•• Design Example of 8Design Example of 8--bit Ripple Carry Adderbit Ripple Carry Adder–– CPLD DesignCPLD Design
•• Full AdderFull Adder–– FPGA DesignFPGA Design
•• 22--bit adder subcomponentbit adder subcomponent•• LUT programming (Combining LUTs for more input variables)LUT programming (Combining LUTs for more input variables)•• Programmable interconnect Programmable interconnect
–– Adder Using VHDLAdder Using VHDL
Exam Review OutlineExam Review Outline
•• Design FlowDesign Flow–– DesignerDesigner
•• Write HDL CodeWrite HDL Code•• SimulateSimulate•• ConstraintsConstraints
–– CAD ToolCAD Tool•• SynthesisSynthesis•• Translate/MapTranslate/Map•• Place and RoutePlace and Route•• Generate Programming FileGenerate Programming File•• Download bit fileDownload bit file
•• Xilinx FPGA and CPLDXilinx FPGA and CPLDNote: emphasis on Spartan 3 Note: emphasis on Spartan 3
–– Spartan IIE FPGA ArchitectureSpartan IIE FPGA Architecture•• FPGA FabricFPGA Fabric•• I/O BlockI/O Block•• CLB and CLB SliceCLB and CLB Slice•• Product FamilyProduct Family
–– CoolRunner XPLA3 ArchitectureCoolRunner XPLA3 Architecture•• FeaturesFeatures•• Architecture Block DiagramArchitecture Block Diagram•• PLA Logic InputsPLA Logic Inputs•• Logic Block (MacroBlock)Logic Block (MacroBlock)•• I/O CellI/O Cell•• MacroCellMacroCell•• Timing ModelTiming Model
Exam Review OutlineExam Review Outline
HomeworkHomework1. In class we talked about the migration from discrete logic to CPLDs. State three advantages
of using CPLDs over discrete components.
2. Explain the three ways that SRAM cells are used to configure the Xilinx Spartan2e FPGA.
3. Calculate the fall-time for the Driver inverter in the circuit below whose output is routed through the programmable interconnect on an FPGA. Use the values supplied in the table to approximate Rp, Rn, and CL. Use the following definition of fall time: The time from when the input changes from a low to high logic value to the time when the output reaches 0.1Vdd. (Note: ln(0.1) ≈ -2.3, ln(0.9) ≈ -0.1).
Vin VoutDriver Load
‘1’ ‘1’ ValueComponent
22 kΩRp
11 kΩRn
1x10-15 fCL
4. Map the combinational function, F(X2,X1,X0)=X2 XOR X1 XOR X0, to the macroblock given below. Assume an anti-fuse programmable element in the AND-array and denote a grown fuse with an ‘X’. Indicate the configuration memory required such that F is routed as an output to the I/O pin in the figure. Assume an SRAM-based programmable element (shaded boxes) for the MUX control and use the following notation: 1 = logic high, 0 = logic low, and D = don’t care.
X0 X1 X2
D Q
to AND array
1
0
Clock
global OE
F
10
S
s1s0
0100
1110
0
10
S
5. (a) Given the programmable interconnect structure shown below identify the best routing from the output of CLB 1 to the input of CLB 8 to achieve the minimum interconnect delay. Do so by darkening the best route you determined. All of the programmable interconnects shown use the same type of pass transistor. You can assume the resistance in the wire is approximately zero.
(b) What circuit parameters affect the interconnect delay?
6.6. One student in a prior class asked how are the One student in a prior class asked how are the ““System Gate EquivalentsSystem Gate Equivalents”” determined for determined for FPGAs since a configurable logic block uses look up tables not lFPGAs since a configurable logic block uses look up tables not logic gates for computation. ogic gates for computation. Estimate how many Estimate how many ““System Gate EquivalentsSystem Gate Equivalents”” one LUT has given the following data from one LUT has given the following data from the Xilinx Spartanthe Xilinx Spartan--2E Spec. Assume that all of the LUTs in an FPGA count for 10% o2E Spec. Assume that all of the LUTs in an FPGA count for 10% of the f the System Gates.System Gates.
Device System Gate Range Total CLBs Slices/CLB Device System Gate Range Total CLBs Slices/CLB LUT(16x1b)/SliceLUT(16x1b)/SliceXC2S300E 93K XC2S300E 93K –– 300K 1,536 2 300K 1,536 2 22
1 2 3 4 5 6 7 8 9 A B C D E
•• Computer Systems, Processors, and TerminologyComputer Systems, Processors, and Terminology–– Custom HW Custom HW –– ASIC, VLSI, ASIC, VLSI, ……–– Processor vs. MicroprocessorProcessor vs. Microprocessor–– Microcomputer vs. MicrocontrollerMicrocomputer vs. Microcontroller–– Embedded system design processEmbedded system design process
•• RequirementsRequirements•• SpecificationsSpecifications•• ArchitectureArchitecture•• ComponentsComponents•• System IntegrationSystem Integration
–– Embedded SystemEmbedded System•• Characteristics: Complex Algorithms, user interface, realCharacteristics: Complex Algorithms, user interface, real--time, multitime, multi--raterate•• Costs: Cost of goods, mfg cost, development costCosts: Cost of goods, mfg cost, development cost•• Challenges Challenges
–– Hardware performance vs. CostHardware performance vs. Cost–– Code Space/ Code DensityCode Space/ Code Density–– Need to meet realNeed to meet real--time demandstime demands–– Minimize power consumptionMinimize power consumption–– Design for upgradeDesign for upgrade--abilityability–– VerificationVerification–– ReliabilityReliability
Exam Review Outline Exam Review Outline –– lecture 4lecture 4
•• Embedded Systems ContinuedEmbedded Systems Continued–– Computer System Block DiagramComputer System Block Diagram–– System on Chip System on Chip ––SoCSoC
•• Processor in ASIC or FPGA with Softcore processorProcessor in ASIC or FPGA with Softcore processor–– Programmers model Programmers model –– Registers, Condition Codes and Instruction Set Registers, Condition Codes and Instruction Set
ArchitectureArchitecture–– Why is it important to know ISA?Why is it important to know ISA?–– Computer ClassificationComputer Classification
•• ArchitectureArchitecture–– Von Neuman / Princeton ArchitectureVon Neuman / Princeton Architecture–– Harvard ArchitectureHarvard Architecture–– DSPDSP’’s s
•• RISC vs. CISCRISC vs. CISC
•• EDK computer systemEDK computer system–– MicroBlaze ProcessorMicroBlaze Processor–– Busses (Busses (ILMB, DLMB, IOPB and DOPB)ILMB, DLMB, IOPB and DOPB)–– MicroBlaze Memory SystemMicroBlaze Memory System
•• Memory Controllers and BRAMMemory Controllers and BRAM–– Memory Mapped I/OMemory Mapped I/O–– IP CoresIP Cores–– GPIO Programming Input and Output DevicesGPIO Programming Input and Output Devices
Exam Review OutlineExam Review Outline
•• Base Address Base Address •• Memory Mapped Registers (Data Register and Data Direction RegistMemory Mapped Registers (Data Register and Data Direction Register)er)•• I/O InstructionsI/O Instructions
–– Software functions to read and write MicroBlaze memory locationsSoftware functions to read and write MicroBlaze memory locations•• Xio_In32( ); and Xio_Out32( );Xio_In32( ); and Xio_Out32( );•• DIO5 I/O Controller (principles only)DIO5 I/O Controller (principles only)
–– Bus Based Interface Between FPGA and I/O ControllerBus Based Interface Between FPGA and I/O Controller–– Computer SystemComputer System–– Bus Write CycleBus Write Cycle
Timing DiagramTiming DiagramAlgorithm to implement using GPIO and MicroBlazeAlgorithm to implement using GPIO and MicroBlaze
–– DIO5 Memory Map of I/O DevicesDIO5 Memory Map of I/O Devices–– LCD initialization RoutineLCD initialization Routine–– LCD Display CharactersLCD Display Characters
–– Nexys interface to LCD and peripherals (buttons and Nexys interface to LCD and peripherals (buttons and ledsleds))
Exam Review OutlineExam Review Outline
HomeworkHomework1. Microcontrollers are often a hybrid of RISC and CISC architectures. List the characteristics
discussed in lecture for each below?
2. At the hardware level how would the MicroBlaze CPU set an 8-bit GPIO peripheral to be an input? Describe what happens at the hardware level between the CPU and the GPIO peripheral and NOT the device driver function call.
3. Describe the uses of and differences between the OPB and the LMB busses?
4. The Spartan IIe that we are using in the lab has 8k words of BRAM memory. The BRAM is dual ported and has an address space of 0x0000 - 0x1fff. If the Instruction Memory Controller base address is set to 0x0000 and the base address for the Data Memory Controller is set to 0x1000 determine:
a. What physical address would be read if the MicroBlaze fetched an instruction from address 0x0100?
b. What physical address would be read if MicroBlaze fetched a data operand with data address of 0x1200?
HomeworkHomework6. The following code is similar to the code in the blinker tutorial and shows how to set the
lower 8 LEDs on the DIO5 board. Show how the code should be changed to read the lower 8 pushbuttons and store the result into the pb variable.
Xuint32 XGpio_DiscreteRead (XGpio *InstancePtr, unsigned Channel)Read state of discretes for the specified GPIO channnel.Parameters: InstancePtr is a pointer to an XGpio instance. Channel contains the channel of the GPIO (1 or 2).Returns: Current copy of the discretes register.
#define BtnLowAddr 0x00#define BtnHighAddr 0x01#define LedLowAddr 0x00#define LedHighAddr 0x01
main() XGpio led_gpio, data_gpio, addr_gpio, cs_gpio, oe_gpio, we_gpio;unsigned pb;
XGpio_Initialize(&data_gpio, XPAR_DIO_DATA_DEVICE_ID);XGpio_Initialize(&addr_gpio, XPAR_DIO_ADDR_DEVICE_ID);XGpio_Initialize(&cs_gpio, XPAR_CS_N_DEVICE_ID);XGpio_Initialize(&oe_gpio, XPAR_OE_N_DEVICE_ID);XGpio_Initialize(&we_gpio, XPAR_WE_N_DEVICE_ID);
XGpio_SetDataDirection(&addr_gpio, 1, 0);XGpio_SetDataDirection(&cs_gpio, 1, 0);XGpio_SetDataDirection(&oe_gpio, 1, 0);XGpio_SetDataDirection(&we_gpio, 1, 0);XGpio_SetDataDirection(&data_gpio, 1, 0);
XGpio_DiscreteWrite(&oe_gpio, 1,1);XGpio_DiscreteWrite(&cs_gpio, 1,0);XGpio_DiscreteWrite(&we_gpio, 1,0);XGpio_DiscreteWrite(&addr_gpio, 1,LedLowAddr);XGpio_DiscreteWrite(&data_gpio, 1,0xAA);XGpio_DiscreteWrite(&we_gpio, 1,1)XGpio_DiscreteWrite(&cs_gpio, 1,1);
HomeworkHomework7. What type of applications would benefit from a processor with a Harvard architecture?
Explain how the application benefits from a processor with a Harvard architecture.8. Describe the uses of and differences between the OPB and the LMB busses?9. Draw a timing diagram that shows a read of the lower 8 pushbuttons through the DIO5 I/O
Controller. Include all of the logic signals that connect to the DIO5 Board. You can assume that the pushbutton 4 is pushed and the rest of the pushbuttons are not pressed.
10. What is the difference between a Harvard and Von Neumann/Princeton architecture? What type of architecture does the MicroBlaze use?
11. MicroBlaze Memory System: Draw the architecture of the MicroBlaze memory system used in Experiments 2 and 3. Provide values for base address registers where applicable.
12.12. I/O Controller Bus Cycles: In Experiments 2 and 3 you configureI/O Controller Bus Cycles: In Experiments 2 and 3 you configured the MicroBlaze system d the MicroBlaze system with five GPIOs for the data bus, the address bus, and three conwith five GPIOs for the data bus, the address bus, and three control signals to communicate trol signals to communicate with the I/O Controller programmed in the CoolRunner CPLD on thewith the I/O Controller programmed in the CoolRunner CPLD on the DIO5 board. Write a C DIO5 board. Write a C function turn_on_leds() that will turn on all 16 LEDs on the DIOfunction turn_on_leds() that will turn on all 16 LEDs on the DIO5 board using this same 5 board using this same MicroBlaze system. The header file for the xparameters.h and thMicroBlaze system. The header file for the xparameters.h and the DIO5 Default Circuit e DIO5 Default Circuit Memory Map are provided on the next page.Memory Map are provided on the next page.
13.13. In Experiments 2 and 3 you configured the MicroBlaze system withIn Experiments 2 and 3 you configured the MicroBlaze system with five GPIOs for the data five GPIOs for the data bus, the address bus, and three control signals to communicate wbus, the address bus, and three control signals to communicate with the I/O Controller ith the I/O Controller programmed in the CoolRunner CPLD on the DIO5 board. Write a C programmed in the CoolRunner CPLD on the DIO5 board. Write a C function function display_message() that will write display_message() that will write ““CPE 329!CPE 329!”” to the LCD screen. on the DIO5 board using this to the LCD screen. on the DIO5 board using this same MicroBlaze system. You may call the function configure_LCDsame MicroBlaze system. You may call the function configure_LCD() to initialize the LCD () to initialize the LCD screen and configure it for entry mode. You can use the header screen and configure it for entry mode. You can use the header file file xparameters.hxparameters.hprovided for lab 2 and 3.provided for lab 2 and 3.
14. You need to select either a PowerPC (RISC) or Motorola 68000 (CISC) microcontroller for a particular design application. Both have adequate performance and comparable cost. The application will require external memory so minimizing the code space is critical. Which microcontroller will you select? Explain why you selected the microcontroller that you did.
HomeworkHomework15. Ace engineer proposes writing a high performance OPB bus. Ace’s goal is to create an OPB
bus equivalent with all of the same functionality as currently is available but allow single cycle bus transactions. Are these goals feasible? If so, describe one way the OPB bus performance can be improved.
16. If our development board was running at 100MHz and the Xio_Write32() and Xio_In32() functions calls only take one clock cycle to execute, then would we need to make any changes in our bus read cycle code? Refer to the information in the DIO5 reference manual?
17. You are asked to add a second DIO5 board to the lab setup so that you have two LCD displays to output messages. Now you are required to write “Hello World!” onto one screen as before, and write “CPE 329 Rules!” on the other LCD Screen. Your design requirements include using the fewest number of Slices and Code space as before.
a. Draw the system architecture for the new system. Be sure to include the number of bits for each GPIO device.
b. Describe how the code would have to change to accommodate the new hardware system and requirements as compared to the default computer system in the tutorial. Your answer can be in bullet format but you must use sufficient detail to carefully describe the software algorithms.
18.18. Given the MicroBlaze memory map used in the blinker tutorial forGiven the MicroBlaze memory map used in the blinker tutorial for the computer system write the computer system write the minimum amount of the minimum amount of ““CC”” code to only light the lower four LEDs on the DIO5 board. Do code to only light the lower four LEDs on the DIO5 board. Do not use any pound defined words in your code (use hex numbers fonot use any pound defined words in your code (use hex numbers for function parameters) or r function parameters) or assume any initialization has been done. assume any initialization has been done.
•• Embedded Developers Kit Design FlowEmbedded Developers Kit Design Flow–– Hardware SystemHardware System
•• Add CoresAdd Cores•• Bus ConnectionBus Connection•• Memory MapMemory Map•• Port ConnectionsPort Connections•• ParametersParameters•• User ConstraintsUser Constraints
–– Software SystemSoftware System•• Device Driver Interface (Xio_Out, Xio_In, Device Driver Interface (Xio_Out, Xio_In, ……))•• Main Code using Main Code using ““CC””•• CompileCompile•• Generate BitstreamGenerate Bitstream•• Update BitstreamUpdate Bitstream•• Download codeDownload code
–– EDK Nexys TutorialEDK Nexys Tutorial
Exam Review Outline Exam Review Outline –– lecture 5lecture 5
2121
HomeworkHomework1.1. When using the EDK explain what happens when you execute When using the EDK explain what happens when you execute
the following commands?the following commands?a.a. Generate Netlist?Generate Netlist?b.b. Generate Libraries? Generate Libraries? c.c. Update BitStream? Update BitStream?
2.2. Describe what happens in the mapping stage of the Hardware Describe what happens in the mapping stage of the Hardware design flow? Describe what the input is for the mapping processdesign flow? Describe what the input is for the mapping processand what is generated by the mapping process.and what is generated by the mapping process.
3.3. You are asked to implement an algorithm using the tools You are asked to implement an algorithm using the tools available to you in the CPE 329 lab. The application requires tavailable to you in the CPE 329 lab. The application requires the he highesthighest--performance design that you can download into the performance design that you can download into the Digilent D2FT board. You notice that the algorithm is Digilent D2FT board. You notice that the algorithm is computationally intense but does not have a significant amount computationally intense but does not have a significant amount of inherent parallelism. Describe which approach and design tooof inherent parallelism. Describe which approach and design tool l you would select. Also, explain why you chose this approach.you would select. Also, explain why you chose this approach.
Exam Review Outline Exam Review Outline –– lecture 6lecture 6•• MicroBlazeMicroBlaze
–– Programmers ModelProgrammers Model–– Data TypesData Types–– Instruction SetInstruction Set–– Program Counter and Machine State RegisterProgram Counter and Machine State Register–– General Purpose RegistersGeneral Purpose Registers–– Instruction formatsInstruction formats
•• Big Endian / Little EndianBig Endian / Little Endian•• PipeliningPipelining
–– Overlapped executionOverlapped execution–– Performance (Latency, throughput, IPC, and CPI)Performance (Latency, throughput, IPC, and CPI)–– MicroBlaze Pipeline (FMicroBlaze Pipeline (F-->D>D-->Execute)>Execute)–– Data Dependency HazardsData Dependency Hazards–– Control HazardsControl Hazards–– Delayed BranchesDelayed Branches
Exam Review Outline Exam Review Outline –– lecture 7lecture 7InterruptsInterrupts•• Asynchronous event that allows device to interrupt CPU and transAsynchronous event that allows device to interrupt CPU and transfer control over to an interrupt fer control over to an interrupt
service routine.service routine.•• Foreground task (main loop)Foreground task (main loop)•• Interrupt Service Routing (ISR) or Interrupt Handler Interrupt Service Routing (ISR) or Interrupt Handler •• Interrupt and AcknowledgeInterrupt and Acknowledge•• Hardware interface for interruptHardware interface for interrupt•• Interrupt process at HW level Interrupt process at HW level
•• CPU Initializes and enables interrupt device and unmasks interruCPU Initializes and enables interrupt device and unmasks interruptspts•• External Interrupt request generatedExternal Interrupt request generated
–– Possibly on chip peripheral devicePossibly on chip peripheral device–– Possibly external devicePossibly external device
•• CPU typically finishes current instructionCPU typically finishes current instruction–– Some instructions are interruptible Some instructions are interruptible
•• Some CPUSome CPU’’s perform HW context save (if not context save is responsibilitys perform HW context save (if not context save is responsibility of ISR)of ISR)•• CPUCPU’’s typically disable interrupts automatically s typically disable interrupts automatically •• Return address stored (on stack or in dedicated register)Return address stored (on stack or in dedicated register)•• Branch to interrupt service routine: Fetch Interrupt Vector (addBranch to interrupt service routine: Fetch Interrupt Vector (address of interrupt service routine) or address of instruction ress of interrupt service routine) or address of instruction
in Jump table and put this address into the PCin Jump table and put this address into the PC•• Execute the interrupt service routineExecute the interrupt service routine•• ISR must clear interrupt flag (acknowledge interrupt)ISR must clear interrupt flag (acknowledge interrupt)•• Restore Context if not handled in HWRestore Context if not handled in HW•• RTI RTI -- Return from interrupt instruction :Restores CPU context includiReturn from interrupt instruction :Restores CPU context including condition codes and Branches to return addressng condition codes and Branches to return address
•• Debugging with interruptsDebugging with interrupts•• Multiple Interrupts and Interrupt Priorities Multiple Interrupts and Interrupt Priorities •• Maskable vs. NonMaskable vs. Non--Maskable interruptsMaskable interrupts•• Handling multiple interrupts using an OR gateHandling multiple interrupts using an OR gate•• Interrupt controllers and multiple interrupt devicesInterrupt controllers and multiple interrupt devices•• Interrupt overheadInterrupt overhead•• Comparison of Interrupts to Polling algorithmsComparison of Interrupts to Polling algorithms
HomeworkHomework1. Determine the number of cycles from the time the first SUB instruction is fetched until the
last BNE instruction completes execution and the CPI for the following MicroBlaze assembly code if the BNE branch is taken 1 times? Assume the SUB instruction execution stage takes 1 cycle to execute and the BNE takes the number of cycles described in lecture.
Loop: SUB r3, r3, 1SUB r1, r1, 4SUB r2, r2, 8BNEI r3, loop_offset
2. The semantics for the MicroBlaze Instruction BEQ and BEQD are both the same if Ra=0: PC:=PC + Rb. What is the difference between the two branch instructions? When would BEQD be used and why would it? Be specific.
3. List three specific items that contribute to interrupt overhead.
4. Explain why the EDK has an Interrupt Controller IP Core? Be certain to discuss the advantages that the Interrupt Controller IP Core would have compared to the simple “OR”gate approach discussed in lecture.
5. Determine the state of the carry bit and the Registers R1, R2, and R3 after the following MicroBlaze assembly instruction is executed if R1 = 0x0f000000, R2 = 0xff000000, R3 = 0x8f000000 and C=0 before the instruction is executed. Also show the RTL description of the instruction.
ADDKC R1, R2, R3
