CMOS ICs are being producedusing a variety ofprocesses,and considerable data is nowavailable on their reliabilityand failure mechanisms.
Reliability of CMOSIntegrated Circuits
There are basic differences between MOS andbipolar digital integrated circuits, and betweenCMOS and other digital MOS technologies. Some ofthose differences have an impact on the reliability ofthe various types of digital integrated circuits.Accelerated-life tests and field use, along with otheravailable data on CMOS reliability, indicate thatCMOS devices, properly made, are equal in reliabili-ty to bipolar digital circuits of equal complexity. Inthis article, we look at CMOS packaging, circuitcomplexity, and electrostatic gate protection andcompare CMOS to other types of digital ICtechnology.
CMOS IC Technology
The basic building block for CMOS integratedcircuitry1-4 is shown in Figure 1. In contrast to othertypes of MOS integrated circuits, the CMOS cir-cuits contain no load resistors; this results in verylow quiescent dissipation. The voltage transfercharacteristics of a basic CMOS inverter are shownin Figure 2, and typical curves of dynamic dissipa-tion versus frequency in Figure 3.CMOS ICs were originally produced in volume in
1968. The technology has evolved from that used forthe original RCA CD4000 series' devices (6-15 volts)to the CD4000A series (3-15 volt) devices2 in 1971,and to the 4000B series (3-20 volt) devices 3,6 in1974. The introduction, in 1970, of plastic-encapsulated devices5 was instrumental in achiev-ing even wider acceptance of the popular 4000series.CMOS ICs are being produced by a number of
manufacturers using a variety of different pro-cesses.2'2w5-'9 Ion implantation is being used to formp-wells, 3,20 to adjust thresholds,6 and to avoid fieldinversion. Metallization materials have includedaluminum, polycrystalline silicon, and titanium-palladium-gold or titanium-platinum-gold.52'2 Tech-
niques for attaching the die to the substrate have in-cluded gold-silicon eutectic bonding and epoxy at-tachment.' Although most CMOS ICs beingmanufactured today are bulk silicon types, devicesfab'ricated on thin-film silicon-on-sapphiresubstrates are being produced.3'7"1'9-1419At present, 4000A series CMOS ICs are commer-
cially available from more than 10 suppliers, andstandardized 4000B series devices22 are or will beavailable from at least nine. Devices qualified toMIL M-38510, Class A are also commerciallyavailable.4The packages used for CMOS devices are similar
to those used for other types of MOS devices and forbipolar devices. The same potential failuremechanisms apply to chip-to-substrate bonds, wirebonds, and packages.2 All MOS devices are,however, more surface-sensitive than digital bipolardevices, and higher voltages are applied to MOSdevices than to digital bipolar devices.
MOS vs. bipolar ICs
MOS ICs have had a major impact on the digitalelectronics industry. Not only have they displacedbipolar ICs for many applications, but they havealso made possible a large number of totally new ap-plications. As a result, they are now being producedin volumes roughly comparable to those of bipolardevices. Because bipolar devices antedate MOSdevices, more information has been published on thereliability of bipolar circuits than on the reliabilityof MOS circuits. Also, bipolar circuits were initiallyused to a large extent in high-reliability military andaerospace applications, whereas'MOS circuits havebeen used principally in consumer and commercialapplications. Also, while most early MOS deviceswere hermetically packaged, a large portion of allMOS ICs produced today are encapsulated inplastic.1,13
6 0018-9162/78/1000-0006$00.75 O 1978 IEEE COMPUTER
INPUT Q-
+ VDD
SUBSTRATE
GATES G 0 OUTPUT
l_n
p - WELL
-vss
Figure 1. The basic building block for CMOS integratedcircuits. Figure 2. Voltage
CMOS inverter.transfer characteristics of a basic
The first commercially available MOS deviceswere based on p-channel enhancement-mode MOStransistors with aluminum gates. Accordingly, con-siderable information is available on the reliabilityof this type of device, and on possible failuremechanisms.ss-27 Devices that have since becomecommercially available include CMOS, silicon-gate,n-channel, depletion-mode, floating-gate, CCD, andCMOS/SOS devices. Considerable data is nowavailable on the reliability and possible failuremechanisms of CMOS devices, on ICs con-taining silicon-gate transistors,51-" and on devicesbased on n-channel transistors.55-"A number of fundamental differences between
MOS and bipolar devices have an impact onreliability. The principal differences are that MOSICs have a higher substrate resistivity and usehigher applied voltages, and the properties of thegate oxide of MOS devices are more important.The process of MOS fabrication is simpler than
bipolar fabrication.5,23 Accordingly, it is easier to at-tain higher chip complexity with MOS, and thushigher gate-to-pin ratios. Since wire-bond failuresare a significant factor in limiting the reliability ofsmall-scale ICs, MOS can significantly improvereliability by reducing the number of wire bonds andexternal interconnections. Moreover, with MOStechnology, there is lower power dissipation perfunction, which improves reliability by loweringchip temperatures. In typical bipolar ICs (TTL),device dissipation is significant.MOS, particularly CMOS, also has an advantage
over bipolar devices in that the high impedance ofMOS devices does not result in high current den-sities in the metal interconnections, and thus elec-tromigration (current-induced mass transport) isnot a common problem in MOS devices. Problems ofhigh current density at metal-silicon contacts arealso less frequent. The high impedance of MOSdevices also makes multilevel interconnectionsfeasible in complex arrays without significantly
October 1978
compromising circuit properties. Diffusedcrossunders in the single-crystal silicon are effec-tive, and if another level of interconnections is re-quired in addition to that provided by the metalliza-tion layer, polycrystalline silicon, deposited as partof the silicon-gate process, is quite effective as an in-terconnection level. By contrast, an additional levelof interconnections. in bipolar arrays means use ofmetal-over-metal 'crossovers, which requires addi-tional technology and introduces possible newfailure mechanisms.Since localized defects in silicon are a factor in IC
reliability, one advantage of MOS compared tobipolar circuits is that no epitaxial layer is requiredfor conventional monolithic MOS devices. MOSdevices are thus fabricated in silicon of better
AMBIENT TEMPERATURE (TA) - 250CPOWER DISSIPATION P = CVDD2f + PQUIESCENT
10 103 104 105 106 107INPUT FREQUENCY (fl) - Hz
Figure 3. Typical relationship between dynamic dissipation of CMOSintegrated circuits and frequency.
7
VDD
VOUT
VIN
crystallographic perfection, with no possibility ofepitaxial stacking faults or of epitaxial spikes thatcause device problems and damage the masks usedfor photolithography. Finally, since MOS process-ing is simpler than bipolar processing and requiresfewer steps, fewer manufacturing errors are possi-ble.
Failure rates for devices of various complexitiesare often lumped together and reported as a failurerate for a particular device family. Since MOSdevices tend to be more complex than bipolardevices, equal reported failure rates per packagedpart actually represent lower failure rates per gate.MOS ICs use many of the same materials and pro-
cesses that bipolar ICs and small-signal transistorsdo. Accordingly, improvements in siliconmaterials,'9 oxidation,65-69 photolithography,50'70-7'diffusion,20'72 metallization,7' passivation,78'" andplastic encapsulation,"23"3'97-79 and also in devicephysics, design, process control,'8 automation,80 andelectrical characterization have resulted in substan-tial improvements in the reliability of both types ofdevices.
Reliability advantages of CMOS
CMOS technology provides a number of relia-bility advantages over other MOS tech-nologies, 34,7-9,14,21,28 For example, since both p-typeand n-type diffusions are part of the normal process,both are available to use as channel stoppers or aspart of a more effective input protection circuit. Thelow dissipation of CMOS ICs results in lower chiptemperatures, which substantially improve reliabili-ty. The wide range of CMOS operating voltages per-mits greater reliability of operation, including allow-ing functional testing at voltages substantially_above and below the ultimate operating voltage.Moreover, because of low dissipation per gate,CMOS can be used to fabricate very complex chipswithout introducing reliability problems resultingfrom excessively high chip temperatures."'0"4 Bycontrast, power dissipation in large chips is a pro-blem with TTL integrated circuits and, to some ex-tent, PMOS and NMOS circuits. Finally, CMOStechnology represents a mature, high-volumetechnology with an extensive history of reliability.Potential failure mechanisms are well understood,and production processes and process controls havebeen specifically selected to ensure against thepossibility of manufacturing errors that mightadversely affect reliability.Other factors of importance to the reliability of
CMOS ICs include device and design features>(dielectric thickness and quality, design rules,device complexity, in-process controls), specifica-tions (maximum and minimum operating voltages,operating temperature range), electrical testing(tests performed on the wafer and on packageddevices), and screening (amount of burn-in or otherscreens applied). Operating conditions of impor-,tance include chip temperature, applied voltage,
voltage transients, moisture content of the ambient,and exact circuit usage.5
CMOS packaging
CMOS ICs are available in all of the commonpackage configurations. The conventionalhermetically sealed ceramic package containing acavity filled with dry gas is generally used for high-reliability military and aerospace applications. Thefrit or Cerdip package, with the final seal made byfusion of a devitrifying solder glass, is the least ex-pensive hermetic package for high-volume commer-cial application. Beam-lead sealed-junction devicesmay also be considered hermetically sealed devicesin that the silicon nitride provides junctionhermeticity. The use of a gold-based metallizationsystem and an overlying amorphous inorganicpassivation layer provides additional protectionagainst possible deleterious reactions over the life ofthe device.Most ICs being manufactured in 1978, including
CMOS as well as other MOS and bipolar types, areencapsulated in plastic rather than in hermeticpackages. Plastic encapsulation provides a numberof significant advantages, including lower productcost, freedom from potential problems with looseparticles (in molded devices), mechanically strongdual-in-line packages, good resistance to- shock andvibration, no leak-test requirement, and possibilityof small packages.A number of possible limitations of plastic-
encapsulated integrated circuits were identified",2"28in studies of early plastic encapsulation systems ap-plied to both bipolar and MOS ICs. These includedmoisture penetration effects, effects due to mis-matches between the coefficients of linear thermalexpansion of plastics and those of silicon and thevarious interconnect metals, and the presence ofionic materials and other contaminants in certainplastics.The knowledge of potential limitations of certain
plastics has led to the use, in recent years, of vastlyimproved materials and processes for fabricatingplastic-encapsulated devices.5,2",36"37'41,48,76 An exam-ple is the use of high-purity novolac epoxy plasticswith high glass transition temperatures.23'7'Modifications in assembly techniques have alsobeen made. As a result of these changes, plastic-encapsulated devices manufactured in the 1976 to1978 period have been significantly more reliablethan devices fabricated a number of years ago.Humidity levels above 85 percent can greatly ac-
celerate 'possible failure mechanisms in plastic-encapsulated silicon devices."523,""i7'41,48.76'78 Conse-quently, high-humidity tests, particularly underbias conditions, have been used to quantitativelyassess the integrity of IC passivation and encap-sulation systems, and have been the basis for pro-cess improvements as well as quality control tests.The effect of high humidity in accelerating failuremechanisms has been the basis for a number ofdetailed studies."37'48,64
COMPUTER8
CMOS failure modes and mechanisms
MOS failure modes can be classified into thecategories of shorts, opens, and degradations.Shorts are most commonly due to dielectric failureof the gate (thin) oxide. Dendrite formation in gold-metallized devices can ilso result in resistive shorts.Electrical opens may be due to microscopic cracks inthe metallization at topographic steps-, to photo-lithography problems, to corrosion of metallization,to fusion of metal due to overstress, or to open wirebonds. Degradation effects are attributable to themotion of ions (such as Na+) in the silicon dioxide,or to surface-charge-spreading effects and conse-quent inversion.Considerable information is available on the
distribution of failure mechanisms in CMOS devicesthat failed during accelerated-life stress tests orfield use. The principal failure mechanisms inCMOS are due to parameter changes caused by mo-tion of charge in or on oxides, and to shorts throughgate oxides. (The relative distribution of CD4000ACMOS field failure mechanisms6 is shown in Table1.) These failure mechanisms are similar to the prin-cipal failure mechanisms of otherMOS device types.There is,- however, a considerable variance in thedistribution of mechanisms: depending on thesource issuing the informatioii The -reports of users,who include electronic equipment manufacturers aswell as government agencies and industrial organ-izations performing government-funded reliabilitystudies, tend to indicate that there are large, varia-tions between products from different suppliers.
Several forms of alkali ion migration are possible,including the commonly reported transverse Na+ion movement in an electric field at an elevatedtemperature, and lateral Na+ ion movement fol-lowed by transverse movement. The net result ofalkali ion migration is to increase the thresholdvoltage of p-channel transistors, to decrease thethreshold of n-channel transistors, or to decrease thefield inversion voltage'of n-type regions. BecauseMOS structures have proven an excellent tool forthe study of silicon-silicon dioxide interface proper-ties, a vast amount of information has beenavailable to- apply to the improvement of the pro-cess, as well as to the design and control of devicefabrication.8'Aluminum metal corrosion in integrated circuits
has been the subject of considerable study in recentyears."'9,23,48,'-89 It has been shown that low-
Table 1.DIstrIbutIon of mechanisms that normally
occur In field failures.
FAILUREMECHANISM PERCENT
FALSE PULLS 35GATE OXIDE SHORTS (HANDLING) 25BLOWN METAL (OVERCURRENT STRESS) 20QUALITY RELATED (SCRATCHED METAL, BONDING,WRONG PELLET-OR PACKAGE). 15
MOISTURE (PLASTIC USED IN WRONG APPLICATION) 5
temperature-deposited glass-like inorganic passiva-tion materials can be very effective in reducing thepossibility of aluminum corrosion. Specific factorsthat can result in chemical corrosion of aluminumand electrochemical corrosion at cathode and anoderegions have been identified.
Failures in plastic-encapsulated devices are fre-
quently attributable to penetration of moisture orother iohic impurities along the chip-plastic inter-face. Figure 4 shows a cross-section of a typicaldual-in-line plastic package. The two paths by whichwater vapor can enter such packages are throughthe plastic and along the leads.' Pl:astic devices rare-ly fail in normal field use unless the wrong packageis selected for the system environment.'Gate oxide breikdown may be due to localized
breakdown at defects or to intrinsic breakdown ofthin oxides at input circuits. Breakdown at inputs is
principally attributable to overstress from staticelectricity discharges, particularly when the devicesare mishandled. While virtually all MOS ICs con-tain an input protection circuit, such circoits vary
considerably in design, principle of operation, andeffectiveness.",990-96 The susceptibility of silicondevices to static electricity effects is not unique toMOS circuits; it has also been reported to occur withbipolar integrated circuits"""'97-" and with otherelectronic components. Improved input protectioncircuits in CMOS integrated circuits have beenshown to provide additional protection againststatic electricity discharges.446',8 " Figure 5 showsthe improved input protection network" being usedon all new CD4000B devices.Some information has been published on the
reliability of silicon-on-sapphire CMOS ICs, and on
possible failure mechanisms for that type of con-struction.88'89'42 While new failure mechanisms are
possible with CMOS/SOS, the principal failuremechanisms are frequently similar to those ob-served with bulk CMOS devices.
Data on CMOS Reliability
Various sources of data on the reliability of CMOS-
-integrated circuits exist, including data generatedby device manufact-urers,"4"59,8,283,29,0,"6,"7,89,4041,48 byusers, and by government agencies and
TRANSFER MOLDING1/4" e MATERIAL
NOVOLAC EPOXY
GOLD 1.0 MIL WlREST.C. BONDED
STEEL
LEAD FRAME
DEPRESSED EPOXY SPOT GOLD FRAME
MOUNT PAD DIE ATTACH SOLDER COATED
Figure 4. Cross-sectlonal:vlew of a typical dual-In-lIneplastic-encapsulated Integrated circult.
October 1978 9
VDD
IN
*INTRINSIC DIODES
Figure 5. Improved input protectionCD4000B Integrated circuits.
network for new
contractors."""""""'""2 Specific types of CMOSdevices that have been evaluated include standardA-series,products in hermetically sealed ceramicpackages,4'""80 B-series devices,"5""""'" beamleadsealed-junction devices,9 CMOS/SOS devices,'339"2and others.
s~CCResults of accelerated-life stress tests. A con-
siderable amount of data has been generated duringqualification and conformance testing of CD4000Aseries CMOS devices for MIL-M-38510, Class A.These data indicate excellent package integrity lonefailure in a total of 729 devices tested to Group Bqualification tests) and excellent stability4"9"45 (onlyone failure in a total of 1504 devices tested to GroupC qualification tests). Conformance test data onmore than 2.3 million device-hours of accelerated-lifestress testing at 125 OC on a wide variety of circuits,from gates to MSI devices, show only five degrada-tional failures and three inoperable failures, whichcorresponds to a functional failure rate at 125 IC of0.14 percent per 1000 hours, at a 60-percent con-fidence level.9Much of the available data on CMOS reliability
has been generated by accelerated-operating-lifestress tests. A typical figure for reliability ofhermetically sealed CMOS devices (ceramicpackages) is on the order of 0.1 percent per 1000hours at a 60-percent confidence level) for devicesoperated at 1250C with VDD of 10 volts. This isbased on more than 9 million device-hours of
Table 2.Effect of activation energieson extrapolated failure rates.
ACTIVATION FAILURE RATE (%/1000 hours)ENERGY VERSUS TEMPERATURE
1250C 550C 250C
0.3 eV 0.1 0.02 0.0051.3 eV 0.1 0.00004 0.0000005
operating-life tests of devices from five manufac-turers.9
Reliability effects of operating temperature. Sincethe thermal activation energy for failure of MOSdevices by the more prevalent failure mechanisms,such as alkali ion migration in the thermally growngate oxide in an electric field, -is relatively high, theoverall thermal activation energy for failure ofMOSICs, including CMOS devices, tends to be high.Reported thermal activation energies for CMOS ICfailure rates range from 0.3 eV to 1.3 eV; In somecases, a low acceleration factor is used to ex-trapolate results of accelerated tests, and it ispointed out that the actual acceleration factor isbelieved to be higher. Where experimental data ispresented to support an activation energy, the valuearrived at is frequently on the order of 1 eV.The implications of these various activation
energies are apparent in Table 2, which shows the ef-fect6 of extrapolating the extremes reported in ac-tivation energies, 0.3 eV and 1.3 eV. Both have beentaken as 0.1 percent per 1000 hours at 125 IC.
Reliability effects of operating voltage. A numberof manufacturers have shown increases in failurerates of CMOS products as a result of increasingoperating voltage under accelerated stress condi-tions in operating-life tests.""9,23'29"36'37"41 Possible ef-fects of higher operating voltage, on MOS ICs in-clude increased chip temperature, accelerated mo-tion of alkali ions, increased susceptibility tosurface-charge spreading and to field inversion, and'increased incidence of oxide breakdown. Oxidebreakdown in MOS structures has been studied by anumber of investigators, and has been consideredby some to follow Peek's law in that the time tofailure is inversely related to the fourth power of theapplied voltage.23The effect of operating voltage on relative failure
rate of CD4000A series and CD4000B series devicesis shown in Table 3. The higher reliability of B seriesdevices at higher voltages is attributed to the abili-ty to electrically test devices at higher voltages, andto operation at a smaller percentage of actual devicebreakdown voltage.3 Functional and DC parametertesting on CD4000B series parts is performed atRCA at 2.8 volts and at 22 volts, whereas CD4000Aseries devices are tested at 2.8 volts and at 17 volts.
Failure rates of plastic-encapsulated CMOS ICs.Some data is available on comparative reliability of
Table 3.Relative failure rates at 1250C at
virious applied voltages.
APPLIED CD4000 CD4000VOLTAGE A SERIES B SERIES
5 1 -
10 3 1
15 10 3
20 - 6
COMPUTER10
similar devices in hermetic versus plastic packages.In general, operating-life failure rates are reportedto bq several times higher for devices in plastic asfor those that are hermetically sealed. It is generallynot possible, hoWever, to take the available data andmake specific quantitative conclusions about the ef-fect of plastic encapsulation on the reliability of agiven type of MOS IC. One reason why this cannotbe done, even though the same wafer processing isapplied to both plastic-encapsulated and hermetical-ly sealed devices, is that there are many differencesin the assembly and test sequences other than thepackaging. For example, devices intended for high-reliability applications may be subjected to morestringent visual inspection criteria, may be assem-bled under very closely controlled conditions withconsiderable documentation, may be electricallytested under wide ranges of conditions (such astemperature ranges between -55 OC and 125 0C),and may be subjected to various screens, electricaltests, burn-ins, and lot-acceptance criteria. Obvious-ly, such techniques, while more costly, are effectivein eliminating a certain number of potentially lessreliable (freak) devices from the main population.The failure rate of plastic-encapsulated MOS
devices can be considered to be the sum of thespecific failure rates of the total system, includingfailure mechanisms occurring on the chip, in the in-terconnection system external to the chip, and inthe package. While unsuitable plastics can adverse-ly affect the reliability of susceptible chips, plasticencapsulation cannot provide a chip reliability in ex-cess of that which would be encountered in a dry, in-ert ambient. Accordingly, the reliability of manyplastic-encapsulated devices, particularly underlower humidity conditions, is limited by the reliabili-ty of the encapsulated chip, rather than by anyreliability limitations imposed by the plastic. Afailure rate on the order of 0.1 percent per 1000hours at 850C, at the 60 percent upper confidencelevel, can be expected for high-quality plastic-encapsulated commercial-type MOS ICs preparedby a mature, well-controlled process.23Figure 6 shows the failtre rate of plastic-
encapsulated CMOS devices as a function of am-bient water-vapor pressure, and indicates the degreeof improvement in packaging attained in recentyears.5
Reliability effects of device complexity. Anumber of authors have dealt with the effect of chipcomplexity on failure rate. It is now generallyagreed that increasing chip complexity increasesthe failure rate per packaged part, but reduces thefailure rate per gate or per function accomplished.The overall failure rate may be considered as thesum of the failure rates due to wire bonds, to failuresthat would occur with a chip of any size, and to chipfailures at localized defects, which is an area-dependent factor.5'28 The failure rate due to wirebonds is simply the product of the failure rate perwire, such as 0.0001 percent per 1000 hours, timesthe number of wires. The failure rate of chips due to
20.
0 / ,a- __1-I.)
C.)
1
0.5__ _
2 4 6 8 2100 1,000
AGE AT FAILURE-HOURS
Figure 6. Weibull plot of results of 85°C185% relativehumidity test on CMOS devices.
localized defects increases with increasing chip areabut is not linearly dependent on the area of the chip;it is considered to increase less rapidly than chipsize, owing to the tendency of localized defects tocluster rather than to occur at random. (The con-siderations here are somewhat similar to those thathave been shown to apply to the effect of chip size orcircuit complexity on IC yield.)100°104 Complex ICsare thus more reliable per gate, and the use of com-plex ICs in electronic equipment to perform thesame functions as a larger number of less complexdevices will in general result in substantially im--proved equipment reliability.
Field failure rates. Failure rates under field-useconditions are much lower than failure rates underaccelerated stress conditions typically used bydevice manufacturers to evaluate reliability. Theprediction of failure rates under field conditions re-quires the use of an acceleration factor to ex-trapolate high-temperature accelerated-stressreliability data. Frequently, the acceleration factorsselected have been excessively conservative, withsome based on very low activation energies thatrepresent early bipolar IC reliability experience. Ingeneral, the Arrhenius equation continues to be con-sidered appropriate for expressing the effect oftemperature on failure rates.Recent data on the reliability of CMOS ICs in
satellites105 includes a total of over 100 milliondevice-hours of operation of CD4000A series devicesat 25-125 OC with no failures, which corresponds to afailure rate of 0.0009 percent per 1000 hours at a 60percent confidence level.104 Field failure rates forplastic-encapsulated CMOS ICs, at operatingtemperature up to 550C, can be considered to be onthe order of 0.001-0.01 percent per 1000 hours at a60 percent confidence level. Obviously, variationswill occur depending upon type, design, process,
October 1978 11
manufacturer, screens applied, voltage, and severityof the ambient conditions.
Radiation hardening. Ionizing radiation is aspecific type of environmental stress that can pro-duce severe degradation in the electrical propertiesof silicon ICs. Early MOS devices were sensitive toionizing radiation, with degradation occuring at alevel as low as 103 rads. Recent studies havegenerated a considerable amount of informationconcerning the effect of the thermally grown oxidepurity, growth conditions, and annealing conditionson susceptibility to radiation damage. As a result ofthese studies, it is now possible to modify the pro-cessing conditions to produce CMOS integrated cir-cuits with considerably improved radiation hard-ness.4,9106-12 CMOS ICs guaranteed (by testing) towithstand 1 X 106 rads became commerciallyavailablels in early 1978.
Reliability effects of processtechnology trends
A number of trends in CMOS fabricationtechnology affect IC reliability. Important recenttrends include increased chip complexity (morefunctional devices per chip), 01-I5,20,801141-122 use ofdevices with smaller geometries,123-128 and increaseduse of automation and of better process-monitoringtechniques.129'31 Wafer processing trends includeuse of improved materials.132'13 improvedphotolithography and etching techniques,134'135 in-creased use of ion implantation, 1.137 improvedmetallization, and more effective passivationlayers.'38-140 Process moodifications have also beendevised to substantially improve the radiation hard-ness of MOS oxides. Advances have also been madein encapsulation techniques, in plastic materials,141and in testing of completed devices.Ion implantation provides a high-purity, very-
closely controlled source of dopant atoms. This, inturn, permits tighter distributions of the electricalcharacteristics of transistors. High chip complexitymakes possible higher gate-to-pin ratios, decreasingthe probability of failure due to wire bonds,packages, or external interconnections of varioustypes, such as. soldered conffections in electronicequipment. Moreover, with chips of high complexi-ty, the failure rate per logic gate tends to be lowerthan that of gates on chips of low complexity. Theseand other advantages, plus immunity to noise, haveresulted in very wide use of CMOS ICs in electronicsystems, with predictions of even wider use in thenext several years.142-147 A number of authors haveindicated that CMOS/SOS is particularly well suitedto fabrication of VLSI circuits.10"4'4The reliability of MOS IC chips is not at present
limited by the inherent properties of silicon, silicondioxide, aluminum, or thin-film polycrystallinesilicon; further improvements being made in chipdesign and processing will continue to increase thereliability of MOS ICs in all types of packages.
The net result ofMOS process changes made in re-cent years has been to lower costs of all types, topermit more complex circuits to be fabricatedeconomically, and to produce products withsubstantially improved reliability, both in plasticand in hermetic packages.
Reliability of CMOS vs. other MOS devices
Data on comparisons of the reliability of CMOSICs with that of other MOS technologies, such-asp-channel or n-channel MOS circuits, or with that ofbipolar ICs such as TTL circuits, indicates thatwhen circuits of equal complexity, prepared bymature, well-controlled processes are compared atthe same operating temperature, there are nosystematic differences among devices incorporatingthe major MOS technologies, between MOS deviceswith aluminum and polycrystalline silicon gates, orbetween MOS and bipolar ICs."99,23,30148149The most reliable integrated circuits are those
specifically designed for high reliability; fabricatedby mature, well-controlled processes; and screenedat all stages to remove freak devices that deviatefrom the main population and are susceptible to ear-ly failure. Even the most reliable devices availabletoday are not limited in reliability by the propertiesof materials; further substantial improvements inCMOS device reliability are possible and are beingmade by improvements in CMOS circuit design,processing, packaging, and testing.
Conclusion
The reliability of CMOS ICs is equal to that ofbipolar ICs of equal complexity, when each type isprepared by a well-controlled process and operatedat the same temperature. The reliability of CMOSICs in plastic depends on the design, process, cir-cuit, manufacturer, degree of testing and screening,and on the application, as well as on packaging.Plastic packages are satisfactory for the majority ofall MOS IC applications.No major differences in the reliability of products
of equal functional complexity, made with the majorMOS technologies (PMOS, CMOS, or NMOS), or ofproducts made with aluminum or silicon gates, areevident in the available reliability data. Further-more, the reliability of MOS devices can be con-sidered to be equal to that of bipolar digital circuitsof equal complexity when each type is prepared by awell-controlled process and operated at the sametemperature.The potential failure mechanisms of CMOS
devices are now well understood, and CMOS devicesare being made by processes that minimize suscep-tibility of those devices to electrical degradation orcatastrophic failure. Process changes made in recentyears have lowered costs as well as substantially im-proved the reliability of CMOS ICs. M
COMPUTER12
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6. E. C. Douglas and A. G. F. Dingwall, "Ion Implan-tation for Threshold Control in COS/MOSCircuits," IEEE Trans. Electron Devices, Vol.ED-21, June 1974, pp. 324-331.
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11. Y. Nishi, "Silicon on Sapphire Technology," ibid.,pp. 89-116.
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16. W. H. White, "Versatile Bulk CMOS," EASCON 77Record, Sept. 1977, pp. 30-5A to 30-5D.
17. A. C. Ipri and J. C. Sarace, "Integrated Circuit Pro-cess and Design Rule Evaluation Techniques,"RCA Rev., Vol. 38, Sept. 1977, pp. 323-350.
18. A. Aitken and P. Kung, "The Influence of Designand Process Parameters on the Reliability of CMOSIntegrated Circuits," Microelectron. and Reliab.,Vol. 17, Jan. 1978, pp. 201-210.
19. N. Snyderman, "Seniconductor Materials," Elec-tronic News, Mar. 20, 1978, pp. 86-88.
20. M. Lassus and J.-P. Founaud, "Modern PhysicsBrings Semiconductor Technology to a TurningPoint," Microelectron. and Reliab., Vol. 16, No. 4,1977, pp. 367-387.
21. H. Khajezadeh and A. S. Rose, "Reliability Evalua-tion of Trimetal Integrated Circuits in PlasticPackages," 15th Ann. Proc. Reliab. Phys., 1977, pp.244-249.
October 1978
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22. D. Blandford, "Industry Standard for B-SeriesCMOS," Microelectron. and Reliab., Vol. 16, No. 4,1977, pp. 449-460.
23. G. L. Schnable, "Reliability of MOS Devices inPlastic Packages," Proc. of the Tech. Program In-tern'l Microelectronics Conf, 1976, pp. 82-91.
24. W. Eccleston and M. Pepper, "Modes of Failure ofMOS Devices," Microelectron. and Reliab., Vol. 10,No. 10, Oct. 1971, pp. 325-338.
25. G. L. Schnable and R. S. Keen, "On FailureMechanisms in Large-Scale Integrated Circuits," inAdvances in Electronics and Electron Physics, Vol.30, L. Marton, Editor, Academic Press, New York,1971, pp. 79-138.
26. G. L. Schnable, H. J. Ewald, and E. S. Schlegel,"MOS Integrated Circuit Reliability," IEEETrans. Reliab., Vol. R-21, Feb. 1972, pp. 12-19.
27. E. D. Colbourne, G. P. Coverley, and S. K. Behera,"Reliability of MOS LSI Circuits," Proc. IEEE,Vol. 62, Feb. 1974, pp. 244-259.
28. D. J. Burns and V. C. Kapfer, "A ComparativeReliability Evaluation of C/MOS-A MaturingTechnology," Proc. 1975 Ann. Reliab. and Maint.Symp., Jan. 1975, pp. 354-359.
29. J. Kinney, "Solid Statements from Solid StateScientific, Inc.," Reliability Bulletin No. 25, SolidState Scientific, Inc., Montgomeryville, Pa., Sept.1975.
30. M. N. Vincoff and G. L. Schnable, "Reliability ofComplementary MOS Integrated Circuits," IEEETrans. Reliab., Vol. R-24, Oct. 1975, pp. 255-259.
31. L. Mattera, "Component Reliability, PartI: Failure Data Bears Watching," Electronics, Vol.48, No. 20, Oct. 2, 1975, pp. 91-98; "ReliabilityRevisited: Failure-Rate Comparisons are Given aSecond Look," Electronics, Vol. 48, No. 26, Dec. 25,1975, pp. 83-85.
32. M. Stitch, G. M. Johnson, B. P. Kirk, and J. B.Brauer, "Microcircuit Accelerated Testing UsingHigh Temperature Operating Tests," IEEE Trans.Reliab., Vol. R-24, Oct. 1975, pp. 238-250; "Adden-dum," IEEE Trans. Reliab., Vol. R-25, No. 2, Apr.1976, p. 62.
33. J. S. Smith and D. D. Talada, "A CMOS/SOSReliability Study," 14th Ann. Proc. Reliab. Phys.,1976, pp. 23-32.
34. T. J. Kobylarz and A. J. Graf, "Long Term Dor-mant Storage Testing, Initial Results," Proc. 1976Ann. Reliab. and Maint. Symp., Jan. 1976, pp.176-181.
35. R. P. Schuster and R. D. Fischer, "Analysis of Elec-tronic Component Screening Programs and TheirCost Effectiveness," IEEE Trans. Mfg. TechnoL,Vol. MFT-5, June 1976, pp. 37-43.
36. "Reliability Report-1976 CMOS Life StressTesting," Motorola Semiconductor Products, Inc.,Austin, Tex., June 1976.
37. "Reliability Report-1976 CMOS Plastic ICPackaging System," Motorola SemiconductorProducts, Inc., Austin, Tex. June 1976.
38. G. M. Johnson, "Accelerated Testing HighlightsCMOS Failure Modes," EASCON '76 Record, Sept.1976, pp. 142-A to 142-I.
39. G. Caswell and S. Cohen, "A Reliability Study ofCMOS/SOS Technology," GOMAC '76 Pro-ceedings, Nov. 1976, pp. 84-87.
40. S. Kumar, "Failure Mechanism in MOS Devicesversus HC1 Gettering," Proc. Advanced Tech-niques in Failure Analysis Symp.-1976, Feb. 1976,pp. 104-109.
41. "Semiconductor Data Library/CMOS," Vol. 5,Series B, Motorola Semiconductor Products, Inc.,Austin, Tex., 1976, pp. 3-2 to 3-3, 6-2 to 6-20.
42. W. E. Ham, M. S. Abrahams, J. Blanc, and C. J.Buiocchi, "The Study of Microcircuits by Transmis-sion Electron Microscopy," RCA Rev., Vol. 38,Sept. 1977, pp. 351-389.
43. M. E. Levy, "An Investigation of Flaws in ComplexCMOS Devices by a Scanning PhotoexcitationTechnique," 15th Ann. Proc. Reliab. Phys., 1977,pp. 44-53.
44. G. M. Johnson and M. Stitch, "Microcircuit Ac-celerated Testing Reveals Life Limiting FailureModes,'" 15th Ann. Proc. Reliab. Phys., 1977, pp.179-195.
45. B. Maximow, E. M. Reiss, and S. Kukunaris, "Ac-celerated Testing of Class A CMOS Integrated Cir-cuits," 15th Ann. Proc. Reliab. Phys., 1977, pp.212-216.
46. A. Shumka, E. L. Miller, and R. R. Piety, "FailureModes and Analysis Techniques for CMOSMicrocircuits," Proc. ATFA-77, Sept. 1977, pp.75- 87.
47. J. M. Patterson, "Failures Due to Pinholes inPolysilicon Conductors on CMOS MemoryDevices," Proc. ATFA-77, Sept. 1977, pp. 60-63.
48. M. J. Fox, "A Comparison of the Performance ofPlastic and Ceramic Encapsulations Based onEvaluation of CMOS Integrated Circuits,"Microelectron. and Reliab., Vol. 16, No. 3, 1977, pp.251-254.
49. "Memory/LSI, 1977," Second Edition, MDR-7,Reliability Analysis Center, Rome Air Develop-ment Center, 1977.
50. T. T. Sheng and R. B. Marcus, "Gate Oxide Thin-ning at the Isolation Oxide Wall," J. Electrochem.Soc., Vol. 125, Mar. 1978, pp. 432-434.
51. R. J. Mattauch and W. M. Howle, Jr., "FieldStrength Degradation in Si-SiO2-Polycrystalline SiStructures," IEEE J. of Solid-State Circ., Vol.SC-11, Oct. 1976, pp. 732-735.
52. M. R. Child, D. W. Ranasinghe, and D. White, "Ap-plications of the Scanning Electron Microscope inthe Development of Microtechnology," Proc.ATFA-77, Sept. 1977, pp. 323-344.
53. R. M. Anderson and D. R. Kerr, "Evidence for Sur-face Asperity Mechanism of Conductivity in OxideGrown on Polycrystalline Silicon," J. Appl Phys.,Vol. 48, Nov. 1977, pp. 4834-4836.
54. H. M. Naguib and L. H. Hobbs, "The Reduction ofPoly-Si Dissolution and Contact Resistance at Al/n-Poly-Si Interfaces in Integrated Circuits," J. Elec-trochem. Soc., Vol. 125, Jan. 1978, pp. 169-171.
55. R. Allan, "The Failure Tracers," IEEE Spectrum,Vol. 13, No. 10, Oct. 1976, pp. 33-39.
56. E. R. Hnatek, "Semiconductor Memory AttritionSummary," IEEE 1976 Semiconductor Test Sym-posium Digest, Oct. 1976, pp. 35-40.
57. C. R. Barrett and R. C. Smith, "Failure Modes andReliability of Dynamic RAMs," System Design-ADiscipline in Transition, COMPCON 77 SpringDigest, Feb. 1977, pp. 179-182.
58. J.C. McDonald and P. T. McCracken, "Testing forHigh Reliability," ibid., pp. 190-191.
59. E. R. Hnatek, "Microprocessor Device Reliability,"Microprocessors, Vol. 1, June 1977, pp. 299-303.
60. D. S. Peck, "Current Status of Integrated-CircuitReliability," Proc. Int. Conf. on Thin- and Thick-Film Technology, Augsburg, Germany, Sept. 1977,pp. 223-228.
COMPUTER14
61. C. H. Sie, R. A. Youngblood, J. H. Liao, and A.Turk, "Soft Failure Modes in MOS RAMs," 15thAnn. Proc. Reliab. Phys. 1977, pp. 27-32.
62. R. V. Pappu, E. Harris, and M. Yates, "ScreeningMethods and Experience with MOS Memory,"Microelectron. and Reliab., Vol. 17, Jan. 1978, pp.193-199.
63. B. Hall, "The Microprocessor Failure Rate Predic-tions," Microelectron. and Reliab., Vol. 17, No. 1,Jan. 1978, pp. 211-221.
64. J. W. Peeples, "Influence of Electrical Bias Levelon 85/85 Test Results of Plastic Encapsulated 4KRAMs," 16th Ann. Proc. Reliab. Phys., 1978.
65. B. E. Deal, "The Current Understanding of Chargesin the Thermally Oxidized Silicon Structure," J.Electrochem. Soc., Vol. 121, June 1974, pp.198C-205C.
66. R. Williams, "Properties of the Silicon-SiO2 Inter-face," J. Vac. Sci. Technol., Vol. 14, Sept./Oct. 1977,pp. 1106-1111.
67. E. H. Nicollian, "Electrical Properties of the Si-SiO2 Interface and its Influence on Device Perform-ance and Stability," J. Vac. Sci. TechnoL, Vol. 14,Sept./Oct. 1977, pp. 1112-1121.
68. P. Solomon, "Breakdown in Silicon Oxide-AReview," J. Vac. Sci. Technol., Vol. 14, Sept./Oct.1977, pp. 1122-1130.
69. B. R. Singh and P. Balk, "Oxidation of Silicon in thePresence of Chlorine and Chlorine Compounds," J.Electrochem. Soc., Vol. 125, Mar. 1978, pp. 453-461.
70. W. S. DeForest, Photoresist, McGraw-Hill BookCo., New York, 1975.
71. E. I. Gordon and D. R. Herriott, "Pathways inDevice Lithography," IEEE Trans. Electron.Devices, Vol. ED-22, July 1975, pp. 371-375.
72. K. A. Pickar, "Ion Implantation inSilicon-Physics, Processing and MicroelectronicDevices," in Applied Solid State Science, Vol. 5,edited by R. Wolfe, Academic Press, New York,1975, pp. 151-249.
73. E. Philofsky and E. L. Hall, "A Review of theLimitations of Aluminum Thin Films on Semicon-ductor Devices," IEEE Trans. on Pts. Hbr. Pkg.,Vol. PHP-11, Dec. 1975, pp. 281-290.
74. A. J. Learn, "Evolution and Current Status ofAluminum Metallization," J. Electrochem. Soc.,Vol. 123, June 1976, pp. 894-906.
75. P. B. Ghate, J. C. Blair, and C. R. Fuller, "Metalliza-tion in Microelectronics," Thin Solid Films, Vol. 45,Aug. 15, 1977, pp. 69-84.
76. G. L. Schnable, W. Kern, and R. B. Comizzoli,"Passivation Coatings on Silicon Devices," J. Elec-trochem. Soc., Vol. 122, Aug. 1975, pp. 1092-1103.
77. W. Kern and R. S. Rosler, "Advances in DepositionProcesses for Passivation Films," J. Vac. Sci.TechnoL., Vol. 14, Sept./Oct. 1977, pp. 1082-1099.
78. J. M. Lock, et al., Proc. Symp. Plastic EncapsulatedSemicond. Dev., (symposium held at the RoyalSignals and Radar Establishment, Malvern,England, May 1976), pp. 1-13 /17.
79. C. H. Taylor, "Plastic Encapsulated SemiconductorDevices-A Bibliography," Microelectron. andReliab., Vol. 16, No. 6, 1977, pp. 701-704.
80. J. Lyman, "Demands of LSI are Turning ChipMakers Towards Automation, Production Innova-tions," Electronics, Vol. 50, No. 15, July 21, 1977,pp. 81-92.
8L A. H. Agajanian, "Semiconducting Devices: ABibliography of Fabrication Technology, Proper-ties, and Applications," IFI/Plenum Data Co., NewYork, 1976.
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0
82. R. C. Olberg and J. L. Bozarth, "Factors Con-tributing to the Corrosion of the Aluminum Metalon Semiconductor Devices Packaged in Plastics,"Microelectron. and Reliab., Vol. 15, No. 6, 1976, pp.601-611.
83. R. B. Comizzoli, "Aluminum Corrosion in thePresence of Phosphosilicate Glass and Moisture,"RCA Rev., Vol. 37, Dec. 1976,- pp. 483-490.
84. B. Reich, "Bias Influence on Corrosion of PlasticEncapsulated Device Metal Systems," IEEETrans. on Reliab., Vol. R-25, Dec. 1976, pp. 296-298.
85. E. P. G. T. van de Ven and H. Koelmans, "TheAnodic Corrosion of Aluminum," J. Electrochem.Soc., Vol. 123, Jan. 1976, pp. 143-144.
86. W. M. Paulson and R. P. Lorigan, "The Effect ofImpurities on the Corrosion of AluminumMetallization," 14th Ann. Proc. Reliab. Phys., 1976,pp. 42-47.
87. F. Neighbour and B. R. White, "Factors GoverningAluminum Interconnection Corrosion in Plastic En-capsulated Microelectronic Devices," Microelec-tron. and Reliab., Vol. 16, No. 2, 1977, pp. 161-164.
88. A. Quach and W. L. Hunter, "A Study of Propertiesof Plastics Used for SemiconductorEncapsulation," J. Electronic Mtls., Vol. 6, May1977, pp. 319-331.
89. N. L. Sbar and R. P. Kozakiewicz, "New Accelera-tion Factors for Temperature, Humidity, BiasTesting," 16th Ann. Proc. Reliab. Phys., 1978, pp.161-178.
90. M. Lenzlinger, '-'Gate Protection of MIS Devices,"IEEE Trans. Electron Devices, Vol. ED-18, Apr.1971, pp. 249-257.
91. L. W. Linholm and R. F. Plachy, "ElectrostaticGate Protection Using an Arc Gap Device," 11thAnn. Proc. Reliab. Phys., 1973, pp. 198-202.
92. C. E. Jowett, Electrostatics in the Electronics En-vironment, Halstead Press, New York, 1976, pp.55-70, 107-113, 117-128.
93. "RCA COS/MOS Integrated Circuits," SSD-250,RCA Solid State, Sommerville, N.J., July 1977.
94. F. S. Hickernell and J. J. Crawford, "VoltageBreakdown Characteristics of Close SpacedAluminum Arc Gap Structures on OxidizedSilicon," 15th Ann. Proc. Reliab. Phys., 1977, pp.128-131.
95. R. K. Pancholy, "Gate Protection for CMOS/SOS,"14th Ann. Proc. Reliab. Phys., 1977, pp. 132-137.
96. L. J. Gallace and H. L. Pujol, "The Evaluation ofCMOS Static-Charge Protection Networks andFailure Mechanisms Associated with OverstressConditions as Related to Device Life," 15th Ann.Proc. Reliab. Phys., 1977, pp. 149-157.
97. T. S. Speakman, "A Model for the Failure ofBipolar Silicon Integrated Circuits Subjected toElectrostatic Discharge," 12th Ann. Proc. Reliab.Phys., 1974, pp. 60-69.
98. A. C. Trigonis, "Electrostatic Discharge inMicrocircuits," Proc. 1976 Annual Reliab. andMaint. Symp., Jan. 1976, pp. 162-169.
99. R. L. Minear and G. A. Dodson, "Effects of Elec-trostatic Discharge on Linear Bipolar IntegratedCircuits," 15th Ann. Proc. Reliab. Phys., 1977, pp.138-143.
100. E. I. Muehldorf, "Fault Clustering: Modeling andObservation on Experimental LSI Chips," IEEE J.Solid-State Cir., Vol. SC-10, Aug. 1975, pp. 237-244.
101. C. H. Stapper, "LSI Yield Modeling and ProcessMonitoring," IBM J. Res. Develop., Vol. 20, May1976, pp. 228-234.
102. G. E. Moore, "The Cost Structure of the Semicon-ductor Industry and Its Implications for ConsumerElectronics," IEEE Trans. Cons. Electr., Vol.CE-23, No. 1, pp. x-xvi, Feb. 1977.
103. 0. Paz and T. R. Lawson, Jr., "Modification ofPoisson Statistics-Modeling Defects Introducedby Diffusion," IEEE J. Solid-State Circ., Vol.SC-12, Oct. 1977, pp. 540-546.
104. L. J. Gallace, H. L. Pujol, E. M. Reiss, G. L. Schna-ble, and M. N. Vincoff, "CMOS Reliability," RCAEngineer, Vol. 23, No. 2, Aug./Sept. 1977, pp. 61-69.
105. G. J. Brucker, R. S. Ohanian, and E. G.Stassinopoulos, "Successful Large-Scale Use ofCMOS Devices on Spacecraft Traveling ThroughIntense Radiation Belts," IEEE Trans. on Aerosp.and Electron. Syst., Vol. AES-12, Jan. 1976, pp.23-29.
106. W. R. Dawes, Jr., G. F. Derbenwick, and B. L.Gregory, "Process Technology for Radiation-Hardened CMOS Integrated Circuits," IEEE J.Solid-State Circ., Vol. SC-li, Aug. 1976, pp.459-465.
107. E. M. Reiss, "Radiation-Hardened CMOS," 1976Govt. Microcirc. Appl. Conf (GOMAC) Digest,Nov. 1976, pp. 154-157.
108. C. W. Gwyn, "Radiation Effects in the InsulatorRegion of MOS Devices," in Oxides and OxideFilms, Vol. 4, edited by J. W. Diggle and A. K. Vijh,Marcel Dekker, Inc., New York, 1976, pp. 99-168.
109. H. Borkan, "Radiation Hardening of CMOS Tech-nologies-An Overview," IEEE Trans. Nucl. Sci.,Vol. NS-24, Dec. 1977, pp. 2043-2046.
110. A. Pikor and E. M. Reiss, "Technological Advancesin Manufacture of Radiation-Hardened CMOS In-tegrated Circuits," IEEE Trans. Nucl. Sci., Vol.NS-24, Dec. 1977, pp. 2047-2050.
111. T. J. Sanders, "CMOS Hardness AssuranceThrough Process Controls and Optimized DesignProcedures," IEEE Trans. Nucl Sci., Vol. NS-24,Dec. 1977, pp. 2051-2055.
112. A. London, D. A. Matteucci, and R. C. Wang,"Establishment of a Radiation-Hardened CMOSManufacturing Process," IEEE Trans. Nucl. Sci.,Vol. NS-24, Dec. 1977, pp. 2056-2059.
113. B. LeBoss, "News Update," Electronics, Vol. 51,No. 4, Feb. 16, 1978, p. 8.
114. D. A. Hodges, "A Review and Projection ofSemiconductor Components for Digital Storage,"Proc. IEEE, Vol. 63, Aug. 1975, pp. 1136-1147.
115. J. Cunningham and J. Jaffe, "Insight into RAMCosts Aids Memory-System Design," Electronics,Vol 48, No. 25, Dec. 11, 1975, pp. 101-103.
116. J. Luecke, "Overview of SemiconductorTechnology Trends," Computers... by the Millions,for the Millions, COMPCON 76 Fall Digest, Sept.1976, pp. 52-55.
117. R. J. Koppel and I. Maltz, "Predicting the RealCosts of Semiconductor-Memory Systems," Elec-tronics, Vol. 49, No. 24, Nov. 25, 1976, pp. 117-122.
118. L. Altman, "Five Technologies Squeezing MorePerformance from LSI Chips," Electronics, Vol. 50,No. 17, Aug. 18, 1977, pp. 91-112.
119. R. Falkenberg, "Future SemiconductorMemories-A System Designer's View,"WESCON/77 Record, Sept. 1977, pp. 17/2-1 to17/2-4.
120. A. G. F. Dingwall, R. E. Stricker, and J. 0. Sin-niger, "A High Speed Bulk CMOS- C2LMicroprocessor," IEEE J. Solid-State Circ., Vol.SC-12, Oct. 1977, pp. 457-462.
121. R. G. Stewart, "High-Density CMOS ROMArrays," ibid., pp. 502-506.
COMPUTER16
122. G. Kasouf and S. Mercurio, "Evaluation ofLSI/MSI Reliability Models," Proc. 1978 Ann. Rel.Maint. Symp., Jan. 1978, pp. 443-446.
123. R. W. Keyes, "Physical Limits in Digital Elec-tronics," Proc. IEEE, Vol. 63, May 1975, pp.740-767.
124. G. Meusburger and R. Sigusch, "Scaling of n-MOSDevices: Experimental Verification of an LSI Con-cept," Siemens Forsch. u. Entwickl Ber., Vol. 5,No. 6, 1976, pp. 332-337.
125. D. Widman and K.-U. Stein, "Semiconductor Tech-nologies with Reduced Dimensions," Solid StateCircuits 1976 (ESSCIRC, Toulouse), Editions duJournal de Physique, Paris, 1977, pp. 29-49.
126. G. R. Madland, "The Future of SiliconTechnology," Solid State Technol., Vol. 20, No. 8,Aug. 1977, pp. 91-99.
127. K.-U. Stein, "Noise-Induced Error Rate as LimitingFactor for Energy per Operation in Digital IC's,"IEEEJ. Solid-State Circ., Vol. SC-12, Oct. 1977, pp.527-530.
128. W. Myers, "The Limits of Silicon," Computer, Vol.11, No. 4, Apr. 1978, pp. 79-80.
129. P. Wang, "An IC Factory in the New Age-AnOverview," in Semiconductor Silicon 1977, editedby H. R. Huff and E. Sirtl, The ElectrochemicalSociety, Inc., Princeton, N.J., 1977, pp. 932-943.
130. P. Wang, "A LSI Factory of the New Age," Japan.J. AppL Phys., Vol. 17, Suppl. 17-1, 1978, pp. 3-7.
131. "Harris Wafer Fab: Automation Boosts Yields in4-Inchers," Electronics, Vol. 51, No. 8, Apr. 13,1978, pp. 80-81.
132. B. E. Deal, "New Developments in Materials andProcessing Aspects of Silicon Device Technology,"Japan. J. Appl. Phys., Vol. 16, Suppl. 16-1,1977, pp.29-35.
133. Semiconductor Silicon 1977, edited by H. R. Huffand E. Sirtl, The Electrochemical Society,Princeton, N.J., 1977.
134. "Projection Printing and Product Mix willTransform Masking Needs by 1980," Electron.Pkg. and Prod., Vol. 16, No. 2, Feb. 1977, p. 11.
135. J. B. Houston, Jr., et al., "Developments in Semi-conductor Microlithography II," Proc. of the Soc. ofPhoto-Optical Inst. Eng., Vol. 100, Apr. 1977, pp.1-174.
136. J. L. Stone and J. C. Plunkett, "Recent Advances inIon Implantation-A State of the Art Review,"Solid State Technol., Vol. 19, No. 6, June 1976, pp.35-44.
137. R. J. Duchynski, "Ion Implantation for Semicon-ductor Devices," Solid State Technol., Vol. 20, No.11, Nov. 1977, pp. 53-58; Western Electric Eng.,Vol. 21, No. 2, Apr. 1977, pp. 59-66.
138. R. Reichelderfer, et al., "Plasma Technology," SolidState Technol., Vol. 21, No.4, Apr. 1978, pp.87-121.
139. A. K. Sinha, H. J. Levinstein, T. E. Smith, G. Quin-tana, and S. E. Haszko, "Reactive PlasmaDeposited Si-N Films for MOS-LSI Passivation," J.Electrochem, Soc., Vol. 125, Apr. 1978, pp. 601-608.
140. M. Shibagaki, Y. Horiike, and T. Yamazaki, "LowTemperature Silicon Nitride Deposition UsingMicrowave-Excited Active Nitrogen," Japan. J.AppL Phys., Vol. 17, Suppl. 17-1, 1978, pp. 215-221.
141. Proc. ERADCOM Symp. on Plastic Encap-sulated/Polymer Sealed Semiconductors for ArmyEquipment, Symposium held at Fort Monmouth,N.J., May 1978.
142. B. LeBoss, "C-MOS Gets a Rise Out of LSI," Elec-tronics, Vol. 50, No. 21, Oct. 13, 1977, pp. 65-66.
143. "Worldwide Equipment Sales to Top $100 Billion,"Electronics, Vol. 51, No. 1, Jan. 5, 1978, pp.125-148.
144. M. Gold and D. Hanson, "C/MOS MPU Applica-tions Spur RCA Deal with Intel," Electronic News,Vol. 23, No. 1179, Apr. 10, 1978, pp. 22, 26.
145. "RCA to Make Intel Parts Using SOS," Electron-ics, Vol. 51, No. 8, Apr. 13, 1978, pp. 41-42.
146. W. F. Arnold, "SOS Pact has 'em Guessing," Elec-tronics, Vol. 51, No. 9, Apr. 27, 1978, pp. 94-95.
147. Y. Nishi and H. Hara, "Physics and Device Tech-nology of Silicon on Sapphire," Japan. J. ApplPhys., Vol. 17, Suppl. 17-1, 1978, pp. 27-35.
148. L. C. Hamiter, Jr., "How Reliable are MOS IC's?As Good as Bipolars, Says NASA," Electronics,Vol. 42, No. 13, June 23, 1969, pp. 106-110.
149. D. A. Hodges, "Components for SemiconductorMemories," 1973 IEEE INTERCON Technical Pa-pers, Solid State, Mar. 1973, pp. 2/1-1 to 2/1-2.
George L. Schnable is head of solidstate process research in RCA Labora-tories' Integrated Circuit TechnologyCenter. He has been involved in elec-tronic materials and process technol-ogy R&D for 25 years, both at RCAand at Philco-Ford. He is the author orcoauthor of more than 50 publicationsand holds 20 US patents. He is a mem-ber of a number of societies, including
the American Chemical Society and the IEEE. He re-ceived a BS degree in chemistry from Albright Collegeand holds MS and PhD degrees from the University ofPennsylvania.
Larry J. Gallace is manager of theReliability Engineering Laboratory inRCA's Solid State Division in NewJersey. He joined RCA in 1958 and has
t: f g'l0worked predominantly in the area of-0 \% ! f t awreliability engineering. Since 1972, he
has been heavily involved in develop-ing test methods for characterizing
* £g;g l the reliability of CMOS devices. Hehas been a recipient of RCA team
awards for silicon power transistor engineering. He holdsa BS degree in mathematics and an MS degree in appliedand mathematical statistics, both from Rutgers Univer-sity.
Henry L. Pujol is manager of engineer-ing, assembly, and test at RCA's SolidState Division in West Palm Beach,Florida. He joined RCA in 1969 andhas been responsible for the design ofmany standard CD4000 series circuits.He has been responsible for worldwidemarket planning of CMOS standardparts and for the application engineer-ing of MOS logic products, including
custom-circuit support, product specifications, and testspecifications. He holds a BSEE from City College of NewYork and an MSEE from Rutgers University.
October 1978 17
