Transcript
Page 1: R&D ERL ERL LLRF System

February 17-18, 2010

R&D ERL

Kevin S. Smith

R&D ERLERL LLRF System

Kevin S. Smith

February 17-18, 2010

LLRF System

Page 2: R&D ERL ERL LLRF System

February 17-18, 2010

R&D ERL

Kevin S. Smith

LLRF Control Requirements

• Three major sub-system components– 50 kW 5-Cell ERL SRF Cavity, Qext = 3E7

– 1 MW SRF Photocathode Gun, Qext = 40E3

– Laser

• Cavity Field Control Objectives– Amplitude : 0.01% pp

– Phase : 0.05 deg rms

• Laser Control Objective– 9.383 MHz (h=120) phase reference with < 400fs rms integrated jitter

• Energy regulation feasibility

• User Interface and Diagnostic Data

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Page 3: R&D ERL ERL LLRF System

February 17-18, 2010

R&D ERL

Kevin S. Smith

• Carrier Board− Stand alone control system interface, daughter host platform,

communication hub, timing, data acquisition management, power …

• Daughter Module– Provide system specific functionality (ADCs, DACs, DSP, etc.) and signal

processing horsepower

• A LLRF Controller is a stand-alone configurable, modular, hardware / software platform, the basic building block from which a complete LLRF system is built up.

• Two major components from which any Controller is configured:– “Controller” = “Carrier Board” + “Daughter Modules”

BNL Generic LLRF Controller

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• R&D ERL system is a variant of the recently developed generic LLRF Controller, currently being commissioned at both RHIC and the EBIS injector for RHIC

Page 4: R&D ERL ERL LLRF System

February 17-18, 2010

R&D ERL

Kevin S. Smith

LLRF Controller Major Features

• Carrier Board– Xilinx Virtex-5 FX FPGA with remote reconfiguration via ethernet– Embedded RHIC Front End Computer (FEC) with all Controls links– 1x 10/100/1000 Ethernet, 1x 10/100 Ethernet, 2x RS-232– 3x 3.25 Gb/s multi-protocol external (chassis to chassis) serial links– 1 Gbyte DDR2 SO-DIMM, 32 Mbyte Configuration FLASH– Multiple clock distribution, RF “Update Link” distribution– External RF IOs and monitors, digital IOs– Monitoring of Carrier and Daughter system health (temps, voltages, currents)

• Daughter Modules– Xilinx Virtex-5 FX, SX or LX FPGA with remote reconfiguration via ethernet– 6x 3.25 Gb/s serial links (per site) to carrier (2) and nearest neighbors (4)– 1 Gbyte DDR2 SO-DIMM, 32 Mbyte Configuration FLASH, 2x RS-232– Flexible low noise PLL and clock distribution– Standard interface to carrier via “XMC” mezzanine format, COTs compatible– Custom “front ends”: ADCs, DACs, DSPs, etc.

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Page 5: R&D ERL ERL LLRF System

February 17-18, 2010

R&D ERL

Kevin S. Smith

LLRF System Block Diagram

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WAVEGUIDE TUNER

WAVEGUIDE TUNER

LOAD

IOT

IF

LO

RF

IF

LO

RF

IF

LO

RF

ERL 5-CELL703.75 MHz

20 MeV

BEAM DUMP

BPM

IF

LO

RF

FIELD PROBE

RF GUN BEAM PHASE

PICKUP

OUTSIDE

INSIDE

ERL TEST FACILITY, BLDG 912LLRF CONTROL BLOCK DIAGRAMREV A02/04/2010KSS

PIEZO TUNER

PIEZO TUNER

“LASER BEAM”

RF GUN703.75 MHz

2.5 MeV

IF

LO

RF

IF

LO

RF

IF

LO

RF

IF

LO

RF

CIRCULATING BEAM PHASE

PICKUP

LOAD

IOT

IF

LO

RF

IF

LO

RF

IF

LO

RF

IF

LO

RF

LLRF Controller 15-Cell Cavity and Beam Feedback

LLRF Controller 2RF Photocathoide Gun and Laser

1600 MHz PLL

100 MHzUltra Low NoiseMaster Oscillator

RHICEVENT

LINK

800 MHz 800 MHz SAT

RF

DR

IVE

P F

OW

AR

D

P R

EF

LEC

TE

D

FIE

LD

PR

OB

E

RF

DR

IVE

P F

OW

AR

D

P R

EF

LEC

TE

D

FIE

LD

PR

OB

E

TU

NIN

G R

EF

TU

NIN

G R

EF

BP

M O

UT

SID

E

BP

M IN

SID

E

PH

AS

E C

IRC

UL

AT

ING

BE

AM

PH

AS

E I

NJE

CT

ED

BE

AM

PULSE PICKER TRIGGER

LASER RF REFERENCE

LA

SE

R R

F R

EF

PU

LS

E P

ICK

ER

R

EF

2.5 Gbit SERAL LINK

2.5 Gbit SERAL LINK

2.5

Gb

it S

ER

AL

LIN

K

2.5

Gb

it S

ER

AL

LIN

K

RHICRTDL

LLRF UPDATE

LINKGigE

RHICEVENT

LINK

RHICRTDL

LLRF UPDATE

LINKGigE

EXTERNAL 100 MHz

REF

Page 6: R&D ERL ERL LLRF System

February 17-18, 2010

R&D ERL

Kevin S. Smith

LLRF System Topology

• System is a variant of the BNL RHIC and EBIS LLRF systems currently undergoing development and commissioning

• Generator Driven Resonator− Very commonly used (CEBAF, SNS, Cornell …)

− Amplitude and Phase stabilization via digital IQ control loop readily implemented in modern FPGA based systems

− Intrigued by JLAB digital SEL as well

− Currently characterizing 5-cell cavity behavior using analog PLL system.

• RF DACs are 16 bit, 400 MSPS, 1 GHz analog BW

• RF ADCs are 16 bit, 100 MSPS, 700 MHz analog BW

• Current plan is to use a 96.25 MHz IF = 800 MHz – 703.75 MHz

• Systems based on similar technology have already demonstrated 0.01% amplitude and 0.02 deg phase stability

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