Slide 1

Quality Assurance System for the Endcap Hybrids of the ATLAS Semiconductor Tracker Micha Dwunik, for the SCT collaboration AGH University of Science and Technology, Faculty of Physics and Applied Computer Science Krakow, Poland Slide 2 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow ATLAS Inner Detector 61 m 2 of Silicon 4088 modules in total 1976 forward modules 2112 barrel modules 6.3*10 6 channels ~1% occupancy 4 layers 9 disks each side Slide 3 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow Module flavours ~120 mm (60 mm) AC coupled strips 1536 channels Double sided readout Limited R(z) resolution (40 mrad tilt) Data communication via double optical link or redundant LVDS Slide 4 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow strip direction Endcap module construction Carbon spine Sensors Kapton PCB Connectors 12 ABCD3T Readout chips DORIC/VDC chips Hybrid Fanouts Slide 5 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow Hybrid functionality HV/LV distribution and filtering Heat removal Mechanical support Readout Slide 6 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow ABCD3T readout chip 128 channels Binary readout Channel by channel threshold correction Bypass functionality Preamp, shaper discriminator 132 cell FIFO Derandomiser Output buffers Control logic BIAS,DACs, calibration Input register Slide 7 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow DORIC and VDC transmission chips Digital Optical Receiver IC Pin diode BPM signal-> LVDS command and clock VCSEL Driver Circuit LVDS data -> Pin driving SE signal Not qualified technology - > rad-hardness added by design only Slide 8 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow Why do we need _hybrid_ Quality Assurance? Cost/component loss minimization Hybrid -> repairs possible Module -> repairs practically impossible Performance measurements parameter map (SCT DB) Infant mortality Slide 9 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow Production chain ABCD3T Wafer screening DORIC/VDC Wafer screening Manufacturer: Assembly, Simple check Other components Hybrid QA sites Module production sites Slide 10 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow SCT database Slide 11 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow Wafer screening Doric4a Power/LVDS level check Clock generation/synchronization Data decoding 35/45 Mhz operation 3.5/4.5 V operation VDC Power test Standby current test Output waveform test ABCD3T Digital functionality (Vdd, frequency) Direct DAC measurements Mater/slave functionality BC counters Characterization (analogue parameters) Slide 12 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow Hybrid Test Chain Manufacturer: Basic functionality QA site Visual inspection Warm Characterization (4h, 55 C) Burn-in test/long term stability (40h, 55 C) Cold characterization (6h, 0 C) Visual inspection Module assembly site Basic functionality (reception test) Slide 13 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow Characterization Digital/communication tests Command delay Bypass functionality Redundancy test Pipeline test Strobe delay test Analogue (calibrated response) Three Point Gain Trim Range Response Curve Timewalk Noise occupancy test (physicalresponse) confirmation test Slide 14 2005-09-14LECC 2005, Micha Dwunik, AGH Krakow Acceptance criteria Succesfull visual inspection Full digital functionality