FSSR2 Capacitive Noise Measurement and
Analysis
L. Vitale, A. Srebrnic
13th Feb, 2012
Abstract
The goal of this measurement is to determine the capacitive noiseaffecting the FSSR2’s ADC thresholds.
Contents
1 Introduction 21.1 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Measurements 32.1 Initial checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.2 Calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Data analysis 43.1 Encountered problems . . . . . . . . . . . . . . . . . . . . . . . . 43.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
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Figure 1: The FSSR2 module with the lid open.
1 Introduction
1.1 Equipment
The FSSR2 is a self-triggered low noise readout chip for silicon detectors. Itservices 128 channels and provides address, time and magnitude information foreach hit[2]. Magnitude information is obtained for each channel via 7-bit FlashADC with settable thresholds.
The chip uses LVDS1 to communicate with the outside world, so several lay-ers of equipment are needed in order to interface with it. We used the following:
• A PCB for the chip to fit on, and to hold the various capacitors in place.
• Custom adapter board
• CAEN V1495 FPGA board with custom bit-stream
• Agilent E3631A Power Supply
1Low Voltage Differential Signal
2
• A computer running LabView 2009
• A ROOT script to cut and fit the calibration data
Figure 2: Detail of the FSSR2 board: three chips are present, but only themiddle one is tested. At the bottom of the board, the pins for the capacitorscan be seen.
2 Measurements
2.1 Initial checks
When starting, it’s important to check the ADC threshold settings: if the thresh-olds are too low, the FSSR2 picks up ambient noise and calibration is impossible.Threshold settings are considered adequate when the chip produces less than10 hits per second when in acquisition mode.
The capacitance of the test capacitors is measured with a high precision ca-pacitance meter. This turned out to be unnecessary, because the 5% toleranceon the nominal capacitor value turned out to be far inferior than the error onour data. The test capacitors are then inserted into their sockets on the mainPCB.
At this stage it’s crucial to check whether the bonds are still connectedand functional. Bond failures are quite common due to mechanical stress (e.i.PCB bending) upon capacitor insertion. Failures of course lead to unexpectedbehavior (and headaches).
We noted that if a bond fails at the far end from the chip, it acts as anantenna and picks up ambient noise far more than any other channel, causing
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the chip to saturate, which often results in it ignoring all the hits on otherchannels.
2.2 Calibration procedure
Calibration of the FSSR2 is obtained by pulsing each channel with a square wavesignal with increasing amplitude (see figure 3). This procedure is then repeatedup to 10000 times to gain more data. The start and stop amplitude, along withthe number of repeats can be set in software. Additionally, the FSSR2’s channelkill mask can be used to exclude all the channels not under observation.
Once the module is set up, it is enclosed in a metallic container to shield itfrom EMI. Calibration is set up via a program in LabView which let us controlall the FSSR2’s registers and send commands to the chip.
We repeated 100 and 1000 acquisition per channel, which resulted in a largeamount of data, even when we killed the unused channels. We later discoveredthat due to software limitations, we were collecting data from two additionalFSSR2 chips that were bonded on the same PCB. Fortunately we were able tofilter out the unused bits after the data acquisition phase.
3 Data analysis
Data analysis is performed using ROOT and two scripts: one cuts out theunused data and puts it into histograms while the second one fits them andoutputs a graph of the measurements. The function used to fit the data is thefollowing:
1
2
(1 + erf
x− p1p2√
2
)(1)
where p1 and p2 are the mean and standard deviation of the hit distributionrespectively. The standard deviation represents the threshold error, and is ex-pressed in DAC units. The conversion rate between threshold error and ENCis ≈ 300 e/δth.
3.1 Encountered problems
The first problem encountered was probably due to a bug in the FPGA bit-stream. We noticed a pattern in some inconsistent data (see figure 4) Somecalibration amplitudes were getting an inexplicable low count, for every ADCthreshold. We deducted it could be a bug and ignored the flawed data by settingthe error to a value high enough so it could not interfere with the fit. Fortunatelyas long as this happenes outside the transition region, the flawed data can besafely ignored and the fit converges.
Another problem was ambient noise (possibly noise generated by FSSR2control circuitry or supply): when the calibration pulser was outputting smallamplitudes, ambient noise would add onto the signal causing the chip to registera hit. This showed up as a “noise floor” (seen in figure 5 and 6) in the graphs
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v ← Vstart
impulse(v,Ch)
Ch = 128?v = Vstop?
v ← v + 1Ch← 1
Ch← Ch+ 1
END
yes no
yes
no
Figure 3: FSSR2 calibration flowchart
Figure 4: Inconsisted data points are circled in purple.
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and made the fit diverge. This problem was mitigated by eliminating all dataoutside the BCO range 128± 5.
3.2 Results
Fitting the calculated ENC from all the intermediate fits to a straight line,we can approximate the ENC by capacitance, and finally obtain the FSSR2’sintrinsic noise by extrapolating to zero capacitance. The slope of the fitted lineis 19± 8 e−/pF and the intercept is (0.29± 0.15) · 103 e−.
If we exclude the last point in the fit (the one for 33 pF), the fitted line hasa slope of 28± 10 e−/pF and the intercept is (0.20± 0.16) · 103 e−.
References
[1] The INFN SLIM5 website
[2] V. Re, M. Manghisoni, L. Ratti, J. Hoff, A. Mekkauoi, R. Yarema, “FSSR2,a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors”
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Figure 5: Really noisy data, fit is impossible.
Figure 6: Less noise, but fit is still impossible without modifying the fit function.Notice some inconsistant data is still present!
Capacitance [pF] ENC [e−]3.9 235± 216.8 223± 2110 700± 4218 727± 3918 806± 3927 836± 4233 743± 36
Table 1: Results
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y=18.97*x+293.6Legend
ENC
[e rm
s]
0
200
400
600
800
1000
Capacitance [pF]0 5 10 15 20 25 30 35
Figure 7: Final linear fit of data
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