Transcript
Page 1: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 – Digital System Design

Multiplexers and Demultiplexers

(Lecture #13)

Page 2: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 2

Multiplexers

Page 3: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 3

Multiplexer

A multiplexer switches (or routes) data from 2N inputs to the output, where N is the number of

select inputs.

A multiplexer (mux) is a digital switch.

Page 4: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 4

Multiplexer: 2-to-1

f

s

w0

w1

0

1

0

1

f

fs

w0

w1

s

w0

w1

s = 0 selects w0

s = 1 selects w1 F = (w

0.s') + (w

1.s)

2 inputs 1 output

1 select

Page 5: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 5

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY mux2to1 ISPORT ( w0, w1, s : IN STD_LOGIC ;

f : OUT STD_LOGIC ) ;END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 ISBEGIN

WITH s SELECTf <= w0 WHEN '0',

w1 WHEN OTHERS ;END Behavior ;

Multiplexer: 2-to-1 (VHDL)

Page 6: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 6

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY mux2to1 ISPORT (w0, w1, s : IN STD_LOGIC ;

f : OUT STD_LOGIC ) ;END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 ISBEGIN

f <= w0 WHEN s = '0' ELSE w1 ;END Behavior ;

Multiplexer: 2-to-1 (VHDL)

Page 7: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

7

Multiplexer: 4-to-1

f

s 1

w 0 w 1

00

01

s 0

w 2 w 3

10

11

w 0

w 1

0

0

1

1

1

0

1

f s 1

0

s 0

w 2

w 3

f

s 1

w 0

w 1

s 0

w 2

w 3

F = (w0.s

1's

0') + (w

1.s

1's

0) +

(w2.s

1s

0') + (w

3.s

1s

0)

Two select signals

Page 8: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 8

0

w 0

w 1

0

1

w 2

w 3

0

1

f 0

1

s 1

s

Multiplexer: 4-to-1

Select signal for first level of decoders

Select signal for second level of decoders

2-to-1 Muxes

Page 9: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 9

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY mux4to1 ISPORT ( w0, w1, w2, w3 : IN STD_LOGIC ;

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;

END mux4to1 ;

ARCHITECTURE Behavior OF mux4to1 ISBEGIN

WITH s SELECTf <= w0 WHEN "00",

w1 WHEN "01",w2 WHEN "10",w3 WHEN OTHERS ;

END Behavior ;

Multiplexer: 4-to-1 (VHDL)

Page 10: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

10

Multiplexer: 16-to-1

w 8

w 11

s 1

w 0

s 0

w 3

w 4

w 7

w 12

w 15

s 3

s 2

f

Select signals (2) for second level of decoders

Select signals (2) for first level of decoders

4-to-1 Muxes

0123

01

23

01

23

01

23

01

23

Page 11: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 11

LIBRARY ieee ;USE ieee.std_logic_1164.all ;LIBRARY work ;USE work.mux4to1_package.all ;

ENTITY mux16to1 ISPORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;

s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;f : OUT STD_LOGIC ) ;

END mux16to1 ;

ARCHITECTURE Structure OF mux16to1 ISSIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGINMux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ;Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ;Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ;Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ;Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;

END Structure ;

Multiplexer: 16-to-1 (VHDL)

Page 12: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 12

Realizing Logic Functions using Multiplexers

Multiplexers

Page 13: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 13

Mux: Realizing Logic Functions

• Each row in a Truth Table corresponds to a minterm

– N-input Truth Table

• Each minterm can be mapped to a multiplexer input

– N-input Multiplexer

• For each row in the Truth Table, where the output of the function is one (F = 1),

– Set the corresponding input of the multiplexer to 1

Page 14: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 14

Given the following Truth Table:

Design a logic circuit to implement this function, using a 4-to-1 Multiplexer.

Mux: Realizing a Logic Function

0

1

0

0

1

1

1

0

1

f s 1

0

s 0

1

0

Page 15: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 15

Exercise:

Design a circuit, using a 4-to-1 Mux, to implement the Boolean expression given below.

FX,Y

= m(0,2)

Mux: Realizing a Logic Function

Page 16: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 16

Realizing Logic Functions using Multiplexers more efficiently.

Multiplexers

Page 17: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 17

Mux: Realizing Logic Functions Efficiently

• Each row in a Truth Table corresponds to a minterm

– N-input Truth Table

• A product term of N-1 variables can be mapped to each of the multiplexer inputs

– (N-1)-input Multiplexer

• For the rows in the Truth Table,

– Group N-1 inputs into pairs

– Define the output of each pair using the Nth input

Page 18: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 18

Given the following Truth Table:

Design a logic circuit to implement this function, using a 2-to-1 Multiplexer.

Mux: Realizing a Logic Function

0

1

0

0

1

1

1

0

1

f s 1

0

s 0

1

0

0

1

f s 1

s 0

s 0

Page 19: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 19

Given the Truth Table for a 3-input XOR:

Design a logic circuit to implement this function, using 2-to-1 Multiplexers.

Mux: Realizing a Logic Function

0 0

0 1

1 0

1 1

0

1

1

0

0 0

0 1

1 0

1 1

1

0

0

1

w1 w2 w3 f

0

0

0

0

1

1

1

1

w2 w3

w2 w3

Page 20: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 20

Mux: Realizing a 3-input XOR

f

w 3

w 1

w 2

0

10

1

Page 21: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 21

Exercise:

Design a circuit, using a 4-to-1 Mux, to implement the Boolean expression given below.

FX,Y,Z

= m(1,2,3,6)

Mux: Realizing a Logic Function

Page 22: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 22

Demultiplexers

Page 23: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 23

Demultiplexer

A demultiplexer switches (or routes) data from one input to 2N outputs, where N is the number

of select inputs.

A demultiplexer (mux) is also a digital switch.

A demultiplexer performs the opposite function of a multiplexer.

Page 24: ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

ECE 331 - Digital System Design 24

Demultiplexer: 1-to-4

I

s1

s0

O0

O1

O2

O3

01

2

3

S1

S0

O0

O1

O2

O3

0 0 I 0 0 0

0 1 0 I 0 0

1 0 0 0 I 0

1 1 0 0 0 I

O0 = S

1'.S

0'.I

O1 = S

1.S

0'.I

O2 = S

1'.S

0.I

O3 = S

1.S

0.I


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