© Euromicro, 1977 North-Holland Publishing Co., Amsterdam
COMPARISON OF MICROPROCESSORS : A GRAPHICAL APPROACH
DoAspinall, MoHoBarton, E.L.Dagless
D e p t . o f E l e c t r i c a l & E l e c t r o n i c E n g i n e e r i n g , U n i v e r s i t y C o l l e g e , S w a n s e a , W a l e s , UoK.
ABSTRACT
Selecting a microprocessor for a particular application is a task frequently faced today. Manufacturers usually present hardware character- istics consistently, but vary considerably in the way they describe instruction sets, which makes microprocessor comparison tedious and time- consuming. The high cost of software production suggests that care should be taken to choose the correct instruction set for a particular applica- tion.
This paper discusses briefly how various features of the instruction set, such as general layout, size of processor state vector, range of address- ing modes, bit-handling capability, and range of control orders, affect the ease with which the device may be progrcx~med.
Current aids to facilitate the comparison of instruction sets are discussed, and the case is made for a less detailed, graphical method to help in the initial stages of microprocessor selec- tion.
The problems involved in presenting a graphical description of the instruction set are outlined, and solutions are proposed.
Finally, a BASIC program is described which, given a sur~ary of a device's instruction set in a concise form, produces a graphical representa- tion of it.
io INTRODUCTION
T h i s p a p e r i s t h e r e s u l t o f w o r k w h i c h h a s b e e n c a r r i e d o u t t o p r o d u c e a g r a p h i c a l m e t h o d o f i n s t r u c t i o n s e t r e p r e s e n t a t i o n a s an a i d t o m i c r o - p r o c e s s o r comparison.
S e v e r a l i t e r a t i o n s w e r e r e q u i r e d t o c h o o s e t h e p r e s e n t c h a r t f o r m a t , and some o f t h e a r g u m e n t s f o r and a g a i n s t d i f f e r e n t l a y o u t s a r e o u t l i n e d
b e l o w .
T h e c h a r t s p r o d u c e d h a v e b e e n u s e d i n s e v e r a l m i c r o p r o c e s s o r w o r k s h o p s , t o p r e s e n t an o v e r v i e w of the instruction sets of various devices, with-
out resorting to manufacturers' descriptions, and
have been well received.
Work has also been undertaken to speed up the
production of charts by employing a BASIC program°
A brief description of this is given at the end of
the p a p e r .
2 . THE IMPORTANCE OF THE INSTRucTIoN SET
I t may be s t a t i n g t h e o b v i o u s t o s a y t h a t a n y p r o g r a m a c t i o n w h i c h t h e m i c r o p r o c e s s o r p e r f o r m s m u s t be w r i t t e n i n t e r m s o f t h e i n s t r u c t i o n s e t ; b u t t h i s s h o w s j u s t how i m p o r t a n t t h a t d i m e n s i o n i s . K n o w l e d g e o f t h e i n s t r u c t i o n s e t i m p l i e s k n o w l e d g e o f p r o c e s s o r w i d t h , r e g i s t e r l a y o u t , and memory a d d r e s s i n g c a p a b i l i t y , a s w e l l a s t h e r a n g e and t i m i n g o f f u n c t i o n s w h i c h c a n be p e r - f o r m e d . T h e r e a r e c e r t a i n f e a t u r e s o f an i n s t r u c - t i o n s e t w h i c h p r o v i d e a u s e f u l i n d i c a t i o n o f i t s s u i t a b i l i t y f o r a p a r t i c u l a r p u r p o s e , and w h i c h a r e w o r t h y o f f u r t h e r d i s c u s s i o n .
F i v e y e a r s a g o , i t w o u l d h a v e s e e m e d u n u s u a l f o r a l o g i c d e s i g n e r t o be a s k e d t o c h o o s e a c o m p u t e ~ y e t t o d a y s u c h a t a s k i s q u i t e c o m m o n p l a c e . T h e m i c r o p r o c e s s o r c h i p h a s m a d e t h e p r o c e s s o r j u s t another item in the designer's armoury of compo-
nents. Unfortunately, the IO00-fold drop in the
price of processors has not been matched by a
similar reduction in their complexity°
The microprocessor chosen for a particular
application must have the correct hardware
characteristics, just as for any other electronic component. Microprocessor manufacturers usually
list these characteristics - e.go, power supplies, clock inputs required - in a reasonably standard
form.
H o w e v e r , w h a t m a k e s m i c r o p r o c e s s o r s m o r e c o m p l e x t h a n o t h e r c o m p o n e n t s i s t h e i r a d d e d d i m e n s i o n - i n s t r u c t i o n s e t , t h e p r e s e n t a t i o n o f w h i c h i s n o t s t a n d a r d i s e d . S i n c e t h e p r o d u c t i o n o f t h e s o f t w a r e c o n s t i t u t e s a m a j o r c o s t o f d e v e l o p i n g a m i c r o p r o c e s s o r - b a s e d s y s t e m , b e t t e r s t a n d a r d - i s a t i o n c o u l d be a d v a n t a g e o u s .
84
2 . 1 G e n e r a l L a y o u t
A w e l l l a i d o u t i n s t r u c t i o n s e t , i . e . o n e w h i c h d o e s n o t p l a c e a p p a r e n t l y a r b i t r a r y r e s t r i c t i o n s on t h e f u n c t i o n / o p e r a n d 1 / o p e r a n d 2 c o m b i n a t i o n s w h i c h a r e a v a i l a b l e , r e d u c e s t h e t i m e n e c e s s a r y t o b e c o m e f a m i l i a r w i t h t h e p r o c e s s o r .
2 . 2 P r o c e s s o r W i d t h
T h e w i d t h o f t h e p r o c e s s o r d e t e r m i n e s t h e a c c u r a c y t o w h i c h a r i t h m e t i c c a n b e p e r f o r m e d . D o u b l e l e n g t h w o r k i n g may be r e q u i r e d , and "Add w i t h C a r r y " o r " S u b t r a c t w i t h B o r r o W ' i n s t r u c t i o n s w o u l d f a c i l i t a t e t h i s .
W h e r e n o n - a r i t h m e t i c p r o c e s s i n g i s b e i n g c a r r i e d o u t , p r o c e s s o r w i d t h may be c o n s i d e r e d a s t h e n u m b e r o f I / O s i g n a l s w h i c h c a n b e p r o c e s s e d i n p a r a l l e l .
2 . 3 P r o c e s s o r S t a t e ( V e c t o r )
P r o c e s s o r s t a t e [ 2 ] i s t h e i n f o r m a t i o n h e l d i n
COMPARISON OF MICROPROCESSORS : A GRAPHICAL APPROACH ~5
t h e p r o c e s s o r b e t w e e n i n s t r u c t i o n s . T h e s i z e o f t h e p r o c e s s o r s t a t e d e p e n d s on t h e n u m b e r o f o n - c h i p r e g i s t e r s a v a i l a b l e , i n c l u d i n g g e n e r a l r e g i - s t e r s , p r o g r a m c o u n t e r , i n d e x r e g i s t e r s , s t a c k p o i n t e r s ( o r h a r d w a r e s t a c k ) and s t a t u s r e g i s t e r s .
A p r o g r a m m e r w o r k i n g a t m a c h i n e l e v e l c a n u s e a s e t o f o n - c h i p r e g i s t e r s a s i f t h e y w e r e t h e s i m - p l e v a r i a b l e s o f a h i g h - l e v e l l a n g u a g e , p r o v i d e d t h e r e a r e s u f f i c i e n t f o r e a c h o n e t o b e a s s i g n e d a m e a n i n g f o r t h e d u r a t i o n o f t h e a l g o r i t h m . I f a c c e s s t o t h e s e r e g i s t e r s i s much f a s t e r t h a n t o m a i n m e m o r y , a c o n s i d e r a b l e i n c r e a s e i n e x e c u t i o n s p e e d may be a c h i e v e d . H o w e v e r , when t h e p r o c e s ~ o r s t a t e i s l a r g e , t h e r e a r e m o r e r e g i s t e r s t o b e s a v e d when d e a l i n g w i t h a c o n t e x t c h a n g e .
I t may b e n o t e d t h a t c o m p i l e r s a r e u n l i k e l y t o t a k e a d v a n t a g e o f f a s t o n - c h i p r e g i s t e r s b e c a u s e o f t h e i n c o n v e n i e n c e o f d e a l i n g w i t h t h e i r l i m i t e d a d d r e s s s p a c e ( t y p i c a l l y ~ 8 ) [ 6 ] •
2 . 4 . R a n g e o f A d d r e s s i n g Modes
E v e r y o p e r a n d w h i c h i s i n v o l v e d i n an o p e r a t i o n p e r f o r m e d by a m i c r o p r o c e s s o r r e s i d e s on t h e c h i p , i n m a i n m e m o r y , o f i n an i n p u t / o u t p u t p o r t . N e g -
l e c t i n g s p e e d r e q u i r e m e n t s , a p r o c e s s o r o f f e r i n g s i m p l y d i r e c t a d d r e s s i n g o f a l l t h e s e l o c a t i o n s w o u l d be a b l e t o e x e c u t e t h e s a m e a l g o r i t h m s a s o n e w i t h a m o r e s o p h i s t i c a t e d i n s t r u c t i o n s e t . H o w e v e r , i m p r o v e m e n t s t o t h e b a s i c i n s t r u c t i o n s e t a r e o f t e n m a d e , and t a k e two m a i n f o r m s :
( i ) S i n g l e o r d e r s a r e p r o v i d e d t o g i v e a c c e s s t o d a t a s t r u c t u r e s , s u c h a s s t a c k s a n d t a b l e s , w h e r e n o r m a l l y s e v e r a l o r d e r s wou ld b e r e q u i r e d .
( i i ) S h o r t o r d e r s , w i t h o n e o r m o r e o p e r a n d s i m p - l i e d , a r e i n t r o d u c e d t o s a v e s p a c e , a s i t i s n o t a l w a y s n e c e s s a r y t o s p e c i f y e x p l i c i t y t h e a d d r e s s o f a l l t h e o p e r a n d s . F o r s u c h o r d e r s , t h e ' n u m b e r o f a d d r e s s e s p e r i n s t r - u c t i o n ' i s s a i d t o b e r e d u c e d .
T h e s e i m p r o v e m e n t s a m o u n t t o t h e p r o v i s i o n o f additional addressing modes implied,indirect,
indexed, and autoincrement/autodecrement - and
can greatly simplify the programming of certain
types of routine. These modes are considered in more detail below.
2 . 4 . 1 .Implied Addressing
To p e r f o r m an o p e r a t i o n s u c h a s A + B + C, w h e r e A, B a n d C r e s i d e i n m a i n m e m o r y , a t h r e e - a d d r e s s o r d e r w o u l d s e e m s u i t a b l e . S u c h o r d e r s a r e n o t u s u a l on m i c r o p r o c e s s o r s b e c a u s e o f t h e c h i p com- p l e x i t y w h i c h w o u l d b e i n v o l v e d ; i n a n y c a s e , s e v e r a l s t o r e a c c e s s e s w o u l d b e r e q u i r e d t o r e a d an o r d e r c o n t a i n i n g so many a d d r e s s b i t s . T h e r e - ~ o r e , i n s t r u c t i o n s w i t h some o p e r a n d s i m p l i e d a r e o f t e n f o u n d . I n f a c t , c e r t a i n a l g o r i t h m s a r e n e a t l y i m p l e m e n t e d u s i n g t h i s t y p e o f i n s t r u c t i o n , when t h e s t a c k i s an i m p l i e d o p e r a n d . F o r e x a m p l e , c o n s i d e r e v a l u a t i n g
A * B - C * D ( a l l o p e r a n d s i n m a i n memory)
I n r e v e r s e P o l i s h :
A B * C D * -
I n c o d e :
PUSH
MUL
PUSH
MUL
RSUB
A (I address: stack + A)
B (i address: stack + stack * B)
C (i address: stack + C)
D (I address: stack + stack * D)
(O a d d r e s s : s t a c k ÷ s t a c k - s t a c k )
T h e r e s u l t i s l e f t on t h e t o p o f t h e s t a c k .
2.4.2.1ndirect Addressing
I n i n d i r e c t a d d r e s s i n g , t h e a d d r e s s o f t h e o p e r - a n d i s h e l d i n a r e g i s t e r o r a memory l o c a t i o n , n o t i n t h e i n s t r u c t i o n i t s e l f . A l t e r i n g t h e a d d r e s s a l l o w s t h e s a m e p i e c e o f c o d e t o a c c e s s d i f f e r e n t m a i n memory l o c a t i o n s .
2 . 4 . 3 .Indexed Addressing
This is an extension of indirect addressing. In
this case, the operand address is formed by add-
ing a value (typically 8 bits) from the instruc-
tion to the contents of an index register (typi-
cally 16 bits). As an example of an application,
c o n s i d e r a r o u t i n e t o a c c e s s c o r r e s p o n d i n g e n t r - i e s i n s e v e r a l t a b l e s ; a s s u m e t h a t t h e i n d e x r e g i s t e r i s u s e d a s a p o i n t e r t o s t e p down t h e f i r s t t a b l e . An e n t r y i n t h a t t a b l e may b e a c c e s s e d , u s i n g i n d i r e c t a d d r e s s i n g v i a t h e i n d e x r e g i s t e r . The c o r r e s p o n d i n g e n t r i e s i n t h e o t h e r t a b l e s may b e a c c e s s e d , u s i n g i n d e x e d a d d r e s s i n g , w h e r e t h e v a l u e i n t h e i n s t r u c t i o n d e t e r m i n e s w h i c h t a b l e i s u s e d .
2 . 4 . 4 . Autoincrement/Autodecrement Addressing
U s u a l l y , t h e o n l y h a r d w a r e - i m p l e m e n t e d s t a c k t o be f o u n d i n a m i c r o p r o c e s s o r i s t h e o n e u s e d i n t e r n a l l y t o s a v e s u b r o u t i n e r e t u r n a d d r e s s e s . P r o g r a m m e r s o f t e n r e q u i r e t o u s e a s t a c k f o r o t h e r p u r p o s e s , s u c h a s s a v i n g a d d i t i o n a l v a l u e s when n e s t i n g s u b r o u t i n e s , o r e v a l u a t i n g e x p r e s s - i o n s ( s e e S e c t i o n 2 . 4 . 1 ) . P r o g r a m m e r - a c c e s s i b l e h a r d w a r e s t a c k s a r e r a r e , a n d s e l d o m d e e p e r t h a n 16 l e v e l s . S o f t w a r e - i m p l e m e n t e d s t a c k s a r e t h e r e - f o r e o f t e n e m p l o y e d . An a r e a o f m a i n memory i s u s e d t o h o l d t h e s t a c k e n t r i e s , a n d a r e g i s t e r ( s t a c k p o i n t e r ) i s u s e d t o p o i n t t o t h e t o p - o f -
s t a c k e n t r y . To PUSH an i t e m o n t o t h e s t a c k , t h e s t a c k p o i n t e r i s d e c r e m e n t e d ( o r i n c r e m e n t e d ) , a n d t h e i t e m w r i t t e n t o t h e l o c a t i o n w h i c h i t now a d d r e s s e s . To POP an i t e m o f f t h e s t a c k , r e a d - i n g i s p e r f o r m e d b e f o r e t h e s t a c k p o i n t e r i s i n c r e m e n t e d ( o r d e c r e m e n t e d ) . T h e s t a c k i t e m s a r e s a i d t o b e a c c e s s e d u s i n g a u t o i n o r e m e n t / a u t o - d e c r e m e n t a d d r e s s i n g . I n t h i s p a p e r , t h a t t e r m i s r e s e r v e d f o r t h e p r e d e c r e m e n t / p o s t i n c r e m e n t a n d p r e i n c r e m e n t / p o s t d e c r e m e n t c o m b i n a t i o n s w h i c h a r e r e q u i r e d f o r t r u e s t a c k o p e r a t i o n s .
S e v e r a l v a r i a t i o n s a r e p o s s i b l e : t h e s t a c k may i n c r e a s e o r d e c r e a s e i n memory a d d r e s s f r o m t o p
86 D. ASPINALL, M.H. BARTON, E.L. DAGLESS
t o b o t t o m , and t h e p o i n t e r may p o i n t t o t h e t o p i t e m o r t o t h e n e x t e m p t y s p a c e .
2 . 5 . B i t H a n d l i n g
H i t m a n i p u l a t i o n i s i n v a l u a b l e i n t h e r e a l - t i m e a p p l i c a t i o n s f o r w h i c h m i c r o p r o c e s s o r s a r e m o s t o f t e n u s e d . S h i f t i n s t r u c t i o n s a r e u s e f u l h e r e , e s p e c i a l l y t h e r a r e l y f o u n d v a r i a b l e - l e n g t h s h i f t s w h i c h a l l o w e a s y a c c e s s t o a n y b i t i n , s a y , a v a l - ue r e a d i n f r o m some e x t e r n a l d e v i c e .
2 . 6 . T r a n s f e r o f C o n t r o l
The d i s c u s s i o n so f a r h a s b e e n c o n c e r n e d w i t h o p e r a t i o n a l o r d e r s r a t h e r t h a n c o n t r o l o r d e r s . C o n t r o l o r d e r s may be s u m m a r i z e d as r e l a t i v e and a b s o l u t e J u m p s , r e l a t i v e and a b s o l u t e s u b r o u t i n e c a l l s , and s u b r o u t i n e r e t u r n s , a l l o f w h i c h may be c o n d i t i o n a l o r u n c o n d i t i o n a l .
R e l a t i v e Jumps f a c i l i t a t e t h e w r i t i n g o f r e - l o c a t - a b l e c o d e , w h i l e t h e a b i l i t y t o n e s t s u b r o u t i n e s t o e r e a s o n a b l e d e p t h i s a f e a t u r e w h i c h many p r o g r a m m e r s w o u l d l o o k f o r . T h e s e c o m m e n t s a p p l y as much t o l a r g e r m a c h i n e s a s t h e y do t o m i c r o - processors.
3. ECONOMIC CONSIDERATIONS
The r a p i d l y f a l l i n g c o s t o f m i c r o p r o c e s s o r c h i p s and memory h a s m e a n t t h a t g e n e r a t i n g c o d e i s t h e m a j o r s i n g l e c o s t i n a m i c r o p r o c e s s o r - b a s e d s y s - t e m . N e v e r t h e l e s s , i t c o u l d be a r g u e d t h a t t h e f a l l i n memory c o s t h a s a s i d e e f f e c t w h i c h c o u l d h e l p r e d r e s s t h e b a l a n c e . T h i s i s p t h a t l e s s c a r e n e e d be t a k e n o v e r w r i t i n g c o n c i s e p r o g r a m s ; t h e r e - f o r e l e s s p r o g r a m m e r t i m e i s n e e d e d , and t h e r e i s a l s o t h e p o s s i b i l i t y o f u s i n g a c o m p i l e r t o a l l o w h i g h - l e v e l p r o g r a m m i n g .
In many cases, the number of systems to be pro-
duced would not be large enough to Justify the use of a compiler. In any case, work at machine
level is almost always necessary when commission- ing the finished system, and so a little care over
the choice of microprocessor can save a great deal
of effort st production time.
4. SCHEMES TO AID THE COMPARISON OF INSTRUCTION SETS
The m a i n p r o b l e m w i t h c o m p a r i n g m i c r o p r o c e s s o r i n s t r u c t i o n s e t s i s t h e l a c k o f s t a n d a r d i s a t i o n i n t h e way t h a t m a n u f a c t u r e r s d e s c r i b e t h e i r d e v - i c e s . T e r m s s u c h a s ' i m m e d i a t e a d d r e s s i n g ' , ' i n d i r e c t a d d r e s s i n g ' and ' a u t o - i n c r e m e n t / a u t o - d e c r e m e n t ' h a v e d i f f e r e n t m e a n i n g s f o r d i f f e r e n t m a n u f a c t u r e r s . T h r e e p r e v i o u s l y p r o p o s e d s c h e m e s w h i c h m i g h t be u s e d t o h e l p i n t h e c o m p a r i s o n o f i n s t r u c t i o n s e t s a r e d i s c u s s e d h e r e .
The f i r s t was p u t f o r w a r d i n 1970 by B e l l and N e w e l l [ 1 ] , and i s known as t h e I n s t r u c t i o n S e t P r o c e s s o r ( I S P ) l a n g u a g e . I t p r o v i d e s a s t a n - d a r d n o t a t i o n f o r r e p r e s e n t i n g e x p l i c i t l y t h e r e g i s t e r l a y o u t , memory s p a c e , and m a c h i n e c o d e
structure of any processor already in existence
or likely to be designed in the foreseeable future. I SP is primarily a hardware description language; it describes the processor's hardware first, and then defines the order code in terms of operations
between hardware elements.
The second is the 'mnemo-nics' system, proposed bY Nicoud [4,5] in 1975; it is less general than
I S P , b e i n g a n g l e d s p e c i f i c i a l l y t o w a r d s m i c r o - p r o c e s s o r s . Th e ' m n e m o - n i c s ' s y s t e m e x p r e s s e s a g i v e n m i c r o p r o c e s s o r ' s i n s t r u c t i o n s e t i n t e r m s o f a s t a n d a r d a s s e m b l y l a n g u a g e . F o r e a c h o f t h e s t a n d a r d m n e m o n i c s , t h e p e r m i t t e d o p e r a n d s a r e l i s t e d , t o g e t h e r w i t h t h e i r r e p r e s e n t a t i o n i n m a c h i n e c o d e . The h a r d w a r e s t r u c t u r e o f t h e p r o - c e s s o r c a n be d e d u c e d by i n s p e c t i o n o f t h e p e r m i t - t e d o p e r a n d s . A u s e f u l b y - p r o d u c t o f t h i s m e t h o d i s t h a t i t l e a d s t o t h e c o n c e p t o f a u n i v e r s a l a s s e m b l e r , c a p a b l e o f a s s e m b l i n g f r o m ' m n e m o - n i c s ' s o u r c e i n t o m a c h i n e c o d e f o r an y m i c r o p r o c e s s o r . T h i s w o u l d g r e a t l y f a c i l i t a t e t h e r u n n i n g o f b e n c h m a r k s t o c o m p a r e s e v e r a l m i c r o p r o c e s s o r s a c c u r a t e l y .
The t h i r d s c h e m e i s a g r a p h i c a l m e t h o d p u t f o r w a r d by J . N i c h o l s [ 3 ] i n 1 9 7 5 . The i n s t r u c t i o n s o f t h e p r o c e s s o r a r e p l o t t e d on a m a t r i x s h o w i n g s o u r c e o p e r a n d s a l o n g one a x i s and o p e r a t i o n / d e s t i n a t i o n o p e r a n d c o m b i n a t i o n s a l o n g t h e o t h e r . Th e r e s o l u - t i o n a l o n g t h e a x e s i s s u c h t h a t a c t u a l r e g i s t e r n ames a r e g i v e n ; t h e a p p r o p r i a t e a s s e m b l e r mnemon ic i s shown i n e a c h s q u a r e on t h e m a t r i x c o r r e s p o n d i n g t o a v a l i d o p e r a t i o n .
The N i c h o l s m a t r i x p r o v i d e s a c o m p a c t summary o f an i n s t r u c t i o n s e t f o r a p r o g r a m m e r w o r k i n g w i t h an a s s e m b l e r . H o w e v e r , s i n c e t h e l a y o u t o f t h e a x e s i s d i f f e r e n t f o r e a c h p r o c e s s o r , t h e m e t h o d d o e s n o t a l l o w e a s y c o m p a r i s o n o f a n u m b e r o f i n s t r u c t i o n s e t s .
I S P , ' m n e m o - n i c s ' and t h e N i c h o l s m a t r i x ~ a l l p r o v i d e a l a r g e amoun t o f i n f o r m a t i o n a b o u t t h e m i c r o p r o c e s s o r ' s i n s t r u c t i o n s e t . T h i s i s t h e l e v e l o f d e t a i l w h i c h w o u l d be r e q u i r e d by a d e s i g n e r who h a s n a r r o w e d t h e c h o i c e down t o , s a y , two o r t h r e e p r o c e s s o r s . To u s e an y one o f t h e s e m e t h o d s t o h e l p a t t h e i n i t i a l s e l e c t i o n s t a g e w o u l d be w a s t e f u l o f t i m e . What i s r e q u i r e d i s a s y s t e m w h i c h p r e s e n t s o n l y t h e i n f o r m a t i o n r e q u i r - e d a t t h a t s t a g e , p r e f e r a b l y i n g r a p h i c a l f o r m , and i s t h e r e f o r e q u i c k t o u s e .
5 . TOWARDS A GRAPHICAL REPRESENTATION OF INSTRUCTION SET
5 . 1 . O p e r a t i o n a l O r d e r s
An o p e r a t i o n a l o r d e r i s o n e w h i c h i s n o t c o n c e r n e d w i t h t r a n s f e r o f p r o g r a m c o n t r o l . Any o p e r a t i o n a l o r d e r l i k e l y t o be e n c o u n t e r e d i n m i c r o p r o c e s s o r s c a n be e x p r e s s e d i n one o f t h e f o l l o w i n g f o r m s :
i ) O P 1 ÷ O P l . u
i i ) O P l ÷ O P 2 . u
i i i ) O P l ÷ O P l . b . O P 2
COMPARISON OF MICROPROCESSORS : A GRAPHICAL APPROACH 87
where .u, .b, are unary and binary operators, and
0 P i, O P 2 are operands.
I t f o l l o w s t h a t a n y o f t h e s e o r d e r s may b e r e p r e -
s e n t e d by e n t r i e s on a 2 - d i m e n s i o n a l g r i d w i t h o p e r a t o r s a l o n g o n e a x i s ( v e r t i c a l , s a y ) , a n d o p e r a n d s ( O P l o n l y o r O P 1 / 0 P 2) a l o n g t h e o t h e r a x i s ( h o r i z o n t a l ) . C e r t a i n a r e a s o f t h e g r i d , c o r r e s p o n d i n g t o a c o m b i n a t i o n o f ' O P l o n l y ' operand and binary operator, are logically imposs-
ible, and may be denoted by a cross in the appro-
priate square°
It must be remembered that, to ease the compari-
son of different devices, the layout of the axes
should be independent of the microprocessor being
represented~
5.2. 'Operators' Axis
The 'operators' axis presents few problems; it is
simple to choose a list of operators which covers
all those likely to be encountered. Certain rat-
ionalizations have to be performed; for example)
no distinction is made between MOVE, LOAD, STORE,
PUSH, or POP operators; 'rotate' orders are
categorized as ROTATE or ROTATE VARIABLE LENGTH,
ignoring distinctions such as 'With Carry' or
'Without Carry'~
The division of operators into 'binary' and 'unary )
classes is trivial except in the case of the MOVE
and EXCHANGE operators° These are a special type
of unary operator for which statement (i) above is
meaningless° Therefore any square corresponding
to a combination of MOVE or EXCHANGE operators
and 'OP i only' operand is also invalid°
5 . 3 . _ ~ e r a n d s ' A x i s
D e c i d i n g on a l a y o u t f o r t h e ' o p e r a n d s ' a x i s i s r a t h e r m o r e c o m p l i c a t e d . O p e r a n d s t e n d n o t t o b e a s s t a n d a r d i z e d a s o p e r a t o r s ; t h e r e i s c o n s i d e r - a b l e v a r i a t i o n i n r e g i s t e r n u m b e r s and w i d t h s , memory a d d r e s s i n g m o d e s , and s t a c k f a c i l i t i e s . To a s s i s t w i t h t h e g r o u p i n g , i t i s u s e f u l t o l o o k i n m o r e d e t a i l a t t h e o p e r a n d s i n v o l v e d , a n d a t how t h e y a r e s e l e c t e d by t h e i n s t r u c t i o n w o r d . T a b l e 1 s h o w s t h e m a i n c l a s s e s o f o p e r a n d .
A l l o w i n g a l l p o s s i b l e c o m b i n a t i o n s , t h e n u m b e r o f ' O P 1 / O P 2 ' c o l u m n s t o b e a c c o m m o d a t e d by t h e h o r i z o n t a l a x i s w o u l d be :
7~ (OPl ~ OP2) 2~ ° 5~
+ 6 ( O P 1 = O , 2)
(immediate/immediate is invalid, as writing to
the current instruction is not encouraged)
=27
Note that combinations 1/2 (say) and 2/1 share
one column. Some method is needed to indicate
which ordering is meant. Splitting each grid
square into an upper and a lower section achieves
this. An entry in the upper half would mean that
O P I/O P 2 are as shown by the column heading; an
entry in the lower half would mean that O P I/OP2
are reversed (see Fig.l).
The number of 'O P 1 only' columns = 6; (immediate
mode operands are invalid here). The total of
thirty-three columns can be accommodated quite
easily across the page.
Ref Name
i m m e d i a t e
r e g i s t e r ( o n - c h i p )
memory
indirect
indexed
autoincrement
and
autodecrement
hardware stack
Symbol
F
G
M
Mi
Mv
Ma
ST
Description
f
G or f/G
M or f/M
G/M or M/M'or F/G/M or F/M/M' or G/M/M' or G/G'/M
f + G/M or f + G/M/M' or G/M + f/M' or f + (f'/G)JM
or f + (f'/G)/M/M' or f'/G/M + f/M'
G~/M or G~/M/M' or (f/G):/M or (f/G):/M/M'
s t
Key t o d e s c r i p t i o n : f, fw
G,G'
M,M'
st +
/
@'/
T a b l e 1
a r e f i e l d s i n t h e i n s t r u c t i o n ;
a r e o n - c h i p r e g i s t e r s ;
a r e l o c a t i o n s i n t h e m a i n me mory ;
i s an i t e m on a h a r d w a r e s t a c k ;
h a s i t s u s u a l m e a n i n g ;
m e a n s ' s e l e c t s ' ; ( l e s s b i n d i n g t h a n ' + ' )
m e a n s ' s e l e c t , t h e n i n c r e m e n t ( d e c r e m e n t ) ' when u s e d a s a s o u r c e o p e r a n d ; ' d e c r e m e n t ( i n c r e m e n t ) , t h e n s e l e c t ' when u s e d a s a d e s t i n a t i o n o p e r a n d , i . e . a s o f t w a r e s t a c k
: Operan d Addressin~ Mechanisms
88 D. ASPINALL, M.H. BARTON, E.L. NAGLESS
5o3.1o Possibility of Increasing Number o~Operand Types
E v e n w i t h o p e r a n d s g r o u p e d i n t o o n l y s e v e n c a t e - g o r i e s , t h e c h a r t s t i l l g i v e s a r e a s o n a b l e amount o f i n f o r m a t i o n a b o u t t h e f e a t u r e s d i s c u s s e d a b o v e , i . e . p r e s e n c e o f h a r d w a r e s t a c k , i n d e x i n g , a n d a u t o - i n c r e m e n t / a u t o - d e c r e m e n t o However, no
i n f o r m a t i o n i s g i v e n a b o u t t h e n u m b e r o f g e n e r a l r e g i s t e r s a v a i l a b l e f o r u s e i n d i r e c t r e g i s t e r mode , f o r s e l e c t i n g memory i n i n d i r e c t and a u t o m o d e s , o r f o r i n d e x i n g i n i n d e x e d mode° R e f e r r - i n g b a c k t o t h e l i s t o f o p e r a n d t y p e s , i t c a n be s e e n t h a t c e r t a i n g r o u p s s u b d i v i d e f u r t h e r q u i t e n a t u r a l l y , a c c o r d i n g t o t h e s e c r i t e r i a °
F o r e x a m p l e , i n g r o u p 1 ( T a b l e 1 ) , ' f / G ' m e a n s t h a t a f i e l d i n t h e i n s t r u c t i o n w o r d i s u s e d t o s e l e c t G, a n d s o t h e r e m u s t b e m o r e t h a n o n e G a v a i l a b l e f o r t h e o r d e r . ' G ' m e a n s t h a t t h e r e i s no c h o i c e o f r e g i s t e r ; i t i s i m p l i e d ° G r o u p s 2, 3 , 4 , a n d 5 c a n b e s p l i t s i m i l a r l y . T h e number o f o p e r a n d t y p e s f o l l o w i n g s u c h a s u b d i v i s i o n w o u l d b e 12 , a n d so t h e t o t a l n u m b e r o f c o l u m n s r e q u i r e d w o u l d be :
12~ +11 +ii = 88 2! 10!
( T h e w i d t h o f an o p e r a t i o n i s d e f i n e d a s t h e s m a l l e r o f t h e w i d t h s o f O P 1 and O P 2 ) . S p l i t - t i n g e a c h s q u a r e i n t o t h r e e s e c t i o n s f r o m l e f t t o r i g h t a l l o w s t h i s w i d t h i n f o r m a t i o n t o b e shown on t h e g r i d ° T h e c e n t r e o f t h e t h r e e s e c t i o n s i n t h e s q u a r e c o r r e s p o n d s t o an o p e r a t i o n w i d t h e q u a l t o t h e p r o c e s s o r w i d t h ° The l e f t a n d r i g h t s e c - t i o n s c o r r e s p o n d t o o p e r a t i o n w i d t h s l e s s t h a n and g r e a t e r t h a n t h e p r o c e s s o r w i d t h , r e s p e c t i v e l y ( s e e F i g . l ) .
5°3.3° Arrangement of Columns
The a r r a n g e m e n t o f c o l u m n s a c r o s s t h e p a g e h a s n o t y e t b e e n d i s c u s s e d . I d e a l l y , t h e p a t t e r n o f f i l l e d - i n s q u a r e s s h o u l d h a v e a u s e f u l m e a n i n g , e v e n b e f o r e t h e c o l u m n h e a d i n g s a r e r e a d . ' N u m b e r o f a d d r e s s e s p e r i n s t r u c t i o n ' i s a s u i t a b l e p a r a - m e t e r by w h i c h t o g r o u p t h e c o l u m n s , f o r t h e r e a s o n s o u t l i n e d e a r l i e r .
5 . 4 = P r o c e d u r e f o r F i l l i n g - i n t h e C h a r t
T h e r e a r e two a p p r o a c h e s t o f i l l i n g - i n t h e c h a r t ° The f i r s t a p p r o a c h w o r k s p u r e l y f r o m a t e x t u a l d e s c r i p t i o n o f t h e i n s t r u c t i o n s e t , and r e q u i r e s no i n f o r m a t i o n a b o u t t h e l a y o u t o f f i e l d s i n t h e m a c h i n e c o d e .
Certain columns could be omitted if they were
found to be permanently empty. Even so, the num-
ber of columns would be too large to fit easily
onto a page.
T h e m e t h o d c u r r e n t l y i n u s e i s a c o m p r o m i s e ; g r o u p 1 a l o n e h a s b e e n s p l i t ( i n t o G i m p l i e d and Gf ) , and ' S T u n a r y ' h a s b e e n o m i t t e d , g i v i n g a c o l u m n c o u n t o f 4 1 ,
T h e s e c o n d a p p r o a c h a i m s t o m a k e t h e c h a r t r e f l e c t t h e s t r u c t u r e o f t h e m a c h i n e c o d e .
C o n s i d e r t h e f o l l o w i n g t h r e e i n s t r u c t i o n s , w h e r e A, B, C a r e o n - c h i p r e g i s t e r s :
A ÷ A (m/c code 01010010)
B + B (m/c code Iii01011)
C ÷ C (m/c code 01111001)
operation width
~ OP1 and OP2 as shown by column heading
OP1 and OP2 reversed
< ~ > processor width
S e p a r a t e l y , e a c h o r d e r i s o f t h e O - a d d r e s s t y p e (G ÷ G . u ) , b u t u n d e r t h e f i r s t a p p r o a c h t h e y w o u l d b e m e r g e d t o f o r m a compound o r d e r :
11 B ÷ B
C C
w h i c h i s o f t h e 1 - a d d r e s s t y p e ( ( f / G ) + ( f / G ) . u ) .
The s e c o n d a p p r o a c h w o u l d n o t m e r g e t h e two o r d e r s a s no f i e l d c a n be i d e n t i f i e d i n t h e m a c h i n e c o d e a s c o r r e s p o n d i n g t o f , t h e g r o u p o f b i t s w h i c h s e l e c t s r e g i s t e r A, B o r Co
E i ~ . l : Key t o E n t r i e s w i t h i n a G r i d S q u a r e .
5.3.2° Indicating O~eration Width
So f a r , o p e r a t i o n s o f d i f f e r e n t w i d t h s h a v e b e e n l u m p e d t o g e t h e r ° F o r e x a m p l e , an o p e r a t i o n a d d - i n g two 1 6 - b i t r e g i s t e r s , o r two 8 - b i t r e g i s t e r s , o r a d d i n g a C a r r y b i t i n t o an 8 - b i t r e g i s t e r , w o u l d a l l be i n d i c a t e d by t h e s a m e s q u a r e .
I t i s f e l t t h a t t h e f i r s t m e t h o d i s p r e f e r a b l e a s m o s t u s e r s a r e i n t e r e s t e d i n w h a t r a n g e o f o p e r a t i o n s c a n be p e r f o r m e d , r e g a r d l e s s o f t h e l a y o u t o f t h e m a c h i n e c o d e r e q u i r e d ° A n y o n e c o n - c e r n e d w i t h d e t a i l s o f t h e m a c h i n e c o d e ( a s s e m b l e r w r i t e r s , f o r e x a m p l e ) , w o u l d be b e t t e r s e r v e d by systems such as I S P or mnemo-nics.
5 . 5 . C o n t r o l O r d e r s
C o n t r o l o r d e r s r e q u i r e a s e p a r a t e g r i d , f o r w h i c h t h e r e q u i r e m e n t s a r e m o r e s i m p l e . The o r d e r s
COMPARISON OF MICROPROCESSORS : A GRAPHICAL APPROACH 89
c o n s i s t o f j u m p s a n d s u b r o u t i n e c a l l s , w h i c h c a n b e c o n d i t i o n a l o r u n c o n d i t i o n a l , a n d r e l a t i v e o r a b s o l u t e ; a n d s u b r o u t i n e r e t u r n s , w h i c h c a n b e c o n d i t i o n a l o r u n c o n d i t i o n a l .
( i ) o p e r a n d d e f i n i t i o n s
( i i ) o r d e r d e f i n i t i o n s
T h e r e t u r n s a r e s p e c i a l c a s e s i n t h a t t h e y h a v e n o o p e r a n d f i e l d , a n d n e e d o n l y b e s h o w n o n t h e g r i d a s p r e s e n t , o r n o t . The o t h e r o r d e r s may b e r e p r e s e n t e d a s :
P C ~ P C + o p e r a n d ( r e l a t i v e )
P C ~ o p e r a n d ( a b s o l u t e )
I n t h e r e l a t i v e c a s e , t h e o p e r a n d f i e l d may r e p - r e s e n t a p o s i t i v e o r n e g a t i v e v a l u e . N o t e t h a t s u b r o u t i n e c a l l s i m p l y t h a t P C i s a l s o s a v e d o n a s t a c k . The d e p t h o f t h i s s h o u l d b e s h o w n o n t h e c h a r t .
T h e y a x i s o f t h e g r i d , t h e n , r e p r e s e n t s t h e f o l l o w i n g o p e r a t o r s :
{ j ump } f c o n d i t i o n a l t . { r e l a t i v e }
c a l l ~ u n c o n d i t i o n a l ~ a b s o l u t e
/ c o n d i t i o n a l ~
r e t u r n " [ u n c o n d i t i o n a l ]
T h e x a x i s r e p r e s e n t s t h e o p e r a n d t y p e s . T h e number of columns required is, of course, much less than for the other grid, as combinations of
operand types need not he represented° At least
six columns are needed - one for each of the groups 0 to 5 above; some of these groups may
be subdivided, as described earlier, in which
case II columns would be required.
In the case of control orders, the 'width' of the operation shows the amount of choice allowed for
jump destination° It is therefore useful to
split each column into three sections, from left
to right, as for the other grid, to indicate width of operation.
6. PRODUCTION OF GRIDS USING A BASIC PROGRAM
F i l l i n g - i n g r i d s i s a t e d i o u s t a s k , a n d a n y a u t o - m a t i o n w h i c h c a n b e p r o v i d e d i s w e l c o m e . A p r o g r a m h a s b e e n w r i t t e n i n BASIC t o r u n o n a P D P - 1 1 , t o h e l p i n t h i s r e s p e c t . G i v e n a s u m m a r y o f a n i n s t r u c t i o n s e t , i t p r o d u c e s t h e c o r r e s p o n d i n g c h a r t o n a T e k t r o n i x 4 0 1 0 - 1 VDU. H a r d c o p i e s c a n be made if required°
The translation of the manufacturer's information into a form readable by the program has to be performed manually° In writing the program, the
aim was to make this stage as simple as possible,
and also to ensure that different people perform- ing the same translation would produce identical charts.
F i g u r e 2 s h o w s t h e p r o g r a m i n p u t n e c e s s a r y t o p r o d u c e t h e INTEL 8 0 0 8 ' o p e r a t i o n a l o r d e r s ' c h a r t s h o w n i n F i g ° 3 . The t w o m a i n e l e m e n t s a r e :
#NAME
INTEL 8008
~WIDTH
8
#0PERAND5
00008 N
10008 Q/G.A, B, C, D.E,H,L
10108 Q/G. B, C, D, E,H,L
3 0 0 0 8 G.HL/M. 0:64K-I 70008 G.A
#MACROS
MOO 100 300 000 t O O0 Ol 0 3 04 08 1 0 11 #0RDEhS 0 1 3 1 0 0 1 0 0 1 1 3 1 0 0 3 0 0 2 13300100 3 13100000 4 13300000 5 15101 6 16101 7 1 7 7 0 0 8 FOV00M00
1 2
F i g o 2 o T y p i c a l I n p u t t o BASIC P r o g r a m .
E a c h o p e r a n d d e f i n i t i o n c o n s i s t s o f a n u m e r i c a l o p e r a n d i d e n t i f i e r ( c o n t a i n i n g o p e r a n d t y p e a n d s e r i a l n u m b e r ) , a f i e l d s h o w i n g t h e o p e r a n d w i d t h a n d a s y m b o l i c d e s c r i p t i o n o f t h e a d d r e s s i n g s t r u c t u r e w h i c h s e l e c t s t h e o p e r a n d ( c o g . Q / G o A , B , C ) . T h e p r o g r a m i g n o r e s t h i s l a s t f i e l d . F o r e x a m p l e , t h e l i n e
1 0 1 0 8 Q / G o B , C , D , E , H , L
w o u l d b e i n t e r p r e t e d a s :
o p e r a n d t y p e : 1 ( w h i c h m e a n s " f / G " ) ] o p e r a n d s e r i a l n u m b e r : 0 1 ~ d e n t i f i e r
w i d t h : 0 8 b i t s
s y m b o l i c r e p r e s e n t a t i o n : Q / G . B , C , D , E , H j L
( h e r e , ' Q ' m e a n s a f i e l d i n t h e f i r s t b y t e o f a n i n s t r u c t i o n ) .
E a c h o r d e r d e f i n i t i o n c o n s i s t s o f a r e f e r e n c e n u m b e r f o l l o w e d b y a t w o - o r t h r e e - f i e l d c o d e . T h e f i e l d s i n t h e c o d e a r e :
a 2 - d i g i t o p e r a t o r c o d e ;
o n e o r t w o 3 - d i g i t o p e r a n d i d e n t i f i e r s .
F o r e x a m p l e , t h e l i n e
2 13300100
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x > < x x X I>< X > ~ X x X I>< ~YX x X b,< X~× × X I>< ×~ x X I B
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I I I F I G o 3 . ' O p e r a t i o n a l O r d e r s ' C h a r t s f o r I N T E L 8 0 0 8 a n d D E C L S I - 1 1 .
COMPARISON OF MICROPROCESSORS : A GRAPHICAL APPROACH 91
w o u l d b e i n t e r p r e t e d a s :
r e f e r e n c e n u m b e r : 2
o p e r a t o r c o d e : 13 ( w h i c h m e a n s "MOVE")
o p e r a n d 1 i d e n t i f i e r : 3 0 0
o p e r a n d 2 i d e n t i f i e r : 1 0 0
6° F ° H o S u m n e r . The Application of Paging, Seg-
mentation and Virtual Memory, in:
Infotech State of the Art Report 2,
Giant Computers, (Infotech, U.Ko,
1971) 255-274.
The most powerful property of the system is its
ability to accept macros in any field within an order definitions The input data may contain
definitions of operator macros and operand macros°
This facility is particularly valuable where the
microprocessor being represented has a well struc- tured instruction set, ioeo, one which can be
represented in a few lines of the form (operators)
combined with (operands) combined with (operands)o The program expands the macros before producing
the grid. The same pattern will be produced
whether macros are used or not; they merely
provide a means of saving time for the person doing the translation~
Figure 3 shows 'operational orders' charts for
the INTEL 8008 and the DEC LSI-IIo (To improve
clarity for publication, they have been redrawn from the program output with the number of
operators reduced)°
7° CONCLUSION
T h e g r a p h i c a l m e t h o d o u t l i n e d i n t h i s p a p e r a l l o w s a q u i c k c o m p a r i s o n o f s e v e r a l m i c r o p r o c e s s o r s t o b e m a d e a t a g e n e r a l l e v e l ; t h e B A S I C p r o g r a m r e d u c e s t h e t i m e n e e d e d t o t r a n s f e r i n f o r m a t i o n f r o m t h e m a n u f a c t u r e r ' s h a n d b o o k o n t o t h e c h a r t .
Future enhancements may include the addition of information on instruction timing,input/output
facilities, and the physical characteristics of a
device°
8~ REFERENCES
Io CoG.Bell et al° A New Architecture for Mini- computers - The DEC PDP-II, AFIPS
SJCC (1970)657-675o
2. C.GoBell & A.Newello Computer Structures :
Readings and Examples, (McGraw-Hill, New York, 1971).
3. J°Nichols° The Source-Destination Matrix for
Instruction Set Presentation, Digest of Papers~ IEEE Compcon 75 Spring
( 1 9 7 5 ) 6 1 - 6 3 ~
4. J.DoNicoud° Common Instruction Mnemonics for
Microprocessors, Euromicro Newslette~ i, (1975) 3, 22-29°
5. J.DoNicoud° A Common Microprocessor Assembly
Language, in: M°Sami, J.Wilmink, R.Zaks (eds.), Second Symposium on Micro~rocessing and Microprogramming,
(North Holland, Amsterdam, 1976), 213-22Oo
