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IKI10230Pengantar Organisasi Komputer
Bab 7: Control Unit
28 Mei 2003
Bobby Nazief ([email protected])Qonita Shahab ([email protected])
bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/
Sumber:1. Hamacher. Computer Organization, ed-5.2. Materi kuliah CS152/1997, UCB.
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Pengendalian Eksekusi Instruksi:
Hardwired Control
3
Prosesor: Control & Datapath
Processor (active)
Computer
Control(“brain”)
Datapath(“brawn”)
Memory(passive)
(where programs, data live whenrunning)
Devices
Input
Output
4
Review: Organisasi Prosesor (Single-bus)
Y
Z
MDR
MAR
PC
TEMP
R(n-1)
R0
IR
InstructionDecoder
ALUCarry-in
Add
Sub
XOR
Address lines
Data lines
Control lines
Memory bus
ALU control lines
Control Unit
DatapathUnit
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Interaksi Control Datapath
STEP CONTROL SIGNALS
1. PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
2. Zout, PCin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, Add, Zin
7. Zout, R1in, End
ControlInstruction
Datapath
IR
Con
ditio
ns
ControlSignalsPCout
MARin ADD
Riin
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Organisasi Unit Pengendali
Decoder/Encoder
Control StepCounter
Clock
IR
StatusFlags
ConditionCodes
CLK
Control Signals
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Pemisahan Decoder & Encoder
Encoder
Control StepCounter
Clock
IR
StatusFlags
ConditionCodes
InstructionDecoder
Step Decoder
LDI
CLK
T1 T2 Tn
Control Signals
LD
INSn
Run End
Reset
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Contoh Struktur Encoder untuk sinyal Zin
° Fungsi Logika:
Zin = T1 + T6 ADD + T5 BR + …
° Zin akan terjadi pada:
• T1: untuk setiap instruksi (instruksi berikut: PC+1)
• T5: untuk instruksi ADD
• T6: untuk instruksi BR
ADD BR
T5T6
T1
Zin
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Interaksi Memori [Control,Datapath]
DataOut
Clk
5
Rw Ra Rb
Registers
Rd
AL
U
Clk
Data In
DataAddress
IdealData
Memory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
32
323232
A
B
Nex
t A
dd
ress
Control
Datapath
Control Signals Conditions
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Pengendalian Eksekusi Instruksi:
Microprogrammed Control
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Microprogramming
° Control is the hard part of processor design° Datapath is fairly regular and well-organized
° Memory is highly regular
° Control is irregular and global
Microprogramming:
-- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations
Microarchitecture:
-- Logical structure and functional capabilities of the hardware as seen by the microprogrammer
Historical Note:
IBM 360 Series first to distinguish between architecture & organizationSame instruction set across wide range of implementations, each with different cost/performance
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Microinstructions STEP CONTROL SIGNALS
1. PCout, MARin, Read, Clear Y, Carry-in to ALU, Add, Zin
2. Zout, PCin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, Add, Zin
7. Zout, R1in, End
0 0 1 1 0 0 0 0 0 1 0 1 1 1 1 0 00 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 01 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 00 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 00 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 00 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1
IRin
PC
in
PC
out
MA
Rin
MD
Rou
t
Yin
R1 in
R1 ou
t
R3 ou
t
Zin
Zou
t
Cle
ar Y
Car
ry-i
n
Ad
d
Rea
d
WM
FC
En
d
1
2
3
4
5
6
7
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Organisasi Microprogrammed Control Unit
0 0 1 1 0 0 0 0 0 1 0 1 1 1 1 0 00 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 01 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 00 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 00 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 00 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1
IRin
PC
in
PC
out
MA
Rin
MD
Rou
t
Yin
R1 in
R1 ou
t
R3 ou
t1
2
3
4
5
6
7
IRStartingAddress
Generator
Clock μPC
ControlStore Control
Word
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Organisasi μProgrammed Control Unit: Branching
IRStartingAddress
Generator
Clock μPC
ControlStore Control
Word
Status Flags
Condition Codes
Addr. Microinstruction
0 PCout, MARin, Read, Clear Y, Carry-in to ALU, Add, Zin
1 Zout, PCin, WMFC
2 MDRout, IRin
3 Branch to starting addr. of appropriate μroutine
…………………………………………………………………………….
25 PCout, Yin, if N=0 then branch to μinstruction 0
26 Offset-field-of-IRout, Add, Zin
27 Zout, R1in, End
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Encoding of Microinstruction
0000: No transfer
0001: PCout
0010: MDRout
0011: Zout
0100: R0out
0101: R1out
000: No transfer
001: PCin
010: IRin
011: Zin
100: R0in
101: R1in
0000: ADD
0001: SUB
.
.
.
1111: XOR
000: No transfer
001: MARin
010: MDRin
011: TEMPin
100: Yin
F4F2F1 F3
(4 bits)(3 bits)(4 bits) (3 bits)
° Most signals are not needed simultaneously
° Many are mutually exclusive:• ALU: 1 function at a time
• Data source is unique
° Organization:• Vertical Organization (Highly Encoded μInstruction)
• Horizontal Organization (otherwise)
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Microprogram Sequencing: Branching Implementation
° 1 Machine Instruction 1 Set of μInstructions• large total number of μInstruction
• large Control Store
° Many Addressing Modes many instruction combinations
• results in many duplications of common parts
° If the common parts are to be shared many branches
• results in longer execution time
Need efficient branching techniqe Bit-ORing
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Microprogram Sequencing (1/2): Add src,Rdst
MAR [PC]; Read; Z [PC]+1
PC [Z]; WMFC
IR [MDR]
Branch[InstDec,OR]
MAR [PC]; Read;Z [PC]+1
Z [Rsrc] - 4 MAR [PC]; Read;Z [PC]+1
MAR [Rsrc];Read
PC [Z]; WMFC MAR, Rsrc [Z];Read
Z [Rsrc] Branch[171]; WMFC
Start
000
001
002
003
111141161 121
112142162 122
Indexed Autodecrement Autoincrement Register indirect
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Microprogram Sequencing (2/2): Add src,Rdst
Branch[170,OR];WMFC
Branch[170,OR];WMFC
Branch[170,OR];WMFC
Branch[171];WMFC
End
112143166 123Indexed Autodecrement Autoincrement Register indirect
MAR [MDR]; Read; WMFC
170
Y [MDR]
171
Z [Y] + [Rdst]
172
Rdst [Z]
173
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Branching in Microinstruction: Add (Rsrc)+,Rdst
Rdst0 1 0OP code Rsrc
11 10 8 7 4 3 0
Addr. Microinstruction
000 PCout, MARin, Read, Clear Y, Set carry-in, Add, Zin
001 Zout, PCin, WMFC
002 MDRout, IRin
003 μBranch {μPC 101; μPC5,4 [IR10,9]; μPC3 [IR10].[IR9].[IR8]}
121 Rsrcout, MARin, Read, Clear Y, Set carry-in, Add, Zin
122 Zout, Rsrcin
123 μBranch {μPC 170; μPC0 [IR8]}, WMFC
170 MDRout, MARin, Read, WMFC
171 MDRout, Yin
172 Rdstout, Add, Zin
173 Zout, Rdstin, End
ADD
IR10,9 = 01 (autoincrement)
IR8 = 0 (direct)
Mode
Bit ORing
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Microinstruction Sequencing: Organization
μAR
ControlStore
μIR
Status Flags Condition Codes
IR
Decoding Circuits
Next Address
μInstruction Decoder
Control Signals
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Encoding of Microinstruction w/ Next Address
000: No transfer
001: PCout
010: MDRout
011: Zout
100: Rsrcout
101: Rdstout
000: No transfer
001: PCin
010: IRin
011: Zin
100: Rsrcin
101: Rdstin
0000: ADD
0001: SUB
.
.
1111: XOR
000: No transfer
001: MARin
010: MDRin
011: TEMPin
100: Yin
F3F1F0 F2
(3 bits)(3 bits)(8 bits) (3 bits)
Address of nextmicroinstruction
F4 F9
(1 bit)
. . .
(4 bits)
F8
(1 bit)
0: NextAdrs
1: InstDec
0: No action
1: ORmode
F10
(1 bit)
0: No action
1: ORindsrc
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Content of μStore
F0 F1 F2 F3 F4 F5 F6
F7
F8
F9
F10
0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 00 0 2 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 00 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 01 2 2 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 01 7 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 11 7 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 01 7 2 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 01 7 3 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000001002003121122170171172173
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/Etc
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“Macroinstruction” Interpretation
MainMemory
executionunit
controlmemory
CPU
ADDSUBAND
DATA
.
.
.
User program plus Data
this can change!
AND microsequence
e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s)
one of these ismapped into oneof these
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Control: Hardware vs. Microprogrammed
° Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique.
Initial Representation Finite State Diagram Microprogram
Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs
Logic Representation Logic Equations Truth Tables
Implementation Technique PLA ROM“hardwired control” “microprogrammed control”
