enabling risc-v development with qemu

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© 2019 Western Digital Corporation or its affiliates. All rights reserved. 7/1/2019 Enabling RISC-V Development with QEMU Alistair Francis <[email protected]> RISC-V Workshop - ETH 12 th of June 2019

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© 2019 Western Digital Corporation or its affiliates. All rights reserved. 7/1/2019

Enabling RISC-V Development with QEMU

Alistair Francis <[email protected]>

RISC-V Workshop - ETH

12th of June 2019

7/1/2019©2019 Western Digital Corporation or its affiliates. All rights reserved. 2

What is QEMU?

• QEMU is a very quick open source (mostly GPLv2) emulator

• It is not cycle accurate, but it is functionally accurate

• It uses the Tiny Code Generator (TCG) to translate different guest architecture instructions to host executable code– Supports full system (softMMU) emulation

– Also supports just Linux/BSD user space translation

• It works similarly to GCC with separate host and target support– Currently mainline has RISC-V guest and host

support

It’s FREE!

Benoît Canet

7/1/2019©2019 Western Digital Corporation or its affiliates. All rights reserved. 3

Basics of Tiny Code Generator (TCG)

• TCG began as a backend for a C compiler

• TCG can convert TCG ops to target (host) instructions – It also performs some optimisations and liveness analysis to improve performance

• TCG will combine blocks of guest code into a TB blocks– The end of a block occurs when a branch/jump instruction is encountered

– Running QEMU with single step turned on results in every TB block being a single guest instruction

• TCG caches each instruction so that future decoding is extremely fast– Fast path memory actions don’t need to have addresses recalculated for example

• TCG natively supports these targets (hosts)– AArch64, ARMv7, x86, AMD64, MIPS, PPC, PPC64, RISC-V, S390 and Sparc

• TCG supports even more guest architectures

7/1/2019©2019 Western Digital Corporation or its affiliates. All rights reserved. 4

What do we have in mainline today?

• Support for running 32-bit and 64-bit RISC-V operating systems and Linux user space applications on all supported QEMU platforms

• Support for running 32-bit and 64-bit operating systems and Linux user space applications of all supported guest QEMU architectures on 64-bit RISC-V platforms

• Support for the QEMU virt machine, HiFive Unleased, HiFive One and Spike machines

• ISA extensions can be enabled/disabled via command line (pending pull request)

Mainline QEMU has full RISC-V support, don’t use forks

7/1/2019©2019 Western Digital Corporation or its affiliates. All rights reserved. 5

Getting started with QEMU

• The best way to get started is to follow your distros guide

Fedora, Debian, Buildroot and OpenEmbedded all have guides on running on QEMU

• OpenSBI documentation also describes booting on QEMU

• The QEMU wiki has a RISC-V page

7/1/2019©2019 Western Digital Corporation or its affiliates. All rights reserved. 6

QEMU DemoDebugging OpenSBI with instruction output

7/1/2019©2019 Western Digital Corporation or its affiliates. All rights reserved. 7

QEMU DemoConnecting GDB to QEMU and setting break points

7/1/2019©2019 Western Digital Corporation or its affiliates. All rights reserved. 8

QEMU DemoEnabling RISC-V ISA extensions, Hypervisor (H) extension

7/1/2019©2019 Western Digital Corporation or its affiliates. All rights reserved. 9

QEMU DemoRunning RISC-V Linux User Mode

© 2019 Western Digital Corporation or its affiliates. All rights reserved. 7/1/2019

Western Digital and the Western Digital logo are registered trademarks or trademarks of Western Digital Corporation or its affiliates in the US and/or other countries. Debian is a registered trademark owned by Software in the Public Interest, Inc. Linux® is the registered trademark of Linus Torvalds in the U.S. and other countries. Fedora is a registered trademark of Red Hat, Inc. in the U.S. and other countries. All other marks are the property of their respective owners.