dØ runiib trigger upgrade

FNAL PMG Feb 5, 20041

DØ RunIIb Trigger Upgrade

WBS 1.2Paul Padley, Rice University

for the DØ Trigger Upgrade Group


Run IIb Luminosity Projections

0

50

100

150

200

250

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3 4 5 6 7 8 9 10Start of Fiscal Year

~1.6e32

~2.8e32Accelerator draft plan:Peak luminosities

Pea

k Lu

min

osity

(x1

030cm

-2se

c-1)

You are herePeak FY04 ~5e31


Ingredients of the Trigger Upgrade

Level 1 Calorimeter trigger upgrade

sharpens turn-on trigger thresholds more topological cuts

Calorimeter track-match fake EM rejection tau trigger

L1 tracking trigger upgrade (CTT) improved tracking rejection especially at higher

occupancies inputs to Calorimeter track-match

Level 2 L2 Processor upgrades for more complex algorithms Silicon Track Trigger expansion

More processing power use trigger inputs from new silicon layer 0


Trigger Upgrade Project Institutions

Boston, Columbia, Stony Brook, FSUSTT upgrade

Orsay, Virginia, MSU Level 2

U. of ArizonaCal-Track match

MSU, Northeastern, FSU,LangstonOnline software & integration

Notre Dame, Saclay, Kansas, Manchester, Brown, Northeastern

Simulation & algorithms

Boston U., FNALTrack trigger

ColumbiaCalorimeter: TAB

(Saclay), MSU, UICCalorimeter: ADF

Institution(s)Sub-project


Management structure

WBS 1.2: Trigger UpgradeP. Padley (Rice), D. Wood (Northeastern)

WBS 1.2.1: Level 1 CalorimeterM.Abolins(MSU), H.Evans(Columbia)

WBS 1.2.2: Level 1 Cal-track matchK. Johns (Arizona)

WBS 1.2.3: Level 1 TrackingM. Narain (Boston)

WBS 1.2.4: Level 2 Beta upgradeR. Hirosky (Virginia)

WBS 1.2.5: Level 2 STT upgradeU. Heintz (Boston)

WBS 1.2.6: Trigger SimulationM. Hildreth (ND), E. Barberis (NEU)

WBS 1.2.7: AFE upgradeA. Bross


WBS 1.2.1: L1Cal

ADC+digital filteringClustering

Global sums &topological


Integration Tests

Testing Data Transfer Oct. Integration Test

SCL to ADF/TAB ADF to TAB TAB to Cal-Track

Bench Tests ADF to GAB mechanism


ADF Prototype

MSU is on board working with SACLAY on next prototype

On track to finalize changes and proceed to build a new prototype for testing in the early summer

ADF Digital fine

ADF Analog some noiselargely due to driving voltage on ADCsnew analog “unit cell” to improve noise performance


TAB Prototype

Valuable Data from Integration

TAB almost ready for Prod only data to L2/L3

to test > 6 months ahead

of sched !


What’s next

proto. GAB next week ver.2 ADF layout new integration test

BLS to ADF TAB to L2/L3 ADF to TAB: extended running


WBS 1.2.2: L1 cal-track matching

MTCxx (Trigger Cards) Was submitted for production

UFB (Flavor Board) Prototypes in hand See next Slide

MTCM (Crate Manger) Logic changes finished Awaiting final checks


L1 Cal Track Match

UFB (Flavor Board) Prototypes in hand L1MU “05” algorithm

implemented in Stratix EP1S20F780C7

H successfully implemented and tested

Universal Flavor board (daughter)Run IIb prototype

MTCxx (mother)Run IIa version


L1CalTrack Status

Infrastructure VME crates, processors, power supplies,

cables in hand L1CTT to L1CalTrack cables installed during

current shutdown (not terminated) Crates installed in Movable Counting House

Commissioning Plan is to use spare L1MU cards in

L1CalTrack crates to establish communication with Trigger Framework and L3

Replace spares with L1CalTrack cards as available


WBS 1.2.3: L1 CTT

Digital Front End Axial (DFEA) daughter cards get replaced with new layout with larger FPGA’s (Xilinx Virtex-II XC2V6000).

Allows CTT to use “singlets”

Implemented prototype firmware (Boston U) Includes equation files from all 4

momentum bins pT>10 GeV, 5<pT<10 GeV, 3<pT<5 GeV,

1.5<pT<3 GeV DFEA logic is implemented in two FPGAs

Currently undergoing tests with prototype DFEA card


CTT Workshop

There was a very productive workshop at BU in January

included physicists and engineers

experts from Run2a commissioning involved

detailed discussion of algorithms and FPGA resources

emphasis on firming up final

hardware specifications

building a system that is fast and easy to commission

It was so cold in Boston that this lobster turned blue!


Some highlights from meeting

Specific FPGA choice was made (an important step)

There were a number of design changes suggested to make the upgrade easier to commission and minimize the impact on physics. There should be a detailed specification of

these changes by the end of the month.


WBS 1.2.4: L2eta Upgrade

6U boardCompact PCI

9U board64 bit

<2MHzVME

FPGA

EC

L D

rive

rs

128 bits~20 MHzMBus

32 bits66 MHz (max)Local bus64 bits

33 MHzPCI

J1

J2

J3

J5

J4

PLX9656

UII

Dri

vers

Dri

vers

Clk(s)/roms

•Run IIa Betas are installed and running smoothly in all level 2 crates

•Run IIb strategy: purchase additional, more powerful commercial processors as late as reasonably possible.


WBS 1.2.5: Silicon Track Trigger for Run IIb

Technical Progress: VME Transition

Modules procured With the approval of

Layer 0, the procurement process was restarted.

Presently 90% of components are purchased.

(since this upgrade is just building more of an existing board procurements are the main issue)


1.2.6 Simulation

The simulation effort has been reorganized

E. Barberis has become L3 manger along with M. Hildreth.

Recent simulation work has focused on the CTT but now a renewed effort to look at other aspects of the trigger upgrade, using the most recent experience in operations, is underway.

Plan to have a preliminary trigger list by summer.


1.2.7 AFE II

Work on the AFE II board layout has started.

The specifications for Tript been defined and discussed with Ray Yarema’s group.

Ray Yarema’s group has started work on the Tript

Paul Rubinov is looking into Tript packaging options

Analysis continues on the impact of high luminosity and radiation damage on the CFT capability and how this will effect physics.


Summary

Trigger upgrade proceeding at full speed

Prototypes in hand: L1cal: splitter, TAB, VME/SCL, ADF Cal-track: UFB, MTCxx proto in fabrication L1CTT: DFEA preproduction I being tested

Plan to install with minimal downtime

dØ runiib trigger upgrade

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