digital testing: role of simulation in testing
DESCRIPTION
Digital Testing: Role of Simulation in Testing. Outline. Verification and Simulation Verification Types of Simulation Fault Simulation Parallel Simulation Concurrent Simulation Deductive Simulation Fault Coverage Fault Dictionary. Types of simulation. - PowerPoint PPT PresentationTRANSCRIPT
04/21/23
Based on text by S. Mourad "Priciples of Electronic Systems" and M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal
VLSI Circuits
Digital Testing: Role of Simulation in Testing
Outline
Verification and Simulation Verification Types of Simulation Fault Simulation Parallel Simulation Concurrent Simulation Deductive Simulation Fault Coverage Fault Dictionary
Types of simulation
Event is a change in signal valueUseful for accurate timing modelsUseful for asynchronous circuits
Compiled simulator (table-driven)
• Functional verification
Activity directed (event-driven)simulator
Types of Simulators
Logic versus Fault Compiled versus event driven Functional versus timing Logic versus other levels (RTL or switch) Mixed level Emulators
Simulation of Large Systems
Explosion in number of gates usedNot possible with software to complete
Move to simulation of the whole circuit on
RTL level e.g. use of testbench in HDL
Cycle based Simulationsimulation of components at different levels using different simulatorrelate the results using the same clock
Simulation System
StimuliDesignModel
Simulator
Response
Library
Testbench: Example in Verilog
' timescale 1ns/1ns // Time unit is 1nsmodule adder; // Design Testbenchreg PA, PB, PCI;wire PCO,PSUM;
FA_Behav F1(PA, PB, PCI, PSUM,PCO); // Instantiate module under test
initialbegin: ONLY_ONCEreg[3:0] Count; // Count hold the count of stimuli
//4 bits are needed to accommodate up to 8.
for (Count=0; Count < 8; PAL =Count +1)begin{PA, PB, PCI} =Count; //The stimuli are the values of Count
#5 $display ("PA, PB, PCI=%b%b%b", PA, PB, PCI,":::PCO,PSUM=%b%b", PCO, PSUM);
//Creation of the response display
endendendmodule
Logic Simulation
Verifies both function & timing Check that operation is :
independent on initial statenot sensitive to variations in delaysfree of races, oscillations, illegal & hung-up states
Logic Simulation Software Based
Slow
Hardware AcceleratorsSimulation algorithm is
hardwiredImproves performance with
large set of inputs
EmulatorPrototyping and real time simulatione.g. using FPGAs to implement the designPentium was emulated on 3500 Xilinx3000 FGPAs
EPROM Emulator
Logic Simulation Levels
Circuitdescription
Programminglanguage-like HDL
Connectivity ofBoolean gates,flip-flops andtransistors
Transistor sizeand connectivity,node capacitances
Transistor technologydata, connectivity,node capacitances
Tech. Data, active/passive componentconnectivity
Signalvalues
0, 1
0, 1, Xand Z
0, 1and X
Analogvoltage
Analogvoltage,current
Timing
Clockboundary
Zero-delayunit-delay,multiple-delay
Zero-delay
Fine-graintiming
Continuoustime
Modelinglevel
Function,behavior, RTL
Logic
Switch
Timing
Circuit
Application
Architecturaland functionalverification
Logicverification
and test
Logicverification
Timingverification
Digital timingand analogcircuitverification
0 1 X0 0 01 1 1X 0 1 X
A cube of the Boolean function is a vector
A simplified truth table based on singular cubes is called a singular cover
Rules for intersection of cubes in Boolean logic
Z x x xn( , ,..., )1 2
{( , ,..., | ): ( , ,..., )}v v v v v Z v v vn z z n1 2 1 2
Singular cover
ExerciseCheck if the following cubes describe a logic functionC1 1 1 x 0C2 0 1 0 1C3 0 x 1 1C4 0 0 x 0
ExerciseCheck if the following cubes describe a logic functionC1 1 1 x 0C2 0 1 0 1C3 0 x 1 1C4 0 0 x 0
No, since 001 would cause 2 different output values as it belongs to both c3 and c4
( , , ) ( , , ) ( , , )
( , , ) ( , , ) ( , , )
0 0 1 0 1 0 0 1 1
0 0 1 0 0 0 0 1 0
x output
x output
Unknown logic value
Initial state of powered-up FF & RAMs is unpredictableu -- denotes unknown logic value (0 or 1)Boolean operation with u is a union of all operations on different values like
OR(0,u)=OR{{0},{0,1}}={OR(0,0),OR(0,1)}={1,0}=u 0 1 X U0 0 0 1 1 1 X 0 1 X UU U U
Intersection of cubes in 3 valued logic
u
1
u0
u
u
u
Pessimistic result in 3-valued simulation
Since not(u) = u
Determine value of the logic function defined by the following cubesa) X10 0b) 11X 0c) X0X 1d) 0 1 1 1
For the input vector I=(10u) using simulation
Exercise
True-Value Simulation Algorithms
Compiled-code simulation• Applicable to zero-delay combinational logic
• Also used for cycle-accurate synchronous sequential circuits for logic verification
• Efficient for highly active circuits, but inefficient for low-activity circuits
• High-level (e.g., C language) models can be used
Event-driven simulation• Only gates or modules with input events are evaluated (event
means a signal change)
• Delays can be accurately simulated for timing verification
• Efficient for low-activity circuits
• Can be extended for fault simulation
Compiled-Code Algorithm
Step 1: Levelize combinational logic and encode in a programming language
Step 2: Initialize internal state variables (flip-flops)
Step 3: For each input vectorSet primary input variables
Repeat (until steady-state or max. iterations)
• Execute compiled code
Report or save computed variables
Levelization for Compiled Simulation
G4
G5 G8
G6
G7 G9
G3
G10
G2
G1CD
E
G
IJ
H
AB
Level 0 Level 1 Level 2 Level 3 Level 4
F
Event-driven simulation flow
Advance simulation time
Propagate events
Schedule resulting events
Evaluate activated elements
Update values
Determine current events done
No more events
Delay models
(a) Nominal transition-independent
transport delay
(b) Rise and fall delays
(c) Ambiguous delay
(d) Inertial delay (pulse suppression)
(e) Output inertial delay
A
C
C
C
C
C
3
2 3
1 5
3
R1 R21
(a) d=2
(b) dr=1, df=3
(c) dm=1, dM=3
(d) dI = 4,
(e) dI=2, d=3
A
B=1
C
Delay models(a) Nominal transition-independent transport delay
(b) Rise and fall delays
(c) Ambiguous delay
(d) Inertial delay (minimum duration of input pulse)
(e) Output inertial delay
3
Output inertial delay
A
B
C
dI = 3
A
B
C
2
3 2
The gate cannot produce impulse shorter than dI
A
B
C
2
2 1
3 3
Output inertial delay
dI = 3
A
B
C
d1
d2
Wire delays modeled by delay elements
c x x c ix c x c ix x c c ic’ c’ c’ c’ i
c iAND 0 0OR 1 0NAND 0 1NOR 1 1
Truth tables• quires 2n entriesInput Scanning• gates described by
- c -- controlling value- i -- inversion
Element evaluation
Evaluate (G, c, i)begin
u_values = FALSEfor every input value v of G
beginif v = c then return c iif v = u then u_values = TRUE
endif u_values return ureturn c’ i
end
Gate evaluation in 3-valued logic by scanning input values
evaluate (G, c, i)begin
if c_count > 0 then return c iif u_count > 0 then return ureturn c’ i
endAdvantage:No need to store the multiple input values (only two counters for c_count and u_count are updated during simulation)For instance in AND gate 1->0 change on its input increases c_count while 0->u transition increases u_count and decreases c_count.
Gate evaluation in 3-valued logic based on input counting
Hazard Detection
R Q
S
AB
Z
(Static hazard)
A
B
Z
Latch may be reset
Unknown signal value
B
t t’ t+1
==> B(t)B(t’)B(t+1) = 0u1
Also : A(t)A(t’)A(t+1) = 1u0
Z = (AB)’ = 1u1 {101, 111}- possible static hazard
Static Hazard DetectionDenote by E the set of inputs changing between t and t+1
Procedure 3.11. Set every input E to u and simulate to get output Z(t’)2. Set every input E to its value at t+1 and simulate to get Z(t+1)
Theorem 3.1In a combinational circuit, a static hazard exists iff Z(t)Z(t’)Z(t+1) is 1u1 or 0u0
Hazard Detection
(a) 0 delay : B = 101, C = 000 (b) unit delay : B = 1101, C = 0100(c) arbitrary delay : A = 0u1u0, B = 1u0u1
=> C = 0u0u0 (hazard)
CA
B
If A = 010 then:
Check the following circuit for static hazards
6-valued logic for static hazard analysis
Value Sequence(s) Meaning0 000 Static 01 111 Static 10/1, R {001, 011} = 0u1 Rise (0 to 1) transition1/0, F {110, 100} = 1u0 Fall (1 to 0) transition0* {000, 010} = 0u0 Static 0-hazard1* {111, 101} = 1u1 Static 1-hazard
AND 0 1 R F 0* 1*0 0 0 0 0 0 01 0 1 R F 0* 1*R 0 R R 0* 0* RF 0 F 0* F 0* F0* 0 0* 0* 0* 0* 0*1* 0 1* R F 0* 1*
AND truth table for 6-valued logic
Dynamic Hazards
Dynamic hazards occur during transition 1->0 or 0->1So they require 4 bit sequences to detect1010 or 0101
To detect them in simulation 8 valued logic is used.8 valued logic can detect both static and dynamic hazards
8-valued logic Logic value
Output Sequence Meaning
0 0000 Static 0 1 1111 Static 1 0/1, R {0x11, 00x1} Rise 1/0, F {11x0, 1x00} Fall 0* {0ux0, 0xu0} Static 0 hazard 1* {1ux1, 1xu1} Static 1 hazard R* {0u01, 01u1} Dynamic 1 hazard F* {1u10, 10u0} Dynamic 0 hazard
ExerciseTo determine result of Boolean operation in 8 valued logic all possible sequences must be used
For instance to calculate AND(R,1*) we have
AND(R,1*)=AND({0x11,00x1},{1ux1,1xu1})={0uu1,00u1}=R*
Rules for inversion
NOT(F)=R, NOT(0*)=1*, NOT(F*)=R*
NAND 0 1 R F 0* 1*0 1 1 1 1 1 11 1 0 F R 1* 0*R 1 F F 1* 1* FF 1 R 1* R 1* R0* 1 1* 1* 1* 1* 1*1* 1 0* F R 1* 0*R* 1 F* 1* 1* F*
F* 1 R* 1* R*
R* F*1 1F* R*
F* 1*1* R*
1* 1* 1*F* R*
NAND truth table for 8-valued logic
Exercise: Calculate NAND(R,R*)
NAND 0 1 R F 0* 1*0 1 1 1 1 1 11 1 0 F R 1* 0*R 1 F F 1* 1* FF 1 R 1* R 1* R0* 1 1* 1* 1* 1* 1*1* 1 0* F R 1* 0*R* 1 F* 1* 1* F*
F* 1 R* 1* R*
R* F*1 1F* R*
F* 1*1* R*
1* 1* 1*F* R*
NAND truth table for 8-valued logic
Exercise: Calculate NAND(R,R*)NAND(R,R*) = NAND({0x11,00x1},{0u01,01u1}) =NOT({0u01,01u1,0001,00u1}) ={1u10,10u0,1110,11u0}=F* Exercise:
Calculate NAND(F,R*)
Event-Driven Procedure Event-Driven-Simulator:
Read circuit descriptionRead input vectorsFOR each input vector to be simulated DO
Process new inputsUpdate input nodesSchedule connected elements on timing wheelWHILE elements left for evaluationEvaluate elementIF change on the output
THEN update all fanouts and schedule Connect element on timing wheel
END WHILE END FOR
End procedure
Gate level event-driven simulationOnly the activated gates are analyzed.Not all entries in the event list are events
AB
Z
A
B
Z 0 2 4 6 8 10 12
8 10 12(Z, 1) (Z, 0) (Z, 0) Not an event
Event Simulation
G4
G5
G6
G7 G9
G3
G10
G2E
G(1)
I(1)J(1)
H(1)
A(0)
B(0)
(1 => 0)
*
**
**
F(1)
(0 => 1)
11
1
0
0
0G1C(0)
D(0) G8 *0
While (event list not empty)begin t = next time in list process entries for time tend
There is no events on G3, G5, G7, G8, and G9 due to F=1
Time Wheel (Circular Stack)
t=0
1
2
3
4
5
6
7
maxCurrenttimepointer Event link-list
The Time Wheel
Time in ns is computed modulo M = tc mod Mfor events tc te tc + M-1
If tc+ M te then the event is put on the overflow queue
1
tc
M
i, vi’ j, vj’ *
Event-Driven Algorithm(Example)
2
2
4
2
a =1
b =1
c =1 0
d = 0
e =1
f =0
g =1
Time, t 0 4 8
g
t = 0
1
2
3
4
5
6
7
8
Scheduledevents
c = 0
d = 1, e = 0
g = 0
f = 1
g = 1
Activitylist
d, e
f, g
g
Tim
e s
tac
k
Timing Simulation
(a)
G
AND1
AND2
OR1
INV
A
B
C
D=1
C'
E
F
Delay
14 17
11 18 30 36 4526
37 404530
2620
22 24
38 41
E
F
G
XXXXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
(b)
(d)
8 11
14 22 32 334
7 12 20 25
35
35
3631
30
21
20
13
122
3
10 255
A
B
C
C'
E
F
12 16
10 18 28 36 42
15 17 22 23 32 41 48
G
E
F
G
XXXXXXXXXXXX
XXXXXXXX
XXXXXXXXXXXXX(c)
Unit delayVariable delayRise and fall delay
Static Timing Simulation Critical path delay
Using the circuitand worst case analysis of delayslow complexity
ProblemsNo consideration for the functionFalse path
Oscillation Control
Local oscillation can be controlled by setting unstable feedback signals to uGlobal oscillations are hard to control -- they are avoided by limiting the simulation time.
When oscillation occur during simulation they waste simulator efforts – the same loops are traversed again and again
Other logic values
Tristate logic -- several devices share a bus. Each driving device is controlled by the enable signal E. Simulator should report potential conflicts when a bus is driven by 0 and 1
0 1 Z u
0 0 uc 0 u
1 uc 1 1 u
Z 0 1 Z u
u u u u u
Other logic valuesMOS logic -- Transmission gates act like bus driver, except when the gate is open the wire connected to its output retains its previous value.
u
0 1
Zu
Z0 Z1
Z
Relative strength of logic values used in MOS Simulation.
Weak values are caused by open circuits
Logic Strength
G1 G2A
S
B
S'
Signals A and Bmay be undetermined if S=1 depending on the drivers strength
Exercise for MOS simulation
AI
B
E
D H
G
C
F
Use inputs from the following table to find signals C,F,H,I
A B D E G
1 1 0 1 01 0 0 1 10 1 1 0 11 0 1 0 0
Exercise for MOS simulation
AI
B
E
D H
G
C
F
Use inputs from the following table to find signals C,F,H,I
A B D E G
1 1 0 1 01 0 0 1 10 1 1 0 11 0 1 0 0
C F H I
0 1 0 1Z0|1 1 0 01 Z1|1 0 0Z1 Z1 0 0