APRESENTATION ON

ANALYSIS OF DIFFERENT LOGIC FULL ADDERS

BYA.GUNA SEKHAR

11HR1A04011

CONTENTS

Need of adders

Basic parameters

Full adder

C-CMOS logic full adder

CPL

DPL

Transmission gate full adder

Transmission function full adder

14T Full adder

GDI XOR/XNOR Full adder

2

WHAT IS THE NEED OF ADDERS??

Addition is the basic arithmetic operation

Core of arithmetic operation like multiplication,

subtraction, division etc.,

Adder is the key element for VLSI Systems like

ALU,s

Microprocessors

Parity checkers

Code converters

3

BASIC PARAMETERS

As any VLSI System basic requirements:

Similarly for Full adder circuit requires:

Power consumption

Speed

Area

PDP

Delay

Power dissipation

4

FULL ADDER

For three bit addition

Accept a carry bit from a previous stage

C = AB + ACin + BCin

S = A'B‘Cin + A'BCin'+AB'Cin'+ABCin

5

A B Cin Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

DIFFERENT LOGICS OF FULL ADDER

C-CMOS logic full adder

Pass transistor logic

CPL

DPL

Transmission gate full adder

Transmission function full adder

14T Full adder

GDI XOR/XNOR Full adder

6

C-CMOS LOGIC FULL ADDER

Conventional CMOS

24 transistors

Structure is based on pull up & pull down

High noise margin

Stability at low voltages

Less number of interconnecting wires

Weak output driving capability

7

8

Cont. ,

C-PASS TRANSISTOR LOGIC

Complementary Pass Transistor Logic

24 transistors

Each signal is carried by two wires

Faster than CMOS

High power consumption

Wiring complexity

High delay

9

10

Cont. ,

DOUBLE PASS TRANSISTOR LOGIC

28 Transistors

Both nMOS and pMOS logic network

Reduces threshold loss problem

Noise margin

Speed

Low power

Requires less area

11

12

Cont. ,

TRANSMISSION GATE FULL ADDER

20 Transistors

Delay is less

High number of internal nodes increase parasitic

capacitance

Additional buffers required

Weak driving capability

More power consumption

13

14

Cont. ,

TRANSMISSION FUNCTION FULL ADDER

16 transistors

Two possible short circuit paths to ground

Same delay as C-CMOS and cpl

High noise margin

15

16

Cont. ,

14T FULL ADDER

14 Transistors

Uses hybrid logic styles( more than one logics)

It uses XOR/XNOR circuit with feedback loop

Less driving capability

Noise immunity

17

18

Cont. ,

GDI XOR/XNOR FULL ADDER

10 transistors

It uses XOR/XNOR gate & multiplexers

Consumes less power

Less internal capacitance

Less area

19

COMPARISION BETWEEN DIFFERENT LOGICS

Sl No Cell Name Delay Avg power PDP Transistors

1 C-COMOS 0.195 0.345 0.067 24

2 CPL 0.182 0.367 0.032 32

3 DPL 0.167 0.361 0.06 28

4 TG CMOS 0.135 0.305 0.041 20

5 TFA 0.353 0.044 0.015 16

6 14T 0.548 0.049 0.026 14

7 GDI XOR 0.161 1.384 0.223 10

8 GDI XNOR 0.266 0.055 0.014 10

20

REFERENCES

• Mariano Aguirre-Hernandez and Monico Linares-Aranda, “CMOS Full-Adders for Energy-EfficientArithmetic Applications,” in Proc. IEEE VLSI SYSTEMS, 4, April 2011, vol. 19, pp. 718-721.

• A. M. Shams, T. K. Darwish, and M. Bayoumi, “Performance analysis of low-power1-bit CMOS full adder cells,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20–29, Feb. 2002.

• S. Goel, A. Kumar, and M. Bayoumi, “Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1309–1320, Dec. 2006.

• Amir Ali Khatibzadeh, Kaamran Raahemifar, “A study and comparision of full adder cells based on the standard CMOS logic,” IEEE Trans.CCECE, Niagara Falls, May 2004 0-7803-8253, pp. 2139-2142

21

THANK YOU

22