development of an optically transparent silicon cmos technology platform for biological analysis

1530-437X (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. Seehttp://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI10.1109/JSEN.2014.2367238, IEEE Sensors Journal

1

Abstract— A prototype optical structure suitable for advanced

biological investigation has been successfully manufactured using

plasma enhanced chemical vapor deposition (PECVD) and deep

reactive ion etching (DRIE) techniques. Our approach to the

design and fabrication of the structure is such that it can easily be

integrated onto a lab-on-a-chip (LoC) cell positioning platform,

combining use of integrated circuit (IC) technology with optimal

in-situ analysis of cells through the substrate using high

resolution inverted microscope systems. This work describes the

concept, design, fabrication, and optical characterization of a

transparent window and corresponding via, which extends from

the top surface to bottom surface of a silicon wafer. The

effectiveness of the platform is demonstrated in multi-color

fluorescence imaging of cells, cultured on-chip, using an inverted,

confocal microscope.

Index Terms—CMOS, Dielectrophoresis (DEP), lab-on-a-chip

(LoC), on-chip imaging, on-chip microscopy. Manuscript received May 2nd , 2014

N. Davies is with SPTS, SPTS Technologies, Ringland Way, Newport, UK

NP18 2TA P. Holland, M. Holton, J. Wills, M. Rowan Brown and H.D. Summers are

with the College of Engineering, Swansea University, Swansea, UK SA2 8PP

* Corresponding author: [email protected] This work was funded by the UK’s Engineering and Physical Science

Research Council (EPSRC) First grant scheme; grant number EP/I038799/1

I. INTRODUCTION

dvances in the fabrication techniques of Complementary

Metal Oxide Semiconductor (CMOS) devices for

traditional electronic applications have enabled a new

technology to develop based on electrical and mechanical

operations. These devices termed Micro Electro Mechanical

Systems (MEMS) have evolved through continued

miniaturization to be used across a spectrum of application

areas. These advances have been adapted by and contributed

to ‘on-chip’ tools used in the biotechnology area and as a

consequence of these advancements; miniaturized and self

contained lab-on-a-chip (LoC) systems have been developed.

The traditional method of analyzing biological matter situated

on glass slides is through the use of inverted microscope [1].

Research effort to support effective single cell studies have

identified many techniques to physically manipulate cells [2],

some of which can be implemented on silicon, enabling access

to the power of the integrated circuit (IC). Indeed recent

innovations now allow the automated sorting and isolation of

single cells for biological investigation using LoC

technology[3, 4] and there is a need to integrate this additional

functionality within microscopy platforms. LoC silicon

technology utilizes the power of the integrated circuit to allow

high cell count sorting and positioning. A disadvantage of the

majority of the current generation of such devices is that when

the cell sorting procedure has been completed the isolated

cells then have to be removed to allow more detailed

biological analysis. If the isolated cells could be analyzed

without the need to be removed from the LoC device then the

process would not only gain advantages in terms of the speed

of the analysis but would also reduce the risk of cell damage

and contamination as the cells are moved to a different

medium. Recently some on chip imaging approaches have

emerged that use specific onboard optical biosensors and these

will be of particular use on point-of-care and field applications

[5-8]. However, these LoC onboard optic systems have not yet

reached the level of development of other detection methods

[9]. Whilst reasonable optical performance may be achieved

with integrated systems they can never match the ultimate in

resolution and sensitivity provided by high performance

microscopes. Thus the adaptation of silicon based LoC device

that could use optically transparent windows through the

structure of the integrated circuit in conjunction with modern

biotechnology analytical techniques, such as Epi-fluorescence

microscopy, would have advantages in cost, robustness and

accuracy. A fluorescence microscope is an example of a larger

more expensive piece of equipment that could be used in

conjunction with a cheaper LoC device that would give

consistent reliable results with a large throughput. This

method could also be expanded to include other optical

techniques such as differential interference contrast

microscopy, phase contrast microscopy, darkfield microscopy

and confocal microscopy [10-12].

Whilst silicon IC technology has been successfully

implemented to sort cells using dielectrophoresis [13], no

technology has previously been available to allow in-situ

optical analysis on inverted microscope systems. A concept to

achieve this aim is shown in Fig. 1. In our concept of a

transparent CMOS LoC the normal transistors forming mixed-

signal circuitry and passive components are fabricated in the

standard process. The dielectric layers of a CMOS device

isolate the conducting parts, such as the wire interconnects and

transistors, from one another and are typically made of silicon

based material. The electrical properties of these dielectric

layers such as breakdown voltage and leakage current are

essential to ensure that the CMOS device functions correctly.

Development of an Optically Transparent

Silicon Based Technology Platform for

Biological Analysis Nigel Davies, Huw D. Summers, Mark Holton, M. Rowan Brown, John Wills

and Paul Holland Member IEEE.

A



2

Fig. 1. Schematic of the Proposed LoC CMOS Platform in Cross-Section.

The silicon materials used to fabricate these dielectric

layers also possess inherently good optical properties [14-16].

This leads to interesting possibilities for manipulation of the

refractive indices and thickness of these dielectric layers such

that the optical performance of the stack can be modified for

specific application requirements. For instance in the example

application shown in Fig. 1. the optical stack could be adjusted

to maximize the transmission of specific wavelengths used by

the fluorophores. However, the balance between optical and

electrical performance must be maintained if the functionality

of the CMOS platform is to be preserved.

In this paper we demonstrate the semiconductor fabrication

techniques required to form such an optical structure using

standard dielectric layers. Optical analysis of the dielectric

stacks is performed analytically using the Bayes-Spectral-

Entropy-Based measure of focus technique and is practically

demonstrated by imaging three color fluorescence lung

epithelial cells loaded with quantum dots. Physical optical

transmission measurements are used in conjunction with

computational modeling of transmission properties to

understand the observed thin film interference caused by the

multi-layer dielectric layer stack. The proposed structure is a

novel approach to the traditional method of optical sensing on

a LoC technology platform [17].

II. DEVICE FABRICATION

The CMOS architecture at the 0.35µm node suitable for

LoC work consists of at least three dielectric layers: the Pre-

Metal Dielectric (PMD), Inter-Metal Dielectric (IMD) and a

passivation layer [18]. The two test structures that were

fabricated are shown in Fig. 2. and are representative of a

CMOS device that has been designed with sufficient spacing

between the metal layers to allow the formation of the optical

structure. In this work, we use standard semiconductor

materials. Tetraethylorthosilicate (TEOS) is used to form the

PMD, TEOS to form the IMD of stack 1, Silicon Oxide

(SiO2) to form the IMD of stack 2 and Silicon Nitride (Si3N4)

to form the passivation layer [19-23].

Fig. 2. Schematic (a) Stack 1- TEOS-TEOS- Si3N4 (b) Stack 2 TEOS-SiO2-

Si3N4

725μm

Layer 1 (PMD) TEOS 2μm

Silicon Substrate Silicon Substrate

Etched Via

Layer 2 (IMD) TEOS 2μm

Layer 3 (Passivation) Si3N4 2μm

Layer 1 (PMD) TEOS 2μm

Silicon Substrate Silicon Substrate

Layer 2 (IMD) SiO2 2μm

Layer 3 (Passivation) Si3N4 2μm

Etched Via

1mm

725μm

1mm

(a)

1mm

(b)



3

As different CMOS process architectures use different

planarization schemes, two different stacks were analyzed to

allow flexibility in future integration work. The utilization of

TEOS in the IMD layer of stack 1 would offer improved

planarization over the SiO2 IMD layer of stack 2. However,

TEOS is a more expensive option than SiO2 and should only

be used if required to achieve a specific CMOS architecture.

The dielectric layers were deposited using an SPTS

Technologies Advanced Plasma Module (APM®) that utilizes

Plasma Enhanced Chemical Vapor Deposition (PECVD)

technology.

The SiO2 films were deposited using a Gas flow regime of

1000sccm of N2, 2000sccm of N2O and 100sccm of SiH4,

Electrode Spacing of 20mm, High Frequency (HF) at

13.56MHz and 450W and a process pressure of 1500mTorr

[24]. The Si3N4 films used a Gas flow regime of 3600sccm of

N2, 950sccm of Ammonia and 400sccm of SiH4, Electrode

Spacing of 20mm, HF at 825W, Low Frequency (LF) at

375KHz and 400W and a process pressure of 2600mTorr

[25].The TEOS films used a Gas flow regime of 2700sccm of

O2, 500sccm of He used as a process stability gas and 2.5ccm

of liquid TEOS, Electrode Spacing of 12mm, HF at 1500W,

LF at 130W and a process pressure of 2700mTorr [26].

The difference between the stacks was that layer 2 (IMD) on

Stack 1 used TEOS and on Stack 2 used SiO2. Although

TEOS is more expensive it has improved planarization

properties and the use of TEOS for the IMD layer could be

necessary in some CMOS applications. The 300mm silicon

substrates used were 775μm thick. On completion of the

PECVD process the backside of the 300mm substrate was

masked which exposed different via areas ranging from

0.25mm2 to 2mm

2.

The etching of the silicon substrate through to the optical

structure was performed on a SPTS Technologies Rapier®

Deep Silicon Etch System. Many methods of silicon etching

exist therefore the correct process depends on the required

etch isotropy. It was assumed that a vertical anisotropic etch

would be required for this application so as to allow multiple

windows to be fabricated in close proximity. The reason why

plasma etching techniques were used was due to the fact that

chemical wet etching cannot achieve the anisotropic vertical

etch. However, it is only under certain dry etch process

conditions, referred to as the Bosch process, that a vertical

etch can be achieved [27, 28]. The Rapier module uses two

Radio Frequency (RF) sources which is unique for deep

reactive ion etching (DRIE) capital equipment and thus

benefits from the advantages of Inductive Coupled Plasma

(ICP) and a Deep Silicon Etch (DSE) bell jar source. The etch

process was performed using a variant of the Bosch process,

which consisted of cyclic C4F8 deposition and SF6 etch phases

at an etch pressure regime of 70mTorr. The wafer sat on an

Electrostatic Chuck on to which was applied 50W of HF

power at a temperature 10°C. The DSE source power was set

to 3.5kW of HF power and the ICP source power was set to

1.5kW of HF power. The etch depth was controlled by a

Claritas® endpoint system which optically monitored the

reactive species (etch by-products). In this case the reactive

species was Silicon Tetrafluoride (SiF4) at 440nm. The

substrate was then cleaved to expose the etched via and

dielectric stacks and examined on a Zeiss Supra 55VP

Scanning Electron Microscope (SEM), refer to Fig. 3.

(a)

(b)

(c)

Fig. 3. SEM images (a) Optical Structure (b) Stack 1- TEOS-TEOS- Si3N4 (c)

Stack 2 TEOS-SiO2- Si3N4

III. ELECTRIC-OPTICAL PROPERTIES OF THE DIELECTRIC

LAYERS

A. Wafer Process Results

In order to allow the measurement of voltage breakdown,

leakage current, film stress, non-uniformity, refractive index

(RI) and dielectric constants single films of SiO2, Si3N4 and

TEOS were deposited at 150nm and 2000nm thickness on a

200mm substrate. The results showed that the RI was of

expected values and that the non-uniformity was at levels that

could be used in a production environment as shown in Table

I. Additionally, the film stresses were all compressive; this is

an important result as it is desirable to have a compressive

stress to prevent the formation of cracks in any deposited film.

This may not be clear intuitively from the shape of the

substrate. It should be remembered that if a tensile stress is



4

present the film will be more prone to crack. In addition,

compressively stressed silicon nitride films are generally

acknowledged to give the best barrier properties. These are

widely used in CMOS multi-level metal interconnect scheme

[18].

TABLE I

WAFER PROCESS RESULTS

Film Type

Thickness (µm)

Non Uniformity 1σ (%)

RI

Stress (MPa)

SiO2 0.1486 0.69 1.4644 -

SiO2 1.9740 0.57 1.4636 -140 Si3N4 0.1522 1.52 1.9973 -

Si3N4 1.9392 1.49 2.0056 -220

TEOS 0.170 0.6 1.4514 - TEOS 2.1321 0.64 1.4595 -140

B. Voltage Breakdown and Leakage Current

To measure voltage breakdown and leakage current of the

films 150nm of the SiO2, Si3N4 and TEOS were deposited on

200mm low resistivity [p-type, B-doped, 0.005-0.02 Ohm-cm]

silicon wafers. 1.5mm diameter aluminum dots were then

evaporated through a metal stencil mask to form a test

structure. The low resistivity silicon substrate formed the

lower electrode and the evaporated aluminum formed the

upper electrode. A Keithley 2400 SMU was used to supply the

test voltage [0-200V] and a Keithley 6485 PicoAmmeter was

used to measure leakage current. All measurements were

conducted at room temperature with the voltage sweeping

from 0V to 200V in 5V steps. The current was measured at

each voltage step. The leakage current is quoted at 2 MV/cm.

The expected leakage current and break down voltages of

SiO2, Si3N4 and TEOS are 2.0E-9 A/cm2 and 4-10 MV/cm

respectively[29]. The results are shown in Table II.

TABLE II

LEAKAGE CURRENT AND BREAKDOWN VOLTAGES

Film

Type

Leakage Current

A/cm2

Breakdown

Voltage MV/cm

Dielectric

Constant

SiO2 2.26 × 10-9 10 4.71

Si3N4 2.26 × 10-9 6 6.73

TEOS 2.26 × 10-9 10 4.59

C. Dielectric Constants

In order to measure the dielectric constant of the SiO2, Si3N4

and TEOS a thickness of 2000nm was deposited on 200mm

low resistivity electrode [p-type, B-doped, 0.005-0.02 Ohm-

cm] silicon wafers. 2mm diameter Al dots were evaporated

through metal stencil mask to form a similar test structure

used for the voltage breakdown and leakage current tests. A

Keithley 2400 source-measure unit [SMU] was used as a bias

voltage supply [-200 to +200 V] and a Keithley 590 CV

analyzer was used for capacitance measurement. As in the

leakage current and breakdown voltage tests, the low

resistivity Si substrate formed the lower electrode.

Software-automated capacitance versus voltage measurement

K value can be determined from accumulation capacitance

using (1).

(1)

Where is the relative permittivity, is the permittivity of

free space, d is the film thickness, C is the measured

capacitance and A is the area of the evaporated aluminum dot

that forms the upper electrode. The results are shown in Table

II.

D. Combined Stress of the stacked Dielectric Layers

The combined stress (Sc) of the stacked dielectric layers

used in the optical stack can be determined by using (2),

)321(

)33()22(11

LTLTLT

LSLTLTLTLSLTSc

(2)

Where LT1 is the layer thickness of layer 1 and LS1 is the

layer stress of layer 1, and so on for layer 2 and 3. The layer

target thickness will be 2μm then,

MPaSc

Sc

166

)222(

)1402()2202(1402

As mentioned earlier it is desirable to have a compressive (-)

stress to prevent the formation of cracks in the deposited films.

Also if a tensile stress is present the film will be more prone to

crack. The level of stress also determines the thickness of

films that can be fabricated. The combined stress of layers of

stack 1 and 2 was identical at -166 MPa this is due to the SiO2

and TEOS having matching stress values. Although these

stacks are made of different materials a similar level of stress

was achieved by varying the deposition conditions to

effectively tune the inherent film stress [30-32]. If the films of

the optical stack are too thin then it will be prone to

mechanical damage. If they are too thick it will crack and this

will also degrade the optical properties.

A compressive stress of -166MPa is considered a good level

and suggests that the multi stack film will survive the etching

of the via [33, 34].

IV. OPTICAL ANALYSIS

A. Bayes-Spectral-Entropy-Based measure of focus using a

Discrete Cosine Function

The performance of the optical stacks was quantified against a

known reference, in this case an optical cover slip that was

0.1mm in thickness. The microscope used to image the

optical stack comprised of an Axiovert 135 inverted

microscope fitted with a x10 objective lens and EXi blue

monochrome fluorescence microscopy camera that utilized

1392 x 1040 pixels at a 6.4µm x 6.4µm pixel size. The

transmission illumination was from a halogen lamp at the top

input port. The camera exposure time and gain were controlled

manually. There were three sets of pictures imaged through

Stack 1, Stack 2 and the cover slip. A set of 20 images of a

human hair were taken stepping though a variance of focus

and then saved to a standard PC.

The images were then processed using a Bayes-Spectral-

Entropy-Based measure of focus using a Discrete Cosine .Aε

d.Cε

0

r



5

Function (DCT) this technique is used to evaluate the optical

performance of devices and optical films and lenses [35]. In

order to estimate the depth of focus, a small area at the same

coordinates for all the images in each set of approximately

200x200 pixels was selected in a Matlab routine. These sub

images were then transformed to their spectral representation

via a discrete cosine transform and a measure of the focus was

obtained. The assumption is that when a typical image is out

of focus its "measure" (amplitude) is less than when it is

focused, in terms of the Entropy Based optical quality

evaluation technique then the stacks have comparable or better

optical quality than a standard glass cover slip as shown in Fig

4. The image focus profiles for our stacks are comparable to

that of a glass cover slip.

Fig. 4. Focus Intensity Comparison between the optical stacks and a standard

glass slide

In addition we have the “best in focus” images of a human

hair of Stack 1 and a cover slip shown in Fig. 5

Fig. 5 Best in focus of a human hair. a) Stack 1 b) Glass Cover Slip

B. Reflectivity Measurement

The Spectroscopy hardware used to measure the reflectivity

consisted of a PC based Ocean Optics SpectraSuite®

spectroscopy software, an Ocean Optics USB2000+

Miniature Fiber Optic Spectrometer and an optical fiber

assembly terminated with a standard SMA connector. Light

from a halogen lamp was sampled using a 100mSec capture

time. Experimentally determined spectra were compared to

computational predictions using a transfer matrix approach

with layer thicknesses and wavelength dependent refractive

index values obtained from the wafer process results.

The simulation presented a reflectivity calculation from the

dielectric stack over the visible spectrum typically used

with confocal microscopy. The data from the Ocean Optics

SpectraSuite® was then plotted against this predicted

module as shown in Fig. 6.

Fig. 6. (a) Stack 2: experimental v simulation (b) Stack 1: experimental v

simulation

It can be seen that there is reasonable general agreement

between the experimental and simulated data. The differences

seen between simulated and actual results in the 400-525nm

range are due to the low levels of light intensity produced by

the halogen lamp at this frequency range as shown in Fig 7.

The spectrometer used was an Ocean Optics USB2000+

Miniature Fiber Optic Spectrometer that digitizes the response

of the CCD detector to incoming photons. Due to the

0.55

0.6

0.65

0.7

0.75

0.8

0.85

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Inte

nsit

y

Focus Position

Dielectric Stack_1

Dielectric Stack_2

Cover slip



6

limitation of acquisition system the low intensity at the 0-

525nm range caused poor signal to noise ratio within the

spectrometer.

Fig.7. The frequency spectrum of halogen lamp used in the reflectivity

measurement

The films that were deposited to measure the refractive indices

are single films and therefore the exact values of indices of the

individual layers within the stack cannot be measured

accurately. Similarly, the part of the substrate that was cleaved

in order to perform the SEM thickness measurements was in a

different area of the substrate used to perform the reflectivity

measurements and consequently the films non uniformity

could cause thickness variations.

Therefore an optimization algorithm was employed [36], to

iteratively refine film thicknesses to ensure an optimum fit

between measured and simulated intensities, and . The film thicknesses for the located minima

(i.e.

, where the tolerance ).

In both experiments is optimally matched to .

C. Testing the Optical Structure using Biological Cell lines

Optical stack 2 was tested for use within optical microscopy

by growing adherent lung epithelial cells (BEAS-2B) on the

surface of layer 3 (Si3N4), refer to fig 8 (a).

(a)

(b)

Fig. 8.(a) The optical stack tested using confocal microscopy. (b) LSM-710 laser scanning confocal microscope.

The lung cells were fluorescently labeled in specific spatial

locations with three fluorochromes of differing wavelength,

covering the visible spectrum (blue to red) and then imaged

with laser scanning confocal microscopy.

The substrate was first washed in 70/30 ethanol/H2O, and then

left soaking in this solution for a period of sixteen hours to

sterilize the growth surface prior to the addition of cells. This

is of particular interest from the materials standpoint as it not

only tested the physical strength of the optical stack but also

tested its moisture barrier properties. The substrate was then

washed three times with phosphate buffered saline (PBS) to

remove all traces of the alcohol and then placed in a Petri dish

containing 100% foetal bovine serum for 1 hour under aseptic

conditions.

The substrate was then transferred to a fresh Petri dish and

incubated at 37 °C, 5% CO2 for 12 hours with the BEAS-2B

cells to permit attachment. Cells were seeded at a

concentration of 4000 cells/cm2 in medium consisting of

Dulbecco’s Modified Eagle’s Medium (DMEM, D5796,

500mL available from Sigma Aldrich), supplemented with

10% foetal bovine serum, 1% Penicillin and Streptomycin. A

4nM concentration of quantum dot (QD) solution was

prepared by adding 4µl of 705nm emitting carboxylated

CdTe/ZnS quantum dot solution (Q21361MP, 250 µl @ 8µM,

Invitrogen), to 2 ml of the culture medium, and vortexed for 1

minute.

The existing cell medium covering the substrate was removed

and was replaced with this new QD loaded medium and

returned to the incubator for one hour to allow the quantum

dots to attach to the cells. The sample was then removed from

the incubator, the medium removed and the cells washed twice

with 4ml of PBS, to remove any stray, non-attached quantum

dots. The cells were then incubated at 37 °C, 5% CO2 in 2ml

of FACS FIX (1:10 BD Cell Fix:dH2O); enough to cover the

substrate. The FACS FIX was then removed and replaced with

4ml of PBS and placed in the fridge at 4 °C prior to

imaging. The sample was then washed with three changes of

Hank’s Buffered Salt Solution (HBSS, H6648, 500mL

available from Sigma Aldrich) prior to further fluorescent

labeling. The cell membranes were labeled with a wheat germ

agglutinin 555 Alexa Fluor® conjugate (WGA, W32464,

available from Life Technologies) at 5μg/mL in HBSS for 10

min in the dark. Cells were then covered with 10μL

0

0.2

0.4

0.6

0.8

1

1.2

300 500 700

No

rmal

ized

Inte

nsi

ty

Wavelength (nm)



7

glycerol/TRIS buffered mountant supplemented with 1μg/mL

Hoescht 33342 nuclear stain (H3570, available from Life

Technologies) and a coverslip was placed over the optical

stack.

Confocal microscopy was conducted from underneath through

the optical stack using a LSM-710 laser scanning confocal

microscope using a 20x and 40x Plan-Neofluor objectives and

ZEN software version 2009 (Carl-Zeiss) as shown in Fig 8 (b).

Fig. 9. shows images of the cells obtained with 20x and 40x

objectives.

(a)

(b) Fig. 9. Three color fluorescence micrographs of BEAS-2B cells labeled with Hoechst 33348 (blue; nucleus) WGA-555 (green; cell membrane) and q-

tracker 705nm (red; endosomes). Fluorescence image obtained with (a) 20x

objective, (b) 40x objective,

The optical quality of the dielectric stack and the access

geometry of the wafer via are such that excellent light

collection is obtained allowing high resolution imaging of the

cells with clear delineation of the nanoparticle loaded vesicles

(red channel), cell nucleus (blue channel) and membrane

structures (green channel).

V. CONCLUSIONS

There were several design constraints in the fabrication of this

structure. Firstly, the optical via etched through the substrate

needed to be large enough to accommodate a microscope

objective lens and possess vertical side walls to allow multiple

vias to be fabricated closely together. The required vertical

anisotropic etch was achieved by using the Bosch process

employing advanced DRIE techniques. Given such a large via

this also required the optical stack to possess the physical

properties to survive the etch process, traverse the whole of

the silicon wafer and physically remain intact to support the

analysis of biological cell lines. The dielectric layers within

the stack were enabled to be of the required strength by

depositing sufficiently thick layers at the desired levels of

compressive stress. This was accomplished by utilizing mixed

frequency and general process control techniques during the

PECVD deposition process. Conversely, the thickness of the

stack also needed to be kept as thin as possible to prevent

adverse optical attenuation. Consequently a layer thickness of

2μm was seen as compromise between physical strength and

optical performance. Efforts to improve the optical properties

by further reducing the differences between the refractive

indices of the dielectric layers were not attempted as any

further changes to the refractive index would have degraded

the film electrical characteristics. This holds especially true for

the Si3N4 as any reduction in refractive index would also

reduce its moisture barrier properties. However, attempting to

improve the refractive index matching whilst maintaining

good electrical properties does give the opportunity for a

separate program of work.

We have successfully fabricated an optical stack using

materials that are considered standard in the semiconductor

industry and incorporating design rules that are commonly

used in the fabrication of 0.35µm node CMOS devices. The

structure has the optical characteristics to enable excitation

light to pass through without any serious attenuation that could

prevent the microscope objective allowing analysis of the

biological specimen. This is clearly demonstrated by the

clarity of the images of the BEAS-2B cells produced by

scanning confocal microscopy techniques shown in Fig. 9.

Furthermore, it is hoped that by using the predictive MatLab

model the RI and dielectric layer thicknesses of standard

CMOS architectures could be modified to accommodate

specific wavelength particular to unique biotechnology

analytical techniques[37].

Utilizing the optical performance of what would be considered

standard dielectric layers that also have good electrical

performance is a novel approach to LoC applications.

Benefits of this design methodology include significantly

reducing the cost of LoC fabrication techniques and enabling

the adaptation of a LoC devices to different applications. This

clearly makes a large advancement on the current state-of-the-

art possible where silicon ICs have been adopted for biologic

applications including cell sorting but suffer from the

requirement that after sorting cells are removed from the chip

for detailed analysis preventing full in-situ experimentation



8

and exposing the cells to possible damage or contamination.

This platform will allow single cells or other particles of

interest to be positioned over the optical windows after sorting

‘on-chip’ and studied by biologists ‘in-situ’ on their most

favored analytical tools such as standard inverted microscope

platforms. The use of the CMOS architecture also allows

interesting possibilities to add further sensing functions in

tandem on the chip (resistance, capacitance, magnetic and

optical) to expand the biological insights gained from

analysis of the sample.

This research is ongoing and funded by the Engineering and

Physical Science Research Council (EPSRC) First grant

scheme; grant number EP/I038799/1.

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