designing with finfets

White Paper

Designing with FinFETs: The Opportunities and the Challenges

Author

Jamil Kawa

R&D Group Director,

Synopsys, Inc

IntroductionWith the help of double-patterning and other advanced lithography techniques, CMOS technology

continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs

are replacing planar FETs (also called “planar CMOS”) as the device technology of choice at these

advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage

and dynamic power, intra-die variability, and retention voltage for SRAMs.

FinFET devices have a significantly more complex topology than planar FET devices. In addition, their

design features and characteristics are quite different, creating many questions for designers. For

example,

`` How much of the cumulative experience in planar FET design is applicable and transferrable to

FinFET design? Can design flows and methodologies painstakingly developed over tens of years

be reused? Or are we dealing with a radical change in design methodology?

`` Are EDA tools ready for this transition? To what extent can they be ready, given the industry’s

limited experience with FinFET as a device?

`` Given the complex device models of the FinFET and of its associated parasitics, can designers

(and analog designers in particular) rely on such device models as good predictors for designing

robust circuits?

The list of questions goes on and all represent relevant issues that have to be addressed by foundries and

EDA companies to minimize or avoid design pitfalls and costly iterations.

A superficial view of the custom design flow, especially as far as the design implementation steps are

concerned, could lead one to conclude that the transition from planar FET to FinFET will be seamless

and transparent to the designer. But the impact the FinFET device has on the design flow can be quite

significant.

What does that mean for the designer? Most likely, a longer and steeper learning curve than what is

typical in a transition from one planer technology node to the next, as shown in Figure 1. In fact, the

learning curve has already been expanding with each new planar node as a result of new lithography

artifacts such as restricted design rules (RDR) and double patterning. The jump in complexity with FinFET

is even more pronounced.

September 2012

Designing with FinFETs: The Opportunities and the Challenges 2

FinFET: The DeviceFigures 2 and 3 are simplified depictions of a planar FET and a FinFET, respectively. In the planar FET, a single

gate controls the source–drain channel. Such a gate does not have good electrostatic field control away from

the surface of the channel next to the gate, and as a result leakage currents between source and drain happen

even when the gate is “off”.

By contrast, in the FinFET, the transistor channel is a thin vertical fin with the gate fully “wrapped” around the

channel formed between the source and the drain. The gate of the FinFET can be thought of as a “multiple

gate” surrounding the thin channel. Such a gate can fully deplete the channels of carriers. This results in much

better electrostatic control of the channel and thus better electrical characteristics. The thin body of the fin

is a requirement to ensure that the wrapped gate has complete control of the channel. Figures 2 and 3 show

“bulk” planar and FinFET transistors. It is worth noting that fins can be formed on silicon-on-insulator (SOI)

structures as well.

The most important geometric parameters of a FinFET are its height (HFIN), its width or body thickness (Tsi), and

its channel length (Lg). Figure 4 demonstrates those parameters. The effective electrical width of a FinFET is the

planar width/body thickness Tsi plus twice the fin height HFIN.

28nm and below

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Figure 1: Learning curve progression as a function of technology node

Figure 2: Planar FET Figure 3: FinFET


A simplified representation of the key stages in the process of manufacturing FinFET structures is shown in

Figures 5, 6, and 7.

The definition of the active device areas is shown as the blue mandrels, or temporary supporting structures.

The fins (red) are formed by etching the mandrels (Figure 5). Then a cut mask is used to remove the unwanted

parts of the structure (Figure 6) leaving the final pattern (Figure 7).

Given that FinFET technology will be implemented at 20-nm or smaller geometries, double patterning

techniques will be needed for all critical layers. A “spacer double patterning” is usually the preferred technique

for patterning the fins.

At any one technology node, the FinFET has several advantages over its planar counterpart including (but not

limited to):

`` Very good electrostatic control of the channel. The channel can be “choked off” more easily. FinFETs

boast a near-ideal sub-threshold behavior (associated to leakage), something that’s not easy to

achieve in planar technology without considerable design effort.

`` Greatly reduced short channel effects (an effect that takes place when the channel length is the same

order of magnitude as the depletion-layer widths of the source and drain junction, making the specific

transistor behave differently from standard longer channel transistors). The short channel effects in

planar technology are complex and give rise to a large impact on gate length variations and therefore

on electrical performance.

`` High integration density, or 3D. Thanks to the vertical channel orientation of FinFETs, they deliver

more performance per linear “W” than planar even after the isolation dead-area between the fins is

taken into account.

`` Smaller variability, especially variability resulting from random dopant fluctuation primarily due

to doping-free channels. Also, variability associated with line-edge roughness (LER), the random

deviation of gate line edges from the intended ideal shape, which results in non-uniform channel

lengths, is lower in FinFETs

y Undoped or lightly doped channel: much lower dopant concentrations are necessary in the channel

region.

y Gate definition: the gate is defined from the top of the fin. The dominant part of the gate is defined

by etching processes, which have very low LER

“FinFET”(90ο rotation)

Source

Gate

Drain

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Fin width = TSi

Source

Drain Gate Lg

Fin heightHFIN = W/2

Figure 4: FinFET geometric parameters. Dimensions are not to scale

Figure 5: Mandrels Figure 6: Cut mask Figure 7: Patterned structures


The FinFET as an Opportunity for IP DesignThe desire to optimize the design metrics of performance, power, area, cost, and time to market (opportunity

cost) has not changed since the inception of the IC industry. In fact, Moore’s Law is all about optimizing those

parameters. However, as scaling of manufacturing nodes progressed towards 20-nm, some of the device

parameters could not be scaled any further, especially the power supply voltage, the dominant factor in

determining dynamic power. And optimizing for one variable such as performance automatically translated into

big compromises in other areas, like power.

Another limitation as processes approached 20-nm was the fact that lithography was stuck at ArF illumination

source with a wavelength of 193nm while the process-critical feature was pushing sub-20nm. Optical

innovations such as immersion lithography and double-patterning made that possible, but at the cost of

increased variability.

There were also other innovations along the way such as high-K metal gate that alleviated – to a limited

extent – gate leakage problems. But the fact remained that the design window for optimizing among the

aforementioned design variables was shrinking.

Designing in FinFET broadens the design window once again. Operating voltage continues to scale down,

significantly saving on dynamic and static power. Short channel effects are reduced significantly, reducing

the guard-banding needed to deal with variability. And performance continues to improve compared to planar

at an identical node. In fact, at very low power supply voltages, the performance advantage of the FinFET

compared to its planar equivalent widens due to the superior gate control of the channel in the FinFET.

For memory designers, an added advantage of FinFETs is the significantly lower retention voltage

requirements of FinFET-based SRAMs compared to planar FETs.

Given the emerging metric of performance per unit power (Koomey’s Law), one major design optimization

benefit of FinFET compared to planar is much higher performance at the same power budget, or equal

performance at a much lower power budget. This essentially gives designers the ability to extract the highest

performance for the lowest power, a critical optimization for battery-powered devices.

One feature that makes the transition from designing with planar FETs to designing with FinFETs a little less

complex is the fact that the back-end of the process is essentially the same, and therefore the part of the

design flow associated with the physical implementation remains intact.

FinFET Design: The ChallengesWhile FinFETs offer many advantages, the FinFET is a significantly more complex device to model. Both

accurate FinFET parasitic extraction and generation of good yet compact SPICE models is more challenging

with FinFETs than with planar devices. For most design activities, the aforementioned complexities are

transparent to the designer. However, there still remain many design optimization challenges for the circuit

designer who wants to utilize FinFET technology.

The FinFET has a lower DIBL / SS (sub-threshold swing) that is a desirable characteristic as far as leakage is

concerned. However, that behavior translates to a larger design-induced body biasing to achieve the same Ioff

reduction possible in planar. Body biasing techniques commonly used in planar FETs lose their effectiveness

and alternatives are needed.

The finite granularity of the fin width and the limited range of freedom in channel length for a given architecture

render optimizing analog as well as digital design more complex. Though many fins can be “ganged” together

to generate a desired fin width, the length and width are not completely free parameters. This is because

FinFETs are 3D structures, and controlling etch variability for the high-aspect ratio processes with non-uniform

pitches or locally varying pitches can be a problem. Thus FinFETs have a significant numbers of restricted

design rules (RDR).


For SRAM design, optimizing the beta (β) ratio of a bit-cell is more difficult as W is quantized, and the flexibility

in L as a tuning parameter is limited. Practically speaking, a β of “1” or “2” are the two available choices. That

in turn translates to the need for more advanced assist techniques to enhance SRAM yield.

A less tangible yet crucial challenge, especially for the analog designer, is the close association between

physical layout and circuit behavior. It is an iterative, painstaking process with no alternative (yet). This has to

do with the complex parasitics of the FinFET device. Using a model to design and simulate and then fine-tune

the finished circuit after the layout is extracted might not work. The discrepancy between the model-generated

circuit and the realized one might be too wide to bridge with minor adjustments. This is an area where

enhancements in tools and an extended experience in design is critical to minimize the impact of this issue.

Finally, a physics-based challenge is the reliability concerns in the form of NBTI and PBTI aging that alters the

behavior of the device. Experience in the area for FinFET devices is also crucial for design success.

TCAD and EDA Tool Readiness: The FinFET design process encompasses a complex ecosystem that, for the most part, is similar to that of

planar CMOS design. However, FinFET design differs in complexity in some specific steps in the process.

Figure 8 highlights the key tools directly impacted by FinFET technology and their relationship to each other.

The TCAD part includes elaborate and extensive front-end 3D simulation and modeling of the device behavior.

In the area of process modeling, the high-aspect ratio etching/deposition (topography) of FinFETs poses an

added depth of analysis. Traditionally in TCAD, these processes have not been modeled, and have just been

approximated geometrically. With the higher aspect ratio etching/deposition steps, there is growing interest

in physical simulation of topography. 2D process modeling can be used for the fin generation process, but to

really capture more complex behavior and proximity effects, 3D simulation is needed.

In the area of device modeling, device simulation needs to capture effects of new surface orientation,

surface scattering effects, quasi-ballistic transport, and corner effects. Mobility models need to adapted and

recalibrated.

Also, TCAD tools perform accurate 3D modeling of the FinFET device that addresses layout proximity effects,

topology and architecture stress dependencies, as well as electromigration. It usually has its direct links to the

RC extraction engine and to the BSIM spice modeling arm of the simulators.

HSPICECustomSim IP

Sentaurus Proteus

StarRC CustomDesigner

IC Validator GalaxyImplementation

Figure 8: EDA eco-system


An example of critical 3D simulations is that of stress profiles for various layout patterns and STI etch patterns.

Layout dependency of mobility (stress induced) is a known phenomenon in planar CMOS that is more

exacerbated in FinFET due to the 3D nature of fins and the STI etch profile. The proximity of adjacent fins,

or lack thereof for end of line fins, and the depth of the etch (STI) between them are two critical parameters

in FinFET.

SPICE Models: The traditional SPICE models used for planar devices don’t work sufficiently well. Berkeley

provides a BSIM-CMG (common multi-gate) model that is able to model FinFETs (double-gate, multi-gate) as

well as gate all around (GAA) devices, which are transistors with the channel completely surrounded by the

gate, for example nanowires or pillar transistors.

Also, new reliability concerns such as NBTI / PBTI call for accurate aging and end-of-life (EOL) models that

accurately reflect the behavior of devices under specific bias conditions over specified time spans.

Device Model (Parasitics): The FinFET parasitics device model is significantly more complex than its planar

counterpart. A typical FinFET device model is shown in Figure 10.

RC Circuit Parasitics Models: Efficient yet accurate RC models are needed to handle the increasingly more

complex parasitics associated with FinFET-based circuits.

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Figure 9: Stress simulation of FinFETs

Figure 10: Parasitics model of the FinFET


OPC/LITHO: Patterning and corresponding challenges from an OPC/MDP point of view are not expected to

be fundamentally different from planar patterning, apart from the fin generation process, which is currently

seen as generating a “corrugated substrate.” Spacer patterning is preferential, since the fins are sensitive to

thickness variations. Support of DPT coloring and decomposition compliance checking is no different than

that of all advanced nodes using DPT.

From a physical layout perspective, FinFET design has a disproportionate number of RDR. Lithography is

only one reason for the RDR. The fin patterning/formation process, with the high aspect ratio etches and

the fragility of the fins under the high stress necessary for mobility enhancements, are further factors driving

towards high restrictions.

Layout & Design Database Tools: Existing schematics and layout tools must be enhanced and re-

architected with maximum productivity in mind. It must be a design rule-driven layout platform that

dynamically interacts with simulators and with verification and data preparation tools. The tools must

concurrently check hundreds of rules in real-time and provide error visualization.

Extraction, Simulation, and Verification: With the exception of simulation packages that can efficiently

handle aging and EOL simulations, there are no major changes impacting the extraction, simulation, and

verification part of the EDA ecosystem for FinFETs. However, given the dramatic increase in the complexity of

device and of parasitics models, efficient yet accurate extraction, simulation, and verification techniques are

needed to handle the dramatically larger databases.

Low Power Design: FinFET technology will extend the available options for power system designers by

providing more options for performance versus leakage tradeoffs. FinFET-based design will have more

on-chip power gating and wider use of dynamic voltage frequency scaling (DVFS) as designers strive to

maximize performance per mW. Current techniques and design flows will evolve to accommodate this. FinFET

technology provides a performance advantage at any operating voltage. As shown in Figure 11, this advantage

is even wider at lower supply voltages, making FinFET technology ideal for low power and low operating

voltage applications.

So, while it may appear there is hardly any change in the back-end of the EDA eco-system for FinFET design,

the truth is that significant enhancements have been introduced to all the associated engines to efficiently and

accurately handle the disproportionately larger databases back-end tools have to handle.

32 nmPlanar

18%Faster

37%Faster

22nmTri-Gate

Figure 11: Intel’s 22nm tri-gate technology showing the wider performance advantage at lower VDD

*Source Mark Bhor, Intel, 2011

Synopsys, Inc. y 700 East Middlefield Road y Mountain View, CA 94043 y www.synopsys.com

©2012 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is available at http://www.synopsys.com/copyright.html. All other names mentioned herein are trademarks or registered trademarks of their respective owners.

09/12.RP.CS1202.

Summary and ConclusionsFinFET device technology in all its flavors is the most promising device technology for extending Moore’s Law

all the way down to 5-nm. It is fully compatible with CMOS in both bulk and SOI varieties. It offers excellent

solutions to the problems of sub-threshold leakage, poor short-channel electrostatic behavior, and high

device parameters variability that plagued planar CMOS as it scaled towards 20-nm. Furthermore, it offers the

ability to operate at much lower supply voltages and extends voltage scaling, which was leveling off in CMOS

devices, and allows further static and dynamic power savings. Also, FinFET technology is fully compatible with

the CMOS back-end design processes, reducing the need for new, FinFET-specific developments in that area.

However, no new technology is completely free of risk or challenges. FinFET devices have a significant amount

of parasitics that need to be modeled precisely, and carefully considered in the layout of all circuits, especially

analog circuits. From a circuit design aspect, in addition to the extra effort needed to attend to the impact of

parasitics at the layout step, new circuit techniques are needed in the area of body-biasing and read/write

aspect to replace techniques that worked well in planar but are inefficient for FinFET.

On balance, FinFET technology offers a bright future of device scaling and is an indispensable technology

for designing the next generation of high performance and power sensitive applications ranging from mobile

smart phones to enterprise computing and networking. The technology introduces new design challenges that

can be properly addressed with the growing knowledge and experience of designing with FinFETs to ensure

design success and a differentiated end product.

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