design and simulation tools for rf, power and signal...

Design and Simulation Tools forRF, Power and Signal Integrity

Pratik KhuranaEEsof EDAKeysight Technologies

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Why Simulation? What is the Value?

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Simulation allow the user to observe the impact of their choiceswithout the outcome having any impact on the real operation andpredicts the functionality

Without Simulation:Learn from Try and Error

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Electronic Design Automation (EDA)

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IDEA

CONCEPT | DESIGN

PRODUCT

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Keysight EEsof EDA : Design flow ProposalSystem, Analog, HSD, RF/MW, EM, EMI/EMC Analysis and integration with third party tools up to final Test

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System simulation:Baseband, RF/MW

Communication systems,Radar

System simulation:Baseband, RF/MW

Communication systems,Radar

Circuit simulation:Analog, Signal Integrity,

RF/MW

Circuit simulation:Analog, Signal Integrity,

RF/MW Physical Design:Layout

Physical Design:Layout Physical analysis:

EM, SI/PI, EMI/EMC &Electro-Thermal

Simulation

Physical analysis:EM, SI/PI, EMI/EMC &

Electro-ThermalSimulation

Verification & TestVerification & Test

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Converting Concept to Product

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SystemConcept

RFICDesign &Module

RF BoardIntegration

Packaging,Antenna

FinalProduct

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Converting Concept to ProductKeysight EDA Software help

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SystemConcept

RFICDesign &Module

RF BoardIntegration

Packaging,Antenna

FinalProduct

PageOutline

– System Level Electronic Design with SystemVue

– RF Board Design with ADS, EMPro and Genesys

• Impedance Matching Application

– PCB Signal Integrity & Power Integrityconsideration with ADS, SIPro and PIPro

• Signal Integrity

• Power Integrity

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What is SystemVue?System-level design cockpit, focused on Communications

#2 SystemVue providesan implementation path to

FPGA/DSP hardware

#3 SystemVue enables cross-domain verification, connecting Basebandalgorithm to RF tools, Standards references, and Test & Measurement.

#1 SystemVue models Physical Layer (PHY) architecturesacross multiple Baseband & RF domains, for better system designs

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Validate Comms before/after R&D commitmentsTransition naturally from DesignTest with a single “cockpit”

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RF / AnalogChannel Modeling

MIMO Channel (OTA)Digital Pre-Distortion (DPD)RF System DesignRF EDA platforms

Test EquipmentRF Sources & AnalyzersAWG & DigitizersScopes, Logic, Modular

Test SoftwareI/O Lib, ComExpert89600 VSASignal Studio3rd Party

BB AlgorithmModeling

MATLAB .mFixedPoint, HDL/FPGAEmbedded C++Filtering, EQ, Modem

IP Reference Libraries4G LTE-Advanced, LTE3G HSPA+, WCDMA, etcWLAN 802.11ac/n/a/WPAN 802.11ad, 802.15.3c

BASEBANDMODELINGBASEBANDMODELING

STANDARDSREFERENCESSTANDARDS

REFERENCES

RF SYSTEMMODELINGRF SYSTEMMODELING

LINKS TOREAL WORLD,

HARDWARE TEST

LINKS TOREAL WORLD,

HARDWARE TEST

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Validate Comms before/after R&D commitmentsTransition naturally from DesignTest with a single “cockpit”

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Quickly capture “system level”design concepts

Model implementation-levelimpairments

Connect BB, RF, and T&Mfor rapid validation

Rapid prototyping withintegrated measurement

RF / AnalogChannel Modeling

MIMO Channel (OTA)Digital Pre-Distortion (DPD)RF System DesignRF EDA platforms

Test EquipmentRF Sources & AnalyzersAWG & DigitizersScopes, Logic, Modular

Test SoftwareI/O Lib, ComExpert89600 VSASignal Studio3rd Party

BB AlgorithmModeling

MATLAB .mFixedPoint, HDL/FPGAEmbedded C++Filtering, EQ, Modem

IP Reference Libraries4G LTE-Advanced, LTE3G HSPA+, WCDMA, EDGE, GSMWLAN 802.11ac/n/a/b/gWPAN 802.11ad, 802.15.3c

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Who uses SystemVue?

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System Architects•Simple and easy model based design workflow•Multi-domain modeling for RF, baseband, and algorithms•Fast link level analysis of Layer 1 systems

System Architects•Simple and easy model based design workflow•Multi-domain modeling for RF, baseband, and algorithms•Fast link level analysis of Layer 1 systems

Baseband Architects & Algorithm Developers• Multi-language Modeling• Target Neutral IP development• Cross domain debugging of IP

Baseband Architects & Algorithm Developers• Multi-language Modeling• Target Neutral IP development• Cross domain debugging of IP

RF System Architects• Accurate models and analysis in native Frequency domain• Flow integrity with circuit level design (ADS)• Integration with vector modulation analysis

RF System Architects• Accurate models and analysis in native Frequency domain• Flow integrity with circuit level design (ADS)• Integration with vector modulation analysis

Embedded FPGA and DSP HW Designers•Advanced analysis and heuristics for fixed point systems•Link algorithms to HW in common formats•Structured verification from design to implementation

Embedded FPGA and DSP HW Designers•Advanced analysis and heuristics for fixed point systems•Link algorithms to HW in common formats•Structured verification from design to implementation

System Verifiers•Use “measurement-grade” reference IP, or create custom signals•Verify system block level interoperability at all levels of H/W abstraction•IP aggregation, including both BB and RF Systems

System Verifiers•Use “measurement-grade” reference IP, or create custom signals•Verify system block level interoperability at all levels of H/W abstraction•IP aggregation, including both BB and RF Systems

Typical DesignOrganization

1010 10110110 00101100 0110

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MATLAB Script, for in-line algorithm modelingFamiliar use model, without leaving SystemVue

WORKSPACETREE

COMMANDPROMPT

WORKSPACEVARS

MATLAB Script• 100% consistent with

retail MATLAB• 1-click toggle to switch

to your own locallylicensed MATLAB

• Leverage your librariesand toolboxes fromwithin SystemVue

• Included with baseW1461 SystemVueenvironment

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SystemVue FPGA Design Flow

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SYSTEMLEVEL

FIXEDPOINT

RTL VHDL/VerilogFile HierarchyVHDL/VerilogFile Hierarchy

Co-sim WrapperAldec Riviera-PRO

VHDL/VerilogFile HierarchyVHDL/VerilogFile Hierarchy

Co-sim WrapperMentor ModelSim

Riviera-PROHDL simulation

UI, LibrariesSimulation

VisualizationDebugger

Riviera-PROHDL simulation



ModelSimHDL simulation



ModelSimHDL simulation



POLYMORPHIC MODEL

Xilinx ISEIP, Place &

Route, Synthesis

Xilinx ISEIP, Place &

Route, Synthesis

VirtexVirtex

FPGA

Hardware in-the-Loop (HIL)

StratixIV/V

StratixIV/V

CycloneIV

CycloneIV

Altera Quartus IIIP, Place & Route,

Synthesis

Altera Quartus IIIP, Place & Route,

Synthesis

SystemVue Demo

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Result: An integrated, tops-down design flowCross-domain model-based design: RF, Comms, and C++/HDL

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.bitFiles

FPGASynthesis

FPGASynthesis

FPGA Target

REAL HARDWARE

HDL Simulator(s)

SIMULATED H/W

Dataflow Simulation

.m/C++ ALGORITHMHandwrittenHDL

Custom IP

AlgorithmsC++, .m

MEASUREMENT, ANALYSIS

VSA softwareFlexDCA software

DIGITAL BITS, or MODULATED CARRIERS

MXG / ESG

Infiniium Scope

Logic Analyzer

MXA / PXA

Wideband AWG RF sensor

Target-neutralHDL Generation

System designRF Architecture

Baseband designPHY Reference

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• Power Integrity

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RF Board DesignFront-end & Back-end design with ADS

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Schematic entry & simulation

• Tuning, Optimisation, Monte Carlo

Layout editing

3D Electromagnetic Co-simulation

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ADS - Advanced Design System

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ADS helps designers fully characterize,optimize and produce designs.

• Schematic Entry• RF Layout and Verification• Data Display and Post Processing• Industry leading simulation technology• Tuning/Optimization & Statistical

design• 3D planar & full 3D EM field solvers• Best and broadest selection of

Foundry developed PDKs & SMDlibraries

• Design Flow Integration with Cadence,Mentor, Zuken, Intercept, …

• X-parameter model generation fromcircuit schematic and Keysight'sNVNA

• Wireless Libraries enable design andverification of designs to emergingwireless standards

Premier High-Frequency & High-Speed Design Platform

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Front End Design – SimulationIndustry leading simulation technology to enable first-passdesign success.

Capabilities

Multi-LayerInterconnect

LibraryMomentum

AdvancedModel

ComposerFEM

Phy

sica

l

Ptolemy Timed Dataflow System

Transient

AC S-Parameters

Num

eric

Tim

eF

requ

ency

Channel

HarmonicBalance

ConvolutionCircuit

Envelope

Keysight EEsof EDA19

SpectraSys

What IF

X-ParameterSimulation and ModelGeneration

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ADS & EMPro RF Design Environment

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AMDS

ADS Platform

FDTDSimulator

Finite DifferenceTime Domain

FEMSimulatorFinite Element Method

MomentumSimulator

Method of Moments

EMPro Environment

EMDS

Electromagnetic Co-simulation

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EMPro – ADS Common DatabaseIntegration improves your productivity.

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EMPro 3D Design

Common DatabaseADS Layout (3D View)

ADS Schematic

• EMPro projects now saved as ADS libraries• 3D models now directly available in ADS as schematic and layout views• Changes made in EMPro dynamically update in ADS• Parameters created in EMPro available in ADS for EM sweep/optimization

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EMPro 3D EM Modeling Environment

• Interactive, Intuitive, Efficient,3DEM design Environment

• Full Wave 3D EM FEM and FDTDSimulation Technologies

• Parameterize 3D EM componentsfor co-simulation & optimization inADS

• Transfer ADS Layouts to EMPro foradditional 3D-EM simulation

• Full scripting (Python) andparameterization capability

• Windows & Linux

Advanced 3D Modeling Tools

Revolve

Twist

Draft By Angle Draft By Law

Hole w/wo Draft Hole Special

Chamfer Edges Blend Edges

Shell

Loft Faces

• Quickly create common shapes

• Easily parameterized and modified from thestandard parts tree

Geometry Building Blocks

• Use materials from the default library, or create your own

• Simply drag and drop material definitions onto parts

• Support for complex permittivity materials

Material Definitions and Assignments

Default Library

Importing CAD Files in EMPro

• EMPro allows import of various industry standard CAD formats

Supported CAD formats

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Impedance Matching Application

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Designing with Off-The-Shelf components For IoT

Customizable in Footer 28

Impedance Matching for Sub 1GHz Frequency (Sub 1 GHz) and NarrowBandwidth (200 kHz), e.g. ZigBee, SIGFOX, LoRa, Weightless

ImpedanceMatchingChipset Antenna IoT Module

Matching Chipset to AntennaMatching Chipset to Antenna

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Designing with Off-The-Shelf components For IoT

Customizable in Footer 29

Impedance Matching for 802.15.4 Frequency (2.4 GHz) and BroaderBandwidth (20MHz)

ImpedanceMatching

Chipset Amplifier IoT ModuleImpedanceMatching Antenna

Matching Chipset to Amplifier to AntennaMatching Chipset to Amplifier to Antenna

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Impedance Matching Network DesignIncreasing Levels of Difficulty

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Zsource Zload

MatchingNetwork

1-Stage

Zsource Zload

InputMatching Network

OutputMatching Network

2-Stage

Antenna

Zload

InterstageMatchingNetwork

InputMatchingNetwork

OutputMatchingNetwork

3-Stage

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Automatic Impedance Matching Synthesis

IMS 2016 MicroApps

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Quickly design impedance matching for economicand practical implementation

1. Define Freq andBW to doImpedance Match

2. Browse to S-, X or Sys-parameters of Chip, Amplifier andAntenna that needs matching

3. Select matching topology-simpler is cheaper to realize

4. Matchingnetworkssynthesizedin seconds

5. Quality ofmatch isautomaticallyoptimized

6. Experiment withlumnped / distributedmatching for economy

A New cohesiveflow for Signal &Power Integrity

PageOutline






• Power Integrity

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ADS: SIPro and PIProA Cohesive Workflow for SI and PI Analyses

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4 New EM Simulators

Layout

Manage nets, VRMs, sinks,components

Set up and run analyses

3D layout view and resultsvisualization

PI-DCIR Drop

PI-ACPDN Impedance

Power PlaneResonances

Power-Aware SignalIntegrity

Layout Import into ADS(Direct *.brd Import, Allegro ADFI

or ODB++ flow)

Layout Import into ADS(Direct *.brd Import, Allegro ADFI

or ODB++ flow)SIPro / PIPro AnalysisSIPro / PIPro Analysis

Transient ConvolutionChannel SimDDR Bus Sim

Transient ConvolutionChannel SimDDR Bus Sim

ADS Schematic

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Increased Productivity for Post-layout AnalysisSeamless flow from EM-analyses back into schematic for both SI and PI

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Decap Tuning, Optimization,Circuit-level VRM modeling

PDN Impedance

I/Oports

AutomatedTest BenchGeneration

S-parameter Extraction

AutomatedSub-circuitGeneration

Data with VCC Bounce

SSN Analysis

Channel simulationand

Transient simulation

AndMore

Simulation!

DDR4Low BERSimulation

ComplianceTest

PageOutline






• Power Integrity

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SIProSimulation Technology Overview

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6/3/2016

A composite technology of fast FEM + Planar EM

Power-AwareSignal Integrity

Power-AwareSignal Integrity

• Speed and Accuracy

A purely EM-based simulation, capturing more EMeffects than 2D-hybrid solutions

• SI-specific, net-driven use-model and flow

• Easily plot Transmission, Return loss, Xtalkand TDR/TDT

• Automatic-schematic generation

EM model flows back to schematic ready for furthersimulation with Transient, Channel Sim, DDR BusSim and more

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SIPro: Speed and Accuracy

Customizable in Footer

Xilinx KCU105 FPGA Platform Board

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– Example : SFP (Small Form Factor Pluggable) TX channel

– SIPro finished in 18 min, a fraction of simulation time compared to FEM

• SIPro: 1GB memory, 6 secs per frequency point

• FEM:8GB memory, 12 mins per point

Very good agreement!

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SIPro: Accuracy

Customizable in Footer

DDR4 DQ Channel, Measured vs SIPro

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– 28-layer Xilinx UC1650B DDR4 memory characterization board– DDR4_C2_DQ4 single ended line (cookie cut)

DDR4_C2_DQ4, Single Ended

2431 mil path length(~4.12λ @ 20GHz or 2λ with Er=4)

Red = SIPro Black = Measured

Measurement: Courtesyof GigaTest Labs

Er as specified bythe designer,not ‘as fabricated’

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SIPro: SI-specific use-model and flowLayout to results in less than 20 clicks…

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6/3/2016

– No layout simplificationrequired!

– Net-driven

– Guided port creation

– Quickly plot all crosstalkelements from the samecomponent

– Easily plotTDR/TDT

– Mixed-modeS-parameters

PageOutline






• Power Integrity

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The Power Distribution Network

Roles of the PDN (Source: “Signal and Power Integrity – Simplified”, Second Edition, Eric Bogatin)

– Keep a constant supply voltage on the pads of the chips, from DC up to the bandwidth ofthe switching current.

– Carry the return currents for the signal lines and avoid these overlap. The latter causesground bounce or simultaneous switching noise (SSN).

– Seen the PDN has the largest size, carries the highest currents including HF noise, it hasthe potential of creating most radiated emissions.

HSD2 - PIPro Hands-on

Why doing a PDN analysis?

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Power Rail

Ground Rail

1.2VSinks

1.189V

0.002V

VRM

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PIPro

HSD4

Simulation Technology Overview

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6/3/2016

PIPro has an efficient net-driven PI analysis setup with 3 new simulator engines

PI-DCIR Drop

PI-ACPDN Impedance

Power PlaneResonances

• Speed and Accuracy

• PI-specific net-driven use-model and flow

• Change decap values/models withoutneeding to re-simulate

• Automatic-schematic generation

EM model flows back to schematic ready forfurther simulation with behavioral and circuit-level simulations of VRMs, sinks and more

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PIPro: Accuracy

HSD4

Customer validated test-case, Simulation vs.Measured Data

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6/3/2016

10-2

10-1

100

10-2

10-1

100

101

102

Frequency [GHz]

Z11

[O

hm]

measurementPiPro

10-2

10-1

100

10-2

10-1

100

101

Frequency [GHz]

Z11

[O

hm]

measurementPiProPIPro PIPro

Bare-Board PDN populated with Decaps

Test case:ATE test card – PDN traverses many layers

Customer used ideal capvalues with no ESR specified,hence sharp resonances.

Ideal VRM model.Customer did not have IC data.

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Designed for Usability

– Filter by Net

– Filter by Component

– Right-click to add-to-analysis

– Drag & Drop

– Hierarchical search forcomplex selections

– Context sensitive menuse.g. ‘Select instancesconnected to ONLY theselected nets’

HSD4 45

6/3/2016

Filters

Contextsensitive menus

Easily copysetups from one

analysis toanother

Color codedNets

3D Layout View

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VRM: U41.2 V

Sink : U631.1479 V

Vdrop= 53 mV

Sink : U621.14745 V

Vdrop= 52 mV

Sink : U611.14747 V

Vdrop= 52 mV

Sink : U601.14755 V

Vdrop= 52 mV

PIPro – DC IR Drop

Xilinx KCU105 – VCC1V2 PDN

Power Dissipationand Current Densityvisualization

Voltage and current reported per Via, Sink, VRMand more!

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PIPro – AC PDN Impedance Analysis

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Voltage, current and Power Loss Density Plots

+ Full scripting support for setup, simulation and post-processing

Easy setup:Filter, drag and DropComponents

Component Model assignment:• Lumped• SnP• Murata• Samsung• TDK• Create custom parts from

Schematic models

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PIPro – AC PDN Impedance AnalysisDecap Selection in PIPro

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Voltage, current and Power Loss Density PlotsAnalyze effect of decap

model changes without anyneed to re-simulate

Original PDNImpedance

New ModelSelected

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PIPro – AC PDN Impedance AnalysisDecap tuning from schematic

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Values Tuning

Dec

aps

One

Gro

up o

f Dec

aps

PCB Model

VRM Choke

VRM

Memory-1

Controller

Memory-2

Memory-3

Memory-4

Completelyflexible PDNoptimizationstrategy

Top-level Model

From PIPro

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PIPro – Power Plane Resonance AnalysisSelf resonances

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Analyze self-resonancesof the PCB and inspecttrouble areas that have thehighest field strength

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Keysight EEsof EDAYour software partner for IoT development

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SystemConcept

RFICDesign &Module

RF BoardIntegration

Packaging,Antenna

FinalProduct

design and simulation tools for rf, power and signal...

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