design and optimization of buck and double buck converters by means of geometric programming

Available online at www.sciencedirect.com

Mathematics and Computers in Simulation 82 (2012) 1516–1530

Original article

Design and optimization of buck and double buck converters bymeans of geometric programming

R. Leyva a,∗, U. Ribes-Mallada a, P. Garces a, J.F. Reynaud b

a DEEEA, Universitat Rovira i Virgili, Av. Paisos Catalans, 26, 43007 Tarragona, Spainb Laboratory for Analysis and Architecture of Systems, CNRS, Toulouse, France

Received 17 October 2011; received in revised form 7 February 2012; accepted 7 March 2012Available online 3 April 2012

Abstract

This paper describes a new method for determining the optimal components values and switching frequencies of buck DC–DCconverters. First, we revisit some concepts of the optimization technique named geometric programming. Then, we observe that theproblem of converter designing can be modeled by means of an objective function and certain constraints which can be written ina specific form known as the posynomial form. The constraints involve expressions that depend on magnitudes such as efficiency,bandwidth, and current and voltage ripples.

Specifically, we apply the design method in a synchronous buck converter and a synchronous cascade buck converter. Thistechnique can efficiently determine the optimal sizing of the converter or the infeasibility of the set of design constraints in a quicklymanner and, therefore, it can eases the cumbersome task of manually designing buck DC–DC converters.

As an additional result, we conclude that optimal design of the synchronous cascade buck converter performs more efficiently thanthe optimal design of the synchronous buck converter, given certain realistic set of specifications for wide-range voltage conversion.© 2012 IMACS. Published by Elsevier B.V. All rights reserved.

Keywords: Synchronous buck converter; Synchronous cascade buckconverter; Geometric programming; Optimization; Switchingconverter design

1. Introduction

Many designers have noted that properly designing DC–DC converters is a time-consuming and costly process.Consequently, there is considerable interest in applying optimization methods to ease the burden of such a task. Thispaper introduces a new method to determine the optimal parameter values in a DC–DC converter design. The method,which is based on geometric programming (GP), allows designers to deal with a wide range of specifications andconstraints, and is extremely fast. Moreover, the method either results in a globally optimal solution or conclusivelydetermines infeasibility.

In recent years, the performance of buck DC–DC converters has improved. Some of the advances are related to
energy-storing elements, which are now smaller and have fewer losses. Switches have also improved in that they arenow faster, and have a smaller on-state resistance and a better blocking voltage. However, converter design parametersstill have to be optimized to comply with dimension constraints and improve their efficiency.
∗ Corresponding author.E-mail address: [email protected] (R. Leyva).

0378-4754/$36.00 © 2012 IMACS. Published by Elsevier B.V. All rights reserved.http://dx.doi.org/10.1016/j.matcom.2012.03.004

http://www.sciencedirect.com/science/journal/03784754

dx.doi.org/10.1016/j.matcom.2012.03.004

mailto:[email protected]

dx.doi.org/10.1016/j.matcom.2012.03.004

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R. Leyva et al. / Mathematics and Computers in Simulation 82 (2012) 1516–1530 1517

Several authors have reported different methods to optimize the converter designing process. The process takes intoccount certain objective functions and constraints which are nonlinear, therefore linear programming methods are notuited for this task.

It is worth noting that the following papers report several of recently published approaches for optimizing DC–DCower conversion design.

Specifically, optimization of parameters such as current ripple, switching frequency and voltage swing in theOSFET gate driver is reported in [9] to obtain an optimal design for monolithic DC–DC buck converters. Also Refs.

20,13] present procedures to minimize magnitudes such as efficiency or the electromagnetic interference (EMI).Nevertheless, the methods in [9–13] optimize only one parameter or the optimization procedure is divided into

everal stages and then only one or two parameters are selected at each stage. Consequently, these procedures do notllow that a great number of constraints be imposed simultaneously.

In order to take into account simultaneously a great number of constraints, some authors have reported nonlinearrogramming methods for designing DC–DC converters. Important related studies are those of Seeman and Sanders16], who optimized a switched-capacitor converter design by means of Lagrangian functions, and those of Balachan-ran, Wu et al. [1,17] which describe the optimization of DC–DC converters by means of augmented Lagrangian.ther nonlinear programming methods such as the sequential quadratic programming method have also been used foresigning of DC–DC converters. For example, Busquets-Monge et al. [3] designed of a boost power-factor-correctoronverter using this method.

Nevertheless, the methods in [16,3] only ensure to achieve a local optimum, therefore the solution depend on thetarting point.

Unlike the previous references, this paper presents a new method for designing DC–DC converters which optimizes nonlinear objective function under nonlinear constraints and the solution does not depend on the starting point.oth the objective function and the constraints are expressed in a particular form which is known as the posynomial

orm and is explained in Section 2. An optimization problem expressed in posynomial form is called a geometricrogram. Geometric programs can be solved by means of efficient interior-point algorithms. The main advantage ofhis procedure is that, despite dealing with nonlinear objectives and constraints, it gives the global optimum or indicatesnfeasibility very quickly.

Researchers in optimization methods have been interesting in geometric programming (GP) since the 1960s [2,6].owever, the real advantages of this technique are only starting to be appreciated. The reason for this is the significantevelopment of interior point methods for solving convex optimization problems in the last fifteen years [12]. GPolution methods are now extremely efficient and reliable.

The method that this paper has adapted to buck DC–DC converter design, has been successfully applied in severalngineering fields such as transistor sizing [15], filter design [11], phase locked loop (PLL) circuit design [4], industrialanufacturing [10], among others.The present paper revisits the basics of geometric programming and then analyzes the converter efficiency and usual

esign constraints for two common buck converter topologies. Specifically, it applies the proposed procedure based oneometric programming to a synchronous buck converter and a synchronous cascade buck converter. The advantagesf the proposed method are particularly important in the design of synchronous cascade buck converter where we select

large number of components under a great variety of simultaneous constraints.A cascade topology is best suited when we need broad voltage conversion ratios, because the cascade topology is

ess demanding in terms of switch turn-on time. Despite this, it would seem that as far as the efficiency is concerned, aingle-stage converter is usually a better choice than a two-stage converter. Nonetheless, the present paper shows thathe cascade stage is slightly more efficient given the realistic specifications imposed. As an example, we impose lowipple constraints to prevent fast-scale nonlinear behaviors and EMI in such converters [21]. It is worth to note that theroposed design method is focused on steady-state performances and the buck and double buck converter still wouldequire of a suitable controller [19] to fulfill with certain dynamical performances.

Thus, the modeling of design expressions in such a manner that GP method can be applied to optimize bucknd cascade buck converters constitutes the main contribution of this paper. To our knowledge, no previous design
pproach in converters that need to determine a great number of parameters had taken into account the convexity ofhe optimization problem. The previous approaches only ensure to achieve a local optimum, whereas the proposedrocedure ensures the global optimum achievement. It is of maximal interest that the design procedure reaches theptimum, thus providing not only a good solution but the best solution.

1518 R. Leyva et al. / Mathematics and Computers in Simulation 82 (2012) 1516–1530

The paper is organized as follows: in Section 2, we revisit some of the geometric programming concepts thatwe apply in following sections. Losses and other design magnitudes expressions of DC–DC converters are stated inSection 3. Section 4 describes the objective and common design constraints of the optimization program. Section 5shows a graphical analysis that verifies the optimality of the design solution. Finally, Section 6 summarizes the mainconclusions.

2. Fundamentals of geometric programming

A convex function has a unique minimum. A convex optimization program consists of a convex optimization functionand certain convex constraints and has a unique, global minimum [2]. Modeling an engineering design problem as aconvex program allows the designer to find a unique, global optimum. A geometric program consists of an optimizationfunction and certain constraints that are expressed in a specific form named posynomial form. A geometric programcan be transformed into a convex program by means of an appropriate change of variables, thus the solution is a globaloptimum. In the following subsections, we revisit the basics of geometric programming method and describe how itcan be solved by means of standard interior-point algorithms.

2.1. Basics of geometric programming

GP uses the concepts of monomial and posynomial functions. Using these concepts allows the designer modelingan engineering problem as a geometric program. Next, we define the concepts of monomial and posynomial function.

Given the positive, real variables x1, . . ., xn that are to be determined in an optimization problem and a vector x = (x1,. . ., xn) which groups the variables xi, a function g is defined as a monomial when it has the form

g(x) = c xa11 xa2

2 · · ·xann (1)

where c is a positive real constant called the monomial coefficient, and a1, . . ., an are real constants that are referredto as the exponents of the monomial.

We should note that the monomial definition in the GP domain differs from the monomial definition in the algebradomain, because in algebra, the exponents are integers and the variables do not need to be positive as it is the case inthe GP domain.

We should also remark that the product of monomials is a monomial, and that the division or raising to a real powerof monomials are also monomials [2].

Any sum of monomial functions is referred to as a posynomial function and corresponds to

f (x) =K∑

k=1

ck xa1k1 xa2k

2 · · ·xankn (2)

where ck is a positive, real constant.Posynomial functions keep their form under addition, multiplication and positive scaling.Using the concepts of monomial and posynomial functions, we try to model our nonlinear optimizing problem in

the standard form of a geometric program that corresponds to

minimize f0(x)

subject to fi(x) ≤ 1 i = 1, . . . , m

gj(x) = 1 j = 1, . . . , p

(3)

where f0, . . ., fm are posynomial functions and g1, . . ., gp are monomial functions. Some extensions and some commonmanipulations to transform expressions to posynomial forms can be found in [2]. Also, this reference reports somemodeling examples for the design of electronics systems.

2.2. Solving a geometric program using interior point algorithms

Standard interior point algorithms have substantially evolved during the last decade, and are nowadays able toefficiently solve almost any convex optimization problem [12]. These algorithms are very robust and readily available

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oftware, such as Matlab among others, has implemented the code. An important feature of interior point algorithmss that when they are applied to a convex problem, the solution does not depend on the starting point or initial guess ofhe optimal solution, and that they find the correct solution very quickly if the problem is feasible. When the problems infeasible, these algorithms detect this infeasibility extremely quickly. This is not the case for general nonlinearrogramming algorithms.

It should be noted that the geometric program (3) is not convex, but that it can be readily converted to a convexroblem by means of a logarithmic change of variables.

Thus, in order to solve the problem, the optimization variables, the objective function and the constraints areransformed. We replace the original variables xi with their logarithm yi = log(xi) (or equivalently, xi = eyi ). The objectiveunction f0 is transformed into log(f0). We, also, replace inequality constraints fi ≤ 1 with log(fi) ≤ 0, and gj = 1 withog(gj) = 0. Hence, the program (3) is transformed into,

minimize log(f0(ey))

subject to log(fi(ey)) ≤ 0 i = 1, . . . , m

log(gj(ey)) = 0 j = 1, . . . , p

(4)

Since the functions log(ey), log(fi(ey)) and log(gj(ey)) are convex functions [2] this problem can be readily solvedy standard interior point algorithms.

Thus, modeling an engineering problem so that it can be solved by means of geometric programming consists ofxpressing the objective and the constraints in posynomial form according to (3). In the next section, we show howonverter expressions can be written in posynomial form.

. Review of the design magnitudes in DC–DC converters

In this section, we revisit losses, ripples and other magnitudes that appear in the converter design process. Specifi-ally, we analyze the synchronous buck converter and the synchronous cascade buck converter. On the basis of thesexpressions, the subsequent sections provide an optimal design and evaluate the influence of converter parameters.

.1. The design magnitudes in synchronous buck converters

Current ripple, voltage ripple, efficiency and losses are quantities that should be constrained or optimized in aonverter design procedure. Although the expressions are well known [7,18,8,5], we will review them for the sake ofompleteness.

Fig. 1 depicts the synchronous buck topology, whose dynamic behavior can be described using the state vector

x =[

i1

vo

](5)

here i1 is the inductor current and vo is the output voltage. Thus, the converter state equations correspond to expression6), where in mode ON (i.e. when Q1 is ON and Q2 is inactive) the value of the control signal is u = 1. Similarly, forode OFF (i.e. when Q1 is OFF and Q2 is active) the value of the control signal is u = 0.

di −V V
1
dt= o

L+ i

Lu

dvo

dt= i1

C− Vo

RC

(6)

Fig. 1. Synchronous buck converter.


Parameters L, C and R stand for the inductor value, the capacitor value and the load value, respectively and, Vi representsthe input voltage. The binary signal u turns the MOSFETs Q1 and Q2 on and off at constant switching frequency 1/Ts,with Ts being equal to the sum of intervals that it remains at ON TON and at OFF TOFF (the ratio d = TON/(TON + TOFF)corresponds to the duty-cycle d).

3.1.1. Current and voltage ripples and related design specificationGiven expression (6) and under the hypothesis of low voltage variation in the capacitor, the current ripple is a

triangular waveform whose amplitude depends on its slope during according to [7] and corresponds to

�i1 = Vo(1 − d)

Lfs

(7)

where Vo is the steady-state output voltage and fs = 1/Ts corresponds to the switching frequency.Since the current ripple flows through the capacitor increasing and decreasing its charge, then the voltage ripple

corresponds to

�vo = Vo(1 − d)

8Lf 2s C

(8)

A common specification is that the current ripple be smaller than the average current in the inductor, thus ensuringthat the converter operates in continuous conduction mode (CCM). This design specification can be stated as

Lfs >Vo

2Io

(1 − d) (9)

The converter designer tries to comply with the ripple constraints, but also tries to get a fast dynamic response.The converter will react fast when it has a good bandwidth. The expression of bandwidth in a buck converter isBW = 1/

√LC and should preferably be greater than a certain bound

BW > 2π(10% fs) (10)

Other magnitudes that should be taken into account in design of buck converters are related to the converter powerconsumption which is made up of conduction losses due to parasitic resistances, and switching losses due to parasiticcapacitances. In the next subsection, we consider the MOSFET losses, and ohmic losses in the filter inductor andcapacitor. It is worth noting that the expressions (7)–(10) are monomial terms when we take as optimizing variablesfs, C and L.

3.1.2. Dissipated power at MOSFETIn this subsection, we review the power losses in the high-side transistor Q1 and, afterwards, those induced by the

low-side transistor Q2 which substitutes the diode in a synchronous rectification.Total power consumption of high-side MOSFET PQ1 consist of conduction losses PONQ1 and switching losses

PSWQ1 . Quantities PQ1 , PONQ1 and PswQ1 can be approximated by the following expressions,

PQ1 = PONQ1 + PSWQ1

PONQ1 =(

I2o + �i1

12

2)dRDS

PSWQ1 = ViIo(TswON + TswOFF )fs

(11)

where Io stands for the average current, and TswON and TswOFF represent the transition time to ON and OFF, respectively.These times depend on the gate drive and features of the MOSFET. Parameter RDS stands for the on-resistance of theMOSFET.


b

wt

C

3

es

w

3

w

Fig. 2. Synchronous cascade buck converter.

The total power dissipated by the low-side MOSFET PQ2 is made up of conduction losses PONQ2 and losses in theody diode Pdb. The losses can be expressed as,

PQ2 = PONQ2 + Pdb

PONQ2 =(

I2o + �

12

2)(1 − d)RDS

Pdb = Vf Io(Tdead1 + Tdead2)fs + Qrr(Vi − Vo)fs

(12)

here Pbuck represents the forward voltage drop in the body diode, Tdead1 and Tdead2 are the dead times introduced byhe synchronous rectification, and Qrr corresponds to the body diode charge.

It is worth noting that the expressions (11) and (12) are posynomial terms when we take as optimizing variables fs, and L for buck converters; that is Vi − Vo > 0.

.1.3. Losses at passive elementsThe inductor is responsible for a substantial portion of the converter’s energy consumption. The losses in this passive

lement consist of winding losses and core losses but they can approximately be characterized by a constant equivalenteries resistance RL. Consequently, the power dissipated by the inductive element is expressed as,

Pind =(

I2o + �i1

12

2)RL (13)

Similarly, the capacitor losses can be approximated by,

Pcond =(

�i1

12

2)RC (14)

here RC is the equivalent series resistance in the capacitive element.

.1.4. Total power losses and efficiency in the synchronous buck converterGiven the expressions (11)–(14), the total power losses in the synchronous buck converter Pbuck are written as,

Pbuck = PONQ1 + PONQ2 + PSW + Pdb + Pind + Pcond (15)

The terms on the right contribute unevenly depending on the operating conditions of the converter.Efficiency is defined as,

η = 100Pload

Pload + Pbuck

(16)

here Pload = VoIo is the averaged power at the load.In the next subsection, the similar derivations are carried out for the synchronous cascade buck converter.


3.2. The design magnitudes in synchronous cascade buck converter

This four-order converter is depicted in Fig. 2. The following state vector is used in the analysis

x =

⎡⎢⎢⎢⎣

i1

v1

i2

vo

⎤⎥⎥⎥⎦ (17)

where i1 is the current of inductor L1, v1 is the voltage of capacitor C1, i2 is the current of inductor L2, and vo is theoutput voltage.

Hence, the converter state equations correspond to,

di1

dt=

(Vi − v1

L1

)u − v1

L1(1 − u)

dv1

dt= i1

C1− i2

RC1di2

dt= −vo

L2+ v1

L2u

dvo

dt= i1

C2− vo

RC2

(18)

3.2.1. Current and voltage ripples and related design specificationSimilarly, under the hypothesis of slow voltage variations in capacitors C1 and C2, the ripples of the inductor currents

are triangular and their amplitudes can be expressed as,

�i1 = V1(1 − d1)

L1fs

�i2 = Vo(1 − d2)

L2fs

(19)

where d1 and d2 represent the duty-cycle of first switch and second switch, respectively.Likewise, the voltage ripples are obtained from the aforementioned current ripple under a small variation assumption

and they can be expressed as follows,

�vo1 = V1(1 − d1)

8 C1 L1 f 2s

�vo2 = Vo(1 − d2)

8 C2 L2 f 2s

(20)

In order for the converter to operate in CCM, the following inequalities must be fulfilled,

L1 fs >V1

2Iod2(1 − d1)

L2 fs >Vo

2 Io

(1 − d2)

(21)

In addition, the bandwidth can be bounded by the following expressions,

BW = 1√ , BW = 1√
1L1C1
2L2C2

BW1 > 2π(5% fs)

BW2 > 2π(5% fs)

(22)

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octCo

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.2.2. Dissipated powerThe efficiency objective function takes into account losses in the four MOSFETs and in the two inductors and

apacitors, and they are similar to (11)–(14). Obviously, in the cascade converter case, the averaged currents areifferent. Given that, the averaged voltages corresponds to

V1 = Vid1

Vo = V1d2(23)

The averaged current expressions therefore corresponds to,

I1 = V 2o

R

1

V1= Iod1

I2 = Vo

R= Io

(24)

Thus, the total power losses in the synchronous cascade buck converter are written as,

Pdouble-buck = 2PONQ1 + 2PONQ2 + 2PSW + 2Pdb + 2Pind + 2Pcond (25)

here PONQ1 , PONQ2 , PSW, Pdb, Pind and Pcond are similar to that of the buck converter replacing the correspondingalues of the duty cycles and currents.

We should point out that the design magnitudes (7)–(15) for the buck converter are posynomial functions, theptimization variables being L, C and fs. Also, expressions (19)–(25) for the cascade buck converter are posynomial,he optimization variables being L1, L2, C1, C2, d1 and fs. It can be observed that to design a cascade converter in anppropriate manner requires 6 design variables, therefore finding the most efficient solution it is not an easy task. Inhe following section, we describe the geometric optimization program that solves the design problem.

. Optimal design: optimization objective and constraints

To set up a geometric optimization problem given certain optimization variables, we should choose a posynomialbjective function to be minimized and a group of posynomial constraints. For the synchronous buck converter, wehoose the power consumption Pbuck as the objective function, thus maximizing efficiency. The constraints refer tohe maximum and minimum size of design variables, the maximum admissible ripples, the bandwidth bound and theCM restriction. We express the ripple limits as a percentage of the averaged magnitudes. Therefore, the geometricptimization program to design a synchronous buck converter can be written as,

minimizeL,C,fs

Pbuck

subject to Lmin ≤ L ≤ Lmax

Cmin ≤ C ≤ Cmax

fsmin ≤ fs ≤ fsmax

�i1 ≤ a% of I0

�v0 ≤ b% of V0

CCM constraint (9)

(26)

BW constraint (10)

here a and b represent the percentages of the corresponding averaged magnitudes.


Similarly, the design of synchronous cascade buck converter can be designed using the following geometric program,

minimizeL1,L2,C1,C2,d1,fs

Pdouble-buck

subject to L1min ≤ L1 ≤ L1max

L2min ≤ L2 ≤ L2max

C1min ≤ C1 ≤ C1max

C2min ≤ C2 ≤ C2max

fsmin ≤ fs ≤ fsmax

�i1 ≤ a1% of I1

�i2 ≤ a2% of I0

�vo1 ≤ b1% of V1

�vo2 ≤ b2% of V0

CCM constraint (21)

BW constraint (22)

(27)

where a1, a2, b1 and b2 represent the percentages of the corresponding averaged magnitudes.The method could also be used to minimize the inductor size, thus facilitating the monolithic implementation of the

DC–DC converter [4], the only change being that the first constraints would be, in this case, the objective function,and that the power consumption would be a constraint that binds its value. It is also possible to choose the switchingfrequency fs as the objective function to be minimized.

The design optimization is performed under the hypothesis of low ripple in state variables, thus aspects as chaoticbehaviors in converters dynamics, such as those analyzed in [14] has not been considered in the paper. Nevertheless,it could be interesting to add more design constraints that take into account chaotic behaviors when the low rippleconstraint is not imposed.

In the next section, we instantiate the objective function and constraints for both converters in a real case. We alsoprovide and verify the solution.

5. Optimal design: verification

A design example is used, in this section, to illustrate the optimization procedure and the influence of small variationsaround the optimal point on performance.

The first step in the design procedure consists of choosing the average input and output voltage and the averagedoutput current. The MOSFET parameters used are shown in Table 1 and the design constraints and their bounds areprovided in Table 2.

The design input values, the solution and a graphical verification for the synchronous buck and synchronouscascade-buck converters are described in Sections 5.1 and 5.2, respectively.

Table 1Design example input values.

Vi 15 VVo 1.5 VIo 15 ARDS 5.2 m�

TswON 10−8 sTswOFF 10−8 sQrr 25 × 10−8 CVf 0.9 VTdead1 2 × 10−8 sTdead2 2 × 10−8 s


Table 2Variable bounds on the design example.

Lmin = 0.1 �H Lmax = 10 mHCmin = 0.1 �F Cmax = 100 �Ffsmin = 10 kHz fsmax = 5000 kHzi

5

M

m

s

5

sve

drtt

cnc

s

1 < 15 % Io vo < 15% Vo

.1. Procedure for the optimal design of synchronous buck converters

The input values for the optimization procedure are summarized in Table 1. In most cases the values relating to theOSFET involve a prescribed economic cost, which can be reevaluated in a post-optimization stage.Table 2 shows the bounds imposed over optimization variables. Some of these limits do not constrain the perfor-

ance, however, other do and it is particularly important to determine which values these areOnce the geometric program (26) for the values in Tables 1 and 2 has been coded in MATLAB, we obtain the

olution,

Optimal values of variables

L∗ = 11.9 �H

C∗ = 18.6 �F

f ∗s = 50.2 kHz

Optimal value of objective function

P∗buck = 1.71 W

Current and voltage ripples and BW

�i∗1 = 2.25 A

�v∗o = 0.3 V

BW∗ = 62.80 krad/s

Efficiency

η∗ = 92.93%

(28)

.1.1. Graphical verification of optimal design in the synchronous buck converterWe created some plots to verify that the optimization program result is correct. The plots indicate that any variation

atisfying the constraints around the optimal values (28) causes an efficiency decrease. The optimal values of someariables correspond to the limits of an active restriction; this implies that relaxing the bounds would increase thefficiency.

Fig. 3 depicts the efficiency with respect to inductance values. The red ×-marks correspond to inductance values thato not satisfy current ripple constraint, the blue square marks correspond to inductance values that do not satisfy voltageipple constraint; and the black circles correspond to admissible values. The optimal inductance value corresponds tohe highest black circle. Therefore, relaxing the current ripple constraint may increase the efficiency. It can be observedhat the best admissible values corresponds to (28), thus corroborating the procedure for finding the optimum.

We proceed similarly for the capacitor design variable C. Fig. 4 shows that a variation around the optimum of theapacitor value has very little influence on the efficiency. The blue squares correspond to capacitance values that doot satisfy the voltage ripple constraint and the black circles are admissible values. The optimal capacitance value
orresponds to the highest black circle.
Fig. 5 depicts the variation in the switching frequency value around the optimum. The red ×-marks representwitching frequency values that do not fulfill the current ripple constraint, the blue squares mark frequency values


6 8 10 12 14 16 1892.4

92.5

92.6

92.7

92.8

92.9

93

93.1

93.2

93.3

93.4

Inductance value ( µH)

Effi

cien

cy (

%)

Verification of the optimum value of inductance

Current ripple violationVoltage ripple Violatio nAdmissible value

Fig. 3. Efficiency versus inductance value. (For interpretation of the references to color in the text, the reader is referred to the web version of thearticle.)

0 5 10 15 20 25 30 3592.925

92.926

92.927

92.928

92.929

92.93

92.931

Capacitor value ( µF)

Effi

cien

cy (

%)

Verification of the optimum value of capacitor

Voltage ripple violationAdmissible value

Fig. 4. Efficiency versus capacitance value. (For interpretation of the references to color in the text, the reader is referred to the web version of thearticle.)

44 46 48 50 52 54 56

92.85

92.9

92.95

93

93.05

Switching frequency value (kHz)

Effi

cien

cy (

%)

Verification of the optimum value of capacitor

Current ripple violationVoltage ripple violationAdmissible value

Fig. 5. Efficiency versus switching frequency value. (For interpretation of the references to color in the text, the reader is referred to the web versionof the article.)


Table 3Design example input values for cascade buck converter.

L1min = 0.1 �H L1max = 10 mHL2min = 0.1 �H L2max = 10 mHC1min = 0.1 �F C1max = 100 �FC2min = 0.1 �F C2max = 100 �Ffsmin = 10 kHz fsmax = 5000 kHzi < 15 % I v < 30% V

i

tfs

t

wec

5

o

1 1 o1 1

2 < 15 % Io vo2 < 10% Vo

hat do not satisfy the voltage ripple constraint; and the black circles represent the admissible values. The minimumrequency value that satisfies the restrictions corresponds to the optimal value and to the highest black circle. It can beeen that the optimal efficiency values is 92.927%.

Therefore, relaxing the constraint allow us to decrease the optimal value of the switching frequency and thus increasehe efficiency.

This graphical process allows us to verify that, in effect, the result of (28) is the optimum and it allows us to determinehich variables are limited by design specifications constraints. Finally the slope of the lines gives an insight into the

fficiency increase when a given constraint is relaxed. In the next subsection, we apply this procedure to a synchronousascade buck converter.

.2. Procedure for the optimal design of a synchronous cascade buck converter

The input values for the synchronous cascade buck converter are shown in Table 3. The input values for theptimization procedure are the same as those shown in Table 1.

The optimum corresponds to

Optimal values of variables

L∗1 = 15.244 �H

L∗2 = 4.7922 �H

C∗1 = 127.6 �F

C∗2 = 236.52 �F

f ∗s = 50.226 kHz

d∗1 = 0.90

Optimal value of objective function

P∗double-buck = 1.5485 W

Current and voltage ripples and BW

�i∗1 = 27.5 mA

�i∗2 = 932.6 mA

�v∗o = 8.2 mV

�v∗o = 278 mV

BW∗1 = 3.6087 kHz

BW∗2 = 14.949 kHz

(29)

Efficiency

η∗ = 93.56%


146 148 150 152 154 156 15893.556

93.558

93.56

93.562

93.564

93.566

93.568

Inductance value L1(µH)

Effi

cien

cy (

%)

Verification of the optimum value of inductance L1

L1 current ripple violatio nAdmissible value

Fig. 6. Efficiency versus inductance L1. (For interpretation of the references to color in the text, the reader is referred to the web version of thearticle.)

It should be noted that, since the voltage transformation is from 15 V to 1.5 V, the duty cycle d1 of MOSFET Q1 isan optimization variable, whereas the duty cycle of the second stage is d2 = 10/d1, and is therefore not a free variable.

5.2.1. Graphical verification of optimal design in the cascade buck caseIn this subsection we analyze some plots to verify the optimality of the solution (29) and to evaluate which constraint

limits the efficiency. The plots show efficiency values when only one parameter is varied and the remaining optimalvariables are kept at their optimal values. It should be noted that the power losses function is convex, and that therefore,the efficiency (16) is a concave function (see Fig. 10).

In Fig. 6, the red ×-marks plot the inductance values that do not fulfill current the ripple restriction at L1 and theblack circles satisfy all the constraints. The optimal L1 value corresponds to the highest black square; therefore, thisripple constraint limits the efficiency.

We follow the same procedure for the L2 parameter (Fig. 7), where the blue squares stand for values that do not fulfillthe constraint on the output voltage ripple. The highest black square represents the optimal value of the L2 parameter.

A small change in the capacitor value C1 has no influence on the efficiency performance (Fig. 8). Therefore, wecan add a tighter bound on this parameter in a subsequent step.

In Fig. 9, the output voltage ripple constrains the value of C2.
Finally, in Fig. 10, the switching frequency is constrained by the output voltage restriction (indicated by the blue
square marks), and by the output current restriction (indicated by the red ×-marks). The optimal values correspond tothose of (24). Therefore, the optimum is verified.

4.2 4.4 4.6 4.8 5 5.2 5.493.548

93.55

93.552

93.554

93.556

93.558

93.56

93.562

93.564

93.566

Inductance value L2 ( µH)

Effi

cien

cy (

%)


Intermediate voltage ripple violationAdmissible value

Fig. 7. Efficiency versus inductance L2. (For interpretation of the references to color in the text, the reader is referred to the web version of thearticle.)


6 8 10 12 14 16 1893.5611

93.5611

93.5611

93.5611

93.5611

93.5611

Capacitor value C1 ( µF)

Effi

cien

cy (

%)

Verification of the optimum value of capacitor C 1

Admissible value

Fig. 8. Efficiency versus inductance C1.

18 19 20 21 22 23 24 25 26 27 2893.55

93.555

93.56

93.565

93.57

93.575

Capacitor value C2 (µF)

Effi

cien

cy (

%)


Output voltage ripple violationAdmissible value

Fig. 9. Efficiency versus inductance C2.

26 28 30 32 34 36 3893.5

93.51

93.52

93.53

93.54

93.55

93.56

93.57

93.58

93.59

93.6

Switching frequency falue (kHz)

Effi

cien

cy (

%)

Verification of the optimum value of switching frequency

Input current ripple violationOutput voltage ripple violationAdmissible value

Ft

6

pa

ig. 10. Efficiency versus switching frequency. (For interpretation of the references to color in the text, the reader is referred to the web version ofhe article.)

. Conclusions

We have shown that PG is a suitable approach for the design and optimization of buck DC–DC converters. Theroposed method minimizes power losses while constraining the current and voltage ripples, limiting the bandwidth,nd making the converter operate in continuous conduction mode. The method eases the burdensome task of evaluating

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a great number of alternatives. We have verified that the design objective function and the constraints can be expressedin a posynomial form and that therefore design can be optimized using this approach. Moreover, the feasibility of agiven set of design specifications can be readily verified using PG. The method has been applied to two buck topologies,namely the synchronous buck converter and the synchronous cascade buck converter. We have graphically verifiedthat the optimization result is correct. Furthermore, we show that, for the specification set analyzed, the cascade buckconverter has a slightly better efficiency than the single stage converter. This result contradicts the assumption that thecascade topologies are less efficient.

The method could also be used to minimize the size of inductors, thus facilitating the monolithic implementationof switching converters. Proposals to extend the method to interleaved or isolated topologies ones are being studied.The procedure assumes a constant load, proposals to extend the procedure to converters working in high frequencypulsating load are also been studied.

Acknowledgments

This work was partially supported by the Spanish Ministerio de Educación y Ciencia under Grants DPI2010-16481and DPI2009-14713-C03-02.

References

[1] S. Balachandran, F. Lee, Algorithms for power converter design optimization, IEEE Transactions on Aerospace and Electronic Systems AES-17(3) (1981) 422–432.

[2] S. Boyd, L. Vandenberghe, Convex Optimization, Cambridge University Press, 2004.[3] S. Busquets-Monge, J.-C. Crebier, S. Ragon, E. Hertz, D. Boroyevich, Z. Gurdal, M. Arpilliere, D. Lindner, Design of a boost power factor

correction converter using optimization techniques, IEEE Transactions on Power Electronics 19 (6) (2004) 1388–1396.[4] D. Colleran, C. Portmann, A. Hassibi, C. Crusius, S. Mohan, S. Boyd, T. Lee, M. del Mar Hershenson, Optimization of phase-locked loop

circuits via geometric programming, in: Custom Integrated Circuits Conference, Proceedings of the IEEE 2003, 2003.[5] S. Deuty, Optimizing transistor performance in synchronous rectifier buck converters, in: Applied Power Electronics Conference and Exposition,

2000. APEC 2000, Fifteenth Annual IEEE, vol. 2, 2000.[6] R. Duffin, E. Peterson, C. Zener, Geometric Programming: Theory and Application, Wiley, 1967.[7] R. Erickson, D. Maksimovic, Fundamentals of Power Electronics, Kluwer Academic, 2001.[8] D. Grant, J. Gowar, Power MOSFETS: Theory and Applications, A Wiley-Interscience Publication, 1989.[9] V. Kursun, S. Narendra, V. De, E. Friedman, Low-voltage-swing monolithic dc–dc conversion, IEEE Transactions on Circuits and Systems II:

Express Briefs 51 (5) (2004) 241–248.10] Leandro, dos Santos Coelho, Self-organizing migration algorithm applied to machining allocation of clutch assembly, Mathematics and

Computers in Simulation 80 (2) (2009) 427–435.11] H. Lebret, S. Boyd, Antenna array pattern synthesis via convex optimization, IEEE Transactions on Signal Processing 45 (3) (1997) 526–532.12] Y. Nesterov, N.A., Interior-point Polynomial Methods in Convex Programming, vol. 13 of Studies in Applied Mathematics, SIAM, Philadelphia,

PA, 1994.13] R. Ray, D. Chatterjee, S. Goswami, Reduction of voltage harmonics using optimisation-based combined approach, IEEE Transactions on Power

Electronics 3 (3) (2010) 334–344.14] B. Robert, A.E. Aroudi, Discrete time model of a multi-cell dc/dc converter: non linear approach, Mathematics and Computers in Simulation

71 (4–6) (2006) 310–319.15] S. Sapatnekar, V. Rao, P. Vaidya, S.-M. Kang, An exact solution to the transistor sizing problem for CMOS circuits using convex optimization,

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 12 (11) (1993) 1621–1634.16] M. Seeman, S. Sanders, Analysis and optimization of switched-capacitor dc–dc converters, IEEE Transactions on Power Electronics 23 (2)

(2008) 841–851.17] C. Wu, F. Lee, S. Balachandran, H. Goin, Design optimization for a half-bridge dc–dc converter, IEEE Transactions on Aerospace and Electronic

Systems AES-18 (4) (1982) 497–508.18] P. Xu, Multiphase voltage regulator modules with magnetic integration to power microprocessors, Ph.D. thesis, Virginia Polytechnic Inst.,

2002.19] X. Yang, H. Zhang, X. Ma, Modeling and stability analysis of cascade buck converters with n power stages, Mathematics and Computers in

Simulation 80 (3) (2009) 533–546.
20] X. Yuan, Y. Li, C. Wang, Objective optimisation for multilevel neutral-point-clamped converters with zero-sequence signal control, IEEE
Transactions on Power Electronics 3 (5) (2010) 755–763.21] H. Zhang, X.-P. Yang, X.-K. Ma, F. Zheng, Theoretical and experimental investigation of bidirectional Hopf bifurcations in cascade DC–DC

buck converters, Mathematics and Computers in Simulation 82 (4) (2011) 540–557.

design and optimization of buck and double buck converters by means of geometric programming

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