DESIGN AND IMPLEMENTATION OF LOW POWER REVERSIBLE ALU USING PARITY PRESERVING LOGIC

Under the Guidance of Dr. Y.SYAMALAAssociate Professor

Department of Electronics and Communication Engineering Gudlavalleru Engineering College

By

G.VENKATA LATHA

13481D5507

M.Tech - Embedded Systems

OUTLINE

Design of Arithmetic Logic Unit Based on Parity Preserving Reversible Logic Gates

Block Diagram:

Where

Ai, Bi are input operands,

S0-S3 are selection lines,

Ci-1 is input carry,

M is mode control bit and

Fi is output of ALU.

Xi= S3AiBi+S2AiBiഥതതതതതതതതതതതത

Yi = Ai+S0Bi+S1Biഥതതതതതതതതതതതതതതതതതത Ci =ቐ

Cinതതതത+M i=0Y0 + X0Cinതതതതതതതതതതതതതത+ M i = 1Yi + XiCi−1തതതതതതതതതതതതതത+ M i ≥ 2ቑand 𝐹𝑖 = 𝑋𝑖 ⊕ 𝑌𝑖 ⊕ 𝐶𝑖

Design Equations :

INTERNAL STRUCTURE OF FUNCTION GENERATOR

Gate Count=8

Garbage Output=16

Constant Inputs=14

SIMULATION RESULTS OF FUNCTION GENERATOR MODULE Xi

MODULE Yi

RTL SCHEMATIC OF FUNCTION GENERATOR MODULE Xi

MODULE Yi

INTERNAL STRUCTURE OF MODE CONTROL UNIT

MCU0

Generalized MCU

Gate Count=4

Garbage Output=8

Constant Inputs=8

SIMULATION RESULTS OF MODE CONTROL UNIT MODULE C0

MODULE Ci

RTL SCHEMATIC OF MODE CONTROL UNIT MODULE C0

MODULE Ci

FUNCTION CONTROLLER

Gate Count=1

Garbage Output=3

Constant Inputs=1

Simulation Results :

RTL Schematic:

Simulation Results of 1-bit Arithmetic Logic Unit ARITHMETIC UNIT (M=0 and Cin =1)

LOGIC UNIT (M=1)

RTL Schematic of 1-bit Arithmetic Logic Unit

NEW 4X4 PARITY PRESERVING GATE Internal Structure:

Simulation Results

¨ It is a 4X4 reversible gate.

¨It works as either reversible Full adder or a Full sub

tractor.

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Truth Table of New 4X4 Gate

INPUTS EX-ORof inputs

OUTPUTS EX-ORof outputs

A B C D P Q R S

0 0 0 0 0 0 0 0 0 00 0 0 1 1 0 1 0 0 10 0 1 0 1 0 0 0 1 10 0 1 1 0 0 0 1 1 00 1 0 0 1 0 0 0 1 10 1 0 1 0 0 0 1 1 00 1 1 0 0 0 1 1 0 00 1 1 1 1 0 0 1 0 11 0 0 0 1 1 1 0 1 11 0 0 1 0 1 0 0 1 01 0 1 0 0 1 0 1 0 01 0 1 1 1 1 0 0 0 11 1 0 0 0 1 0 1 0 01 1 0 1 1 1 0 0 0 11 1 1 0 1 1 0 1 1 11 1 1 1 0 1 1 1 1 0

NEW 4X4 PARITY PRESERVING GATE(Cond…)

RTL Schematic:

¨ EX-OR of inputs=Ex-OR of outputs.

¨So, it is a “Parity Preserving Gate”

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NEW 4X4 GATE IMPLEMENTED AS A FULLADDER

RTL Schematic: Internal Structure:

Simulation Results

NEW 4X4 GATE IMPLEMENTED AS A FULLSUBTRACTOR

Internal Structure: RTL Schematic:

Simulation Results

BASE PAPER

INTERNAL STRUCTURE OF FUNCTION GENERATOR

Gate Count=10

Garbage Output=19

Constant Inputs=17

SIMULATION RESULTS OF FUNCTION GENERATOR MODULE Xi

MODULE Yi

RTL SCHEMATIC OF FUNCTION GENERATOR MODULE Xi

MODULE Yi

INTERNAL STRUCTURE OF MODE CONTROL UNIT MCU0

Generalized MCU

Gate Count=6

Garbage Output=15

Constant Inputs=15

SIMULATION RESULTS OF MODE CONTROL UNIT MODULE C0

MODULE Ci

RTL SCHEMATIC OF MODE CONTROL UNIT MODULE C0

MODULE Ci

FUNCTION CONTROLLER

Simulation Results :

RTL Schematic:

Gate Count=1

Garbage Output=3

Constant Inputs=1

Simulation Results of 1-bit Arithmetic Logic Unit ARITHMETIC UNIT (M=0 and Cin =1)

LOGIC UNIT (M=1)

RTL Schematic of 1-bit Arithmetic Logic Unit

COMPARISON OF PERFORMANCE PARAMETERS

Authors Title of the paper/YearParity

preserving

Gate countper 1-bit

ALU)

Garbage Outputs

Constant Inputs

Observed Result

Proposed ALU

Design and Implementation of LowPower Reversible ALU Using Parity Preserving Logic

Yes 13 28 23

16logical and16arithmetic operations.

ShefaliMamataj

An Optimized realization of ALU for 12-Operations by using a Control Unit of reversible gates, 2014 (J).

No 8 10 33 logical and9arithmetic operations.

(Base Paper) Rakshith T.R

Parity Preserving Logic based Fault Tolerant Reversible ALU, 2013 (C).

Yes 17 37 33

16logical and16arithmetic operations.

Rozhin Bashiri

Designing a Novel Nanometric Parity Preserving Reversible ALU,2013(J). Yes 22 28 19

4 logical and4 arithmetic operations.

TOOLS REQUIRED

¨Tools Required: Front end Design Tools.(XILINX ISE)

¨Language Required: HDL programming language.

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PLAN OF ACTION

S.NO ACTIVITY Number of Weeks required (40)

1 Literature survey 4

2 Study and implementation of base paper 4

3 Implementation of Conventional ALU. 4

4 Implementation of proposed gate 5

5 Implementation of Reversible ALU 6

6 Power Analysis of Proposed ALU and Conventional ALU +Literature survey

7

7 Paper publication work +Literature survey

5

8 Project documentation work +Literature survey

5

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CONCLUSION

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¨The ALU is the most prominent component of any processor.

Thus designing of ALU using parity preserving reversible logic gates will make the ALU fault tolerant and

reduce the power dissipation.

¨ In this work along with the existing parity preserving gates, a new gate will be used in designing to reduce

gate count and garbage outputs.

REFERENCES

[1] T.R.Rakshith and R. Saligram, “Parity preserving logic based fault tolarent reversible ALU,” IEEE conference on Information and communication Technologies (ICT), pp.485-490, April 2013.

[2] Soghra shoaei and majid Haghparast, “Novel design of nanometric parity preserving reversible compressor,” Springer science,Business Media Newyark, pp.1701-1714, May 2014.

[3] Zhijin Guan,Wenjuan Li, Weiping and Yueqin hang, “An Arithmetic Logic Uniit design based on reversible logic gate,” IEEE conference on Communications,Computers and Signal processing, pp.925-931, August 2011.

[4] S.Anusha, M.Manoher Rao, and N.Swetha Reddy, “Design, Analysis, Implementation and Synthesis of 16 bit Reversible ALU by using Xilinx 12.2,” International Journal of Engineering Research and Applications, pp.86-91, April 2014.

[5] Rekha K.James,Shahana T.K and K.Poulose Jacob,“Fault Tolerant Error Coding and Detection using Reversible Gates,” IEEE Region 10 Conference TENCON, pp.1-4, October 2007.

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REFERENCES (contd….)

[6] Mahammand and Kamakoti Veezhinathan, “Constructing online Testing Circuits using Reversible Logic” IEEE Transactions on Instrumentation and Measurement, pp 101-109, January 2010.

[7] Xuemei Qi, Fulong Chen, Kaizhong Zuo, Liangmin Guo, Yonglong Luo and Min Hu, “Design of fast fault tolerant reversible signed multiplier,” International Journal of the Physical Sciences, pp. 2506 - 2514, 23 April 2012.

[8] Raghava Garipelly, P.Madhu Kiran and A.Santhosh Kumar “ A Review on Reversible Logic Gates and their Implementation,” International Journal of Emerging Technology and Advanced Engineering, vol 3, pp.417-423, March 2013.

[9] Himanshu Thapliyal, Apeksha Bhatt and Nagarajan Ranganathan,“A New CRL Gates as super class of Fredkin Gate to Design Reversible Quantum Circuits,” IEEE 56th Inrnational Midwest Symposium on Circuits and Systems (MWSCAS), pp.1067-1070, August 2013.

[10] B. Parhami, "Fault tolerant reversible circuits", Asimolar Conference on Signal, systems and computer, pp.1726-1729, October 2006.

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THANK YOU ALL

SUGGESTIONS PLEASE