Delays in Verilog

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Delays in Verilog. Introduction. Delays are crucial in REAL simulations Post-synthesis simulation Post-layout simulation FPGA counter-part: Post-P&R simulation Delay Models Represent different physical concepts Two most-famous models Inertial delay Transport delay. Delay Models. - PowerPoint PPT Presentation

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  • DELAYS IN VERILOG

  • IntroductionDelays are crucial in REAL simulationsPost-synthesis simulationPost-layout simulationFPGA counter-part: Post-P&R simulationDelay ModelsRepresent different physical conceptsTwo most-famous modelsInertial delayTransport delay

  • DELAY MODELSDelays in Verilog

  • Delay ModelsInertial DelayThe inertia of a circuit node to change valueAbstractly models the RC circuit seen at the nodeDifferent typesInput inertial delayOutput inertial delay

  • Delay ModelsTransport DelayRepresents the propagation time of signals from module inputs to its outputsModels the internal propagation delays of electrical elements

  • DELAY TYPESDelays in Verilog

  • Delay TypesRise DelayFall DelayTurn-Off DelayMin/Typ/Max Delay values

  • DELAYS INGATE-LEVEL MODELINGDelays in Verilog

  • Delays inGate-Level ModelingDelay are shown by # sign in all verilog modeling levelsInertial rise delayInertial fall delayInertial turn-off delayand #(rise_val, fall_val, turnoff_val) a(out,in1, in2)

  • Delays inGate-Level Modeling (contd)If no delay specifiedDefault value is zeroIf only one value specifiedIt is used for all three delaysIf two values specifiedThey refer respectively to rise and fall delaysTurn-off delay is the minimum of the two

  • Delays inGate-Level Modeling (contd)Min/Typ/Max ValuesAnother level of delay control in VerilogEach of rise/fall/turnoff delays can have min/typ/max valuesnot #(min:typ:max, min:typ:max, min:typ:max) n(out,in)Only one of Min/Typ/Max values can be used in the entire simulation runIt is specified at start of simulation, and depends to the simulator usedTyp delay is the default

  • DELAYS INDATAFLOW MODELINGDelays in Verilog

  • Delays inDataflow ModelingRegular Assignment Delaysassign #delay out = in1 & in2;As in Gate-Level Modeling the delay is output-inertial delay

  • Delays inDataflow Modeling (contd)Implicit Continuous Assignment Delaywire #delay out = in1 & in2;

  • DELAYS INBEHAVIORAL MODELINGDelays in Verilog

  • Delay in Behavioral Modeling

  • Today SummaryDelaysModelsInertial/TransportTypesRise/Fall/Turn-offMin/Typ/Max ValuesDelays in VerilogGate-Level ModelingDataflow ModelingBehavioral Modeling

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