delay-time suppression technique for dc/dc buck converter using voltage mode … · 2017. 11....
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Delay-time Suppression Technique
for DC/DC Buck Converter
Using Voltage Mode PWM Control
M. W. D. SAHAN *
N.Tsukiji, Y.Kobori, K. Asaishi, N.Takai, H. Kobayashi
Faculty of Science and Technology
Kobayashi laboratory
Gunma University
Paper 13ISPACS2017
XIAMEN CHINA(2017/11/09)
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Slide 2Outline
1. Purpose of This work
2. Research Background
3. Approach
4. Delay time suppression
5. Measurements results & Comparisons
6. Conclusion
ISPACS – XIAMEN 7-9 November 2017
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Slide 3Outline
1. Purpose of This work
2. Research Background
3. Approach
4. Delay time suppression
5. Measurements results & Comparisons
6. Conclusion
ISPACS – XIAMEN 7-9 November 2017
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Slide 4Purpose of This work
Lower output undershoot/overshoot
voltage of the DC/DC buck converter
ISPACS – XIAMEN 7-9 November 2017
Output voltage
undershoot
Load current
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Slide 5Outline
1. Purpose of This work
2. Research Background
3. Approach
4. Delay time suppression
5. Measurements results & Comparisons
6. Conclusion
ISPACS – XIAMEN 7-9 November 2017
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Slide 6
Proposed product
Research background
Research
「Fast Response」ISPACS – XIAMEN 7-9 November 2017
Miniaturization
NoiseReduction
Fast Response
High performance
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Slide 7Outline
1. Purpose of This work
2. Research Background
3. Approach
4. Delay time suppression
5. Measurements results & Comparisons
6. Conclusion
ISPACS – XIAMEN 7-9 November 2017
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Slide 8Approach
ISPACS – XIAMEN 7-9 November 2017
Micro chip
DC/DC
converter
Sudden
Load current
Conventional
method
proposed
methodundershoot
undershoot
Load current
Load current
iPod Charger
Ex :-
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Slide 9Delay time Suppression
ISPACS – XIAMEN 7-9 November 2017
Sudden load
current change
Transistor
power switch
ON
Delay time
Detect with
High-pass filter
Immediately
Undershoot
Undershoot
Load current
Load current
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Slide 10Outline
1. Purpose of This work
2. Research Background
3. Approach
4. Delay time suppression
5. Measurements results & Comparisons
6. Conclusion
ISPACS – XIAMEN 7-9 November 2017
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Slide 11
Delay time
Delay time Suppression
Conventional
circuit
Proposed
circuit
Delay time
Advantages
• Decrease output
voltage
• Fast response
sudden load
current
Disadvantages
• Large output
undershoot
voltage
• Worse load
current response
Inductor current
Output voltage
Load current
Inductor current
Output voltage
Load current
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Slide 12Proposed Converter Architecture
-
+
SR
Q
clkON
PowerStage
OFF
-
+ Vref
sawtooth
Vin
CS
EAcomp
VoVswSW
Cd
Rd
Detection circuit
Control
circuit
-
+-
+
clk
D Q
QN
CS
Vref1
Vref2
ON
OFF
Flip flop
latchOFF
CLK ON
Q
R
S
saw-tooth
Error amp1
OR2
OR1
Amplification
circuit
CS
CS
Error amp2
comparator2
Output
voltage
-
+
Comparator1
+
-
ISPACS – XIAMEN 7-9 November 2017
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Slide 13
Io
Output voltage
Detection circuit
High-pass filterload current has
differentiated by
high-pass filter
50%
Generated a smalldetection voltage (mV)
Load current
Detection signal
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Slide 14Amplification circuit & Control circuit
VA
VB
Amplification
circuit
Control
circuit
Output voltage
CS amplified
ON OFF signals
converted to
Control circuit
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Slide 15Outline
1. Purpose of This work
2. Research Background
3. Approach
4. Delay time suppression
5. Measurements results & Comparisons
6. Conclusion
ISPACS – XIAMEN 7-9 November 2017
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Slide 16Simulation setup
ISPACS – XIAMEN 7-9 November 2017
Parameter Value
Vin 12 V
Vo 5 VFrequency 350 kHz
L 10 μH
Co 20 μF
Rd 10 kΩ
Cd 100 pF
12 V
= 5 V
= 10 kΩ
= 100 pF
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Slide 17Simulation results
191mV
Conventional method
Proposed method Delay time
Delay time
Inductor current
Output voltage
Load current
Inductor current
Output voltage
Load current
Undershoot
191mV
Undershoot
38mV 38mV
Time [ms]
Time [ms]
Curr
ent
[A]
Curr
ent
[A]
Voltage [
V]
Voltage [
V]
Reduce 80%
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Slide 18Simulation Results
Detective
Amplification
Control
ISPACS – XIAMEN 7-9 November 2017
Sudden
load current
Detective circuit
output signal
Error amp 2
Output signal
Comparator 2
Output signal
Flip flop
output signal
Time [ms] Time [ms]
Vo
ltage [
V]
Voltage [
V]
Voltage [
V]
Voltage [
V]
Curr
ent
[A]
Curr
ent
[A]
Voltage [
V]
Voltage [
V]
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Slide 19Logical calculation(1)
Conventional method(include delay time)
𝑄 = 𝑖𝑡Total area= Capacity = 3.890 × 10−6C
𝑉0 =𝑄
𝐶𝑜
=3.890×10−6c20×10−6c
=194mV
𝑉0 : Voltage change𝑄 : Capacity𝑖 : Load current𝑡 ∶ Time𝐶𝑜 ∶ capacitor
Simulation result
191mV
Calculation result
194mV
area
ISPACS – XIAMEN 7-9 November 2017
Inductor current IL
Output voltage Vo
Load current Io
Curr
ent
[A]
Voltage [
V]
Time [ms]
194mV
Transistor power switch
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Slide 20Logical calculation (2)
Proposed circuit(without delay time)
𝑄 = 𝑖𝑡Total area = 8.84 × 10−7𝐶
𝑉0 =𝑄
𝐶
=0.884×10−6c20×10−6c
= 44.2mV
𝑉0 : Voltage change𝑄 : Capacity𝑖 : Load current𝑡 ∶ Time𝐶𝑜 ∶ 𝑐𝑎𝑝𝑎𝑠𝑖𝑡𝑜𝑟
Conventional : 194mV
Proposed : 44.2mV
Simulation result
38mVCalculation result
44.2mV
area
ISPACS – XIAMEN 7-9 November 2017
Inductor current IL
Output voltage Vo
Load current Io
Curr
ent
[A]
Voltage [
V]
Time [ms]
t
undershoot
44.2mV
Transistor power switch
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Slide 21Comparison with Undershoot
Phase[deg]
Und
ers
hoot vo
lta
ge
[mV
]
phase
phase
-180°
-180° 180°
180°0°
0°
proposed
conventional
Phase Between
-180° to 0°
Conventional method
Inductance current does not
change even if load current is
generated
proposed method
When load current occur,
Inductance current rises up at
moment
Undershoot
Clock
Io
IL
𝑇𝑂𝑁
𝑇× 360° = Phase
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Slide 22Comparison with Undershoot
Phase[deg]
Und
ers
hoot vo
lta
ge
[mV
]
phase-180° 180°0°
Phase Between
0° to 180°
NO effects in
Conventional method &
proposed method
Undershoot
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Slide 23Comparison with Overshoot
Phase[deg]
Ove
rsho
ot vo
lta
ge
[mV
]
phase
-180° 180°0°
Phase Between
-180° to 0°
NO effects in
Conventional method
and proposed method
Overshoot
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Slide 24Comparison with Overshoot
Phase[deg]
Ove
rsho
ot vo
lta
ge
[mV
]
phase
phase
-180°
-180° 180°
180°0°
0°
proposed
conventional
Phase Between
0° to 180°
Conventional method
Inductance current does not
change even if load current is
occurred
proposed method
When load current occur,
Inductance current rises down
at moment
Overshoot
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Slide 25
Comparison with Clock Frequency(1)
Phase[deg]
Un
de
rsh
oot vo
lta
ge
[mV
]
phase
phase
-180°
-180° 180°
180°0°
0°
Undershoot
proposed
proposed
Phase -100°
When the load current occur,
inductance current rises up at
moment
Phase 90°
Inductance current does not
change even if load current is
occurred
Phase Between 0° to 180°
No effect
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Slide 26
Comparison with Clock Frequency(2)
Phase[deg]
Ove
rsh
oo
t vo
lta
ge
[mV
]
phase
phase
-180°
-180° 180°
180°0°
0°
Overshoot
proposed
proposed
Phase Between -180° to 0°
No effect
Phase -90°
When the load current occur,
Inductance current rises up at
moment
Phase 90°
Inductance current does not
change even if load current is
occurred
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Slide 27
Comparison with Load current(1)
phase
phase
-180°
-180° 180°
180°0°
0°
Undershoot
proposed
proposed
Phase[deg]
Und
ers
hoot vo
lta
ge
[mV
]
Phase Between 0° to 180°
No effect
Phase -100°
When the load current occur,
Inductance current rises up at
moment
Phase 90°
Inductance current does not
change even if load current is
occurred
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Slide 28
Comparison with Load current(2)
phase
phase
-180°
-180° 180°
180°0°
0°
Overshoot
proposed
proposed
Phase[deg]
Ove
rsho
ot vo
lta
ge
[mV
]Phase Between -180° to 0°
No effect
Phase -90°
When load current occur,
Inductance current rises up at
moment
Phase 90°
Inductance current does not
change even if load current is
occurred
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Slide 29Result of conventional & proposed
89% 87%
■ Conventional ■ proposed
Voltage [
V]
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Slide 30Results with frequencies
88% 80% 73% 88% 82% 79%
■ Conventional ■ proposedUndershoot Overshoot
Voltage [
V]
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Slide 31Results with load currents
90% 71% 88% 79%
■ Conventional ■ proposed
Voltage [
V]
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Slide 32Outline
1. Purpose of This work
2. Research Background
3. Approach
4. Delay time suppression
5. Measurements results & Comparisons
6. Conclusion
ISPACS – XIAMEN 7-9 November 2017
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Slide 33Summary
• Delay time suppression
when load current occur, high-pass filter
differentiates signal, amplifies, turns on
transistor power switch immediately
• Proposed Buck DC/DC converter output voltage
- undershoot/overshoot decreases approximately 80%
- verification of calculations & simulations results
• Results Confirmed also in following
- regulate clock frequency
- undershoot/overshoot voltage with phase
- load current range
ISPACS – XIAMEN 7-9 November 2017
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Slide 34
Thanks for your attendance
of my speech
ISPACS – XIAMEN 7-9 November 2017
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