Post on 27-Jan-2017
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Developing Counter And Time delay routine
Microprocessor And Interface
CountersUsing counters programmer can specify that how many times an instruction (or set of instructions) is to be executed.
A loop counter is set up by loading a register with a certain value.
Counters (cont.)Then using the DCR (to decrement) and INR (to increment) the contents of the register are updated.
A loop is set up with a conditional jump instruction that loops back or not depending on whether the count has reached the termination count.
The operation of a loop counter can be described using the following flowchart.
IndexingIndexing means pointing or referencing objects with sequential numbers. In a library, books are arranged according to numbers, and they are referred or sorted by numbers. This is called indexing.
Similarly, data bytes are stored in memory locations and those data bytes are referred to by their memory locations.
Indexing (cont.)E.g., a list of numbers is stored in sequential memory locations. To access this list we need the address of first element and total number of elements in the list. We can use a register pair as an index by loading this address into the pair and then incrementing it to access elements of the list.
DelaysEach instruction passes through different combinations of Fetch, Memory Read, and Memory Write cycles.
Knowing the combinations of cycles, we can calculate how long such an instruction would require to complete.
Knowing how many T-States an instruction requires, and keeping in mind that a T-State is one clock cycle long, we can calculate the time using the following formula:
Delays=No. of T-States/Frequency.
For example MVI instruction uses 7 T-States and if the microprocessor is running at 2MHz ,the instruction would require 3.5 s to complete.
Time Delay Routine
How To Provide Time Delay ?In microprocessors we have studied different instructions like NOP,DCR,DCX. By using this one can use those instructions ,execute it number of times and get a delay.The delay we achieved is due to software instructions ,Therefore the same is referred as software Delay.
Timing delay using countersCounting can also create timing delays.The execution time of a program or the instruction are known to the user.By means of this data a user can determine the account of time delay.The time required for the execution of this program can be calculated with the T-statesTime delay using 8 BIT COUNTER IS AS FOLLOWS
Delay of Instructions Performance/delay of each instruction
MVI C, FFH 7 T-StateLOOP: DCR C 4 T-State JNZ LOOP 7/10 T-State Performance of other INS
ADD R 4 T-State ADD M 7 T-State CALL addr 18 T-State F=Fetch with 4 State, S=Fetch with 6 State, R=Memory Read, W=Memory Write
Calculation of 8 bit counter Total t-states required to execute a given program are =7+(count-1)*(10+4)+ (4+7)
MVI C Iterations/Loops last iterationFor count =2Number of T-states =7+(2-1)*(10+4)+ (4+7)=32Assuming operating frequency of 8085a is 5MHzTime required for 1 T-states=1/(5 MHz)=0.2microsecondsTime required for executing the program =
32* 0.2microseconds=6.4 microseconds
ContinueThe maximum count that can be loaded in 8 bit register is 255(FFH)Hence maximum delay delay possible with 8 bit counter is=
(7+(255-1)*(14)+11)* 0.2microseconds=714.8 microseconds
Time Delay using 16 bit counterLabel Instructions T-states
LXI D,COUNT 10TL1:DCX D 6T MOV A,D 4TORA E 4T JNZ LJ 10/7 TNo. of t-states requierd for an iteration
=T-states (DCX D)+T-states(MOV A,D)+T-states(ORA )+T-states (JNZ )=6+4+4+10=24 T-statesFor last iteration it requires
= T-states (DCX D)+T-states(MOV A,D)+T-states(ORA )+T-states (JNZ )=6+4+4+7=21T-states
Calculation of 16 bit counter Total t-states required to program are=
=10+(count-1)*24 +21LXI D Iterations Last iterationsFor count =0FFH(4095)Number of T-states =10+(4094)*24+21=98287Assuming operating Frequency=5MHZTime required for 1 T-state=1/(5MHZ)=0.2microsecondsTime required to execute the program
=98287*0.2microseconds=19.6574millisecondsMaximum delay can be achived using FFFFH (65535)
Time Delay: Nested LoopPerformance/delay of each instruction
MVI C, FFH 7 T-State MVI D, FFH 7 T-State LOOP1: DCR C 4 T-StateLOOP2: DCR D 4 T-State JNZ LOOP2 7/10 T-State JNZ LOOP1 7/10 T-State Time delay in Nested loop
TNL= N110 x T x ( L1_TStates+ L2_TStates x N210 )
Time delay using nested loopsIn this method there are more than one loops.The outer loop sets the multiplying count to the delays provided by the innermost loop,while the innermost loop is same as above.T-states required for innermost loop=7+(delay count-1)*14+11T-states required for execution of program=(multiplie count-1)*(T*14)+11
ContinueFor delay count =0AH(10) and multiplier count
=5 HT(inner)=7+(10-1)*14+11 =144Time required for executing the program assuming operating frequency 5 MHz=[(5-1)*(144+14)+11]*0.2microseconds=0.1286milliseconds.
Write a subroutine for 8085 to generate delay of 100(assume 320ns clock cycle)The time delay required is and clock cycle is of 320ns.So required T-states =100microseconds/320nanoseconds)As very Less T-states are require we can use delay using 8 bit counter.
MVI C,COUNT7TUP:DCR C 4TJNZ UP10/7TRET10TT(d)=7+(count*(4+10))+10-3=312.5
14 count =312.5-14=297.5Count =21.32=(15)octadecimal
So to get a delay of 100microseeconds use 15 as count value in program
Traffic Light Control: Counter & DelayLOOP: MVI A 01HOUT 01HLD B DELAY_REDCALL DELAYLoad DelayRedTime DelayTurn Signal to RedLoad DelayYellowTime DelayTurn Signal to YellowLoad DelayGreenTime DelayTurn Signal to Green MVI A 02HOUT 01HLD B DELAY_YELLOWCALL DELAY MVI A 03HOUT 01HLD B DELAY_GREENCALL DELAY JMP LOOP