dc graphical

Layer Optimization With Design Compiler Graphical

Version G-2012.06-SP3, December 2012

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Contents

Introduction ............................................................................................................ 4

What is Layer Optimization? .................................................................................. 4

When Is Layer Optimization Required? ................................................................. 5

Layer Optimization Based on Net Patterns ............................................................ 6

What Is a Net Pattern? ....................................................................................... 6

Net Pattern Based Commands ........................................................................... 6

create_net_search_pattern ............................................................................. 6

report_net_search_pattern .............................................................................. 8

remove_net_search_pattern ........................................................................... 9

set_net_search_pattern_delay_estimation_options ........................................ 9

report_net_search_pattern_delay_estimation_options ................................. 10

get_matching_nets_for_pattern .................................................................... 10

set_net_search_pattern_priority .................................................................... 10

Implementation With Design Compiler Graphical ............................................. 11

Binary and ASCII Netlist Handoff to IC Compiler ............................................. 11

Layer Optimization Based on User Constraints ................................................... 12

set_net_routing_layer_constraints Command .................................................. 13



Automatic Layer Optimization .............................................................................. 14



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Introduction

This application note describes the Design Compiler Graphical layer optimization features. The techniques described in this document should not be regarded as optimization technologies; rather, they are a set of commands designed to manipulate net layer assignments to better align them with back-end implementation. With this in mind, you should not always expect high-level metrics, such as worst negative slack (WNS) and total negative slack (TNS), to improve when enabling these layer optimization features. Perfect correlation is not synonymous with superior quality of results; indeed, in some cases, the most efficient way to improve one is at the expense of the other.

In this application note the term “layer assignment” is also used as an equivalent to “layer optimization.”

What is Layer Optimization?

When Design Compiler computes the resistance and capacitance of a net, it uses an average based on the resistance and capacitance of all available layers from the technology library. That average works well when all layers have the same or close enough unit resistance and capacitance value. However, with submicron technologies, the layers’ characteristics can vary greatly. Such variation can cause correlation or timing issues for nets that are known to be routed with only some specified layers. In this case, averaging is not an appropriate solution.

Layer optimization allows you to define specific layer assignment constraints and apply them to nets. This section provides an overview of the layer optimization commands. These commands are documented in more detail later in this application note, along with related layer optimization commands.

Design Compiler Graphical provides the following layer optimization methodologies:

Based on a net pattern (available beginning with version G-2012.06-SP1)

Based on user constraints (available beginning with version G-2012.06-SP2)

Based on automatic recognition (available beginning with version G-2012.06-SP3)

In the net pattern methodology, you use the create_net_search_pattern command

to define a pattern to identify nets, and the

set_net_search_pattern_delay_estimation_options command to define

which layers to use for a specific pattern.

In the user constraints methodology, you use the

set_net_routing_layer_constraints command to specify which nets will have

specific layer assignment constraints applied to them.

In the automatic recognition methodology, you allow Design Compiler Graphical to automatically identify nets and assign them to specific layers to reduce the resistance and capacitance on those nets, instead of using the averaging technique.

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Regardless of the methodology you use, layer optimization will have an impact on runtime. The more nets that are being assigned specifics layers, the longer the runtime.

When Is Layer Optimization Required?

If you are unfamiliar with the nuances of the technology, deriving a comprehensive net pattern-scaling methodology can be tedious. Before investing too much time in flow development, make sure that one or more of the following conditions exist:

The variation in unit resistance from the lowermost to uppermost routing layers is significant. The following example is an excerpt of a Design Compiler TLUPlus initialization message:

****************************************************************

Information: TLUPlus based RC computation is enabled. (RCEX-141)

****************************************************************

Information: The distance unit in Capacitance and Resistance is 1

micron. (RCEX-007)

Information: The RC model used is TLU+. (RCEX-015)

Information: Library Derived Res for layer M1 : 42 42 (RCEX-011)








Information: Library Derived Horizontal Res : 16.75 16.75 (RCEX-011)

Information: Library Derived Vertical Res : 24.5 24.5 (RCEX-011)

As the message shows, when values are normalized, the lowermost routing layer has a unit resistance that is 42 times higher than the uppermost layer. This TLUPlus data is from a sub-45 nm design, but other sub-45 nm designs have lowermost and uppermost unit resistance values that differ by more than 80x. This is problematic because before real routes are available, Design Compiler uses a weighted average resistance of all layers to compute estimated interconnect delays.

There are blatant routing topology differences between the virtual and real routing of a net. Although such nets can be difficult to detect, particularly when they have high fanouts or penetrate congested areas, nets with both of the following characteristics would qualify as strong pattern-based RC scaling candidates:

Timing critical

Higher than normal differences between virtual and real route lengths

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Layer Optimization Based on Net Patterns

Layer optimization based on net patterns is available in Design Compiler Graphical beginning with the G-2012.06-SP1 release.

Layer optimization based on net patterns is a three-step flow:

1. Create a net pattern.

2. Assign routing layers to that pattern.

3. Run optimization.

The following section defines a net pattern and describes the commands available to create a net pattern and the flow to implement layer optimization based on net patterns.

What Is a Net Pattern?

A net pattern consists of several physical attributes that help identify specific types of nets in a design. For example, a combination of attributes such as fanout, preroute length, and bounding box aspect ratios can be used to create collections of nets. Most pattern attributes are saved to the design database, but a few have to be derived dynamically, such as bounding box blocked area and aspect ratios.

Net Pattern Based Commands

The following sections describe all the commands related to pattern handling. For additional information about these commands, see the man pages.

create_net_search_pattern

You create net patterns by using the following command and options:

create_net_search_pattern

-connect_to_port

-connect_to_macro

-fanout_lower_limit integer

-fanout_upper_limit integer

-bbox_half_perimeter_lower_limit float

-bbox_half_perimeter_upper_limit float

-aspect_ratio_lower_limit float

-aspect_ratio_upper_limit float

-net_length_lower_limit float

-net_length_upper_limit float

-blocked_area_ratio_lower_limit float

-blocked_area_ratio_upper_limit float

-centered_within “float float float float”

The patterns created with the create_net_search_pattern command do not have

a name. They are assigned a number starting with 1 and are incremented by one. This number is used to refer to the patterns in any other related pattern command manipulation.

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The following is an overview of the create_net_search_pattern options:

A “lower limit” is the logical equivalent of “greater than or equal to.” To create a collection of nets with a virtual length greater than or equal to 1000 um, enter the following command:

create_net_search_pattern –net_length_lower_limit 1000

An “upper limit” is the logical equivalent of “less than.” To create a collection of nets with a fanout between 1 and 10, enter the following command:

create_net_search_pattern –fanout_upper_limit 11

The –connect_to_port and –connect_to_macro options apply only to nets

connected to top-level and macro cell I/O pins. If a pattern references one or both of these options, it always has a higher precedence than patterns created without them.

Note: If you specify both the –connect_to_port and

–connect_to_macro options, the tool creates a collection of nets

connected only to both I/O types.

Regarding precedence, suppose you create two patterns using the following commands:

create_net_search_pattern \

-fanout_upper_limit 2 \

-bbox_half_perimeter_upper_limit 100 \

-aspect_ratio_upper_limit 0.010




-aspect_ratio_lower_limit 0.008 \


A net with a fanout of 1, a bounding box half perimeter length of 75, and a bounding box aspect ratio of 0.009 matches both patterns; however, if these commands are entered in succession, the net is assigned to the first pattern because it was created first.

Assume that you want to assign the net to the second pattern and, for whatever reason, you do not want to change the order of the commands. (Imagine having

hundreds or thousands of create_net_search_pattern commands.) To

automatically simplify the prioritization of multiple

create_net_search_pattern collections, Design Compiler promotes primary

and macro cell I/O nets to have the highest precedence because they are almost always special cases. Therefore, if you execute the following two commands in order, and the net is connected to at least one macro cell I/O pin, it is automatically assigned to the second pattern:





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-connect_to_macro \



-aspect_ratio_lower_limit 0.008 \


The –centered_within option checks to see if the center coordinates of a net’s

bounding box fit inside the specified area. A bounding box is the smallest square or rectangle that encapsulates all of a net’s source and sink pins.

To check whether the entire net’s bounding box fits inside the specified area (if

you need to), use the pattern_center_in_region variable, as shown:

set pattern_center_in_region false

It is much more difficult to fit a series of random rectangles, such as net bounding boxes, into a targeted area than a series of random points, such as the centers of

net bounding boxes. For this reason, you should use the default setting of true

as often as possible; however, there might be unusual arrangements, such as nub

areas of rectilinear floorplans, that require you to set this variable to false.

The –bbox_half_perimeter_* options check a very explicit measurement: the

sum total of only the width and height of a net’s bounding box, in other words, half of its periphery. Many preroute optimization routines in Design Compiler are dependent upon that value.

The –aspect_ratio_* options specify the ratio of a net’s bounding box width

divided by its height. This value is computed for all nets, including nets that have irregular shapes resulting from rectilinear floorplans. If the width or height of a net’s bounding box is less than 0.05 um, a hard-coded value of 0.05 um replaces the original value. This is necessary to prevent integer overflow problems when computing very small ratios.

The –blocked_area_ratio_* options refer to the fraction of a net’s bounding

box that overlaps a macro cell or placement blockage. Geometry merging ensures that if, for example, a macro cell is covered by a hard blockage, only the larger of the two objects is considered. In addition, if a net contains pins that are outside the core area of a floorplan, only the portion of the net’s bounding box that is inside the core area is considered for the coverage ratio computation. This number, which must be between 0 and 1 (for example 0.50 represents an area that is 50 percent blocked), can be meaningful because layer assignments tend to be abnormal around blockages. Partial placement blockages are not considered for this calculation.

report_net_search_pattern

You can use the report_net_search_pattern command, as shown, to get

information about net patterns that are already created:

report_net_search_pattern -pattern 42

pattern id: 42

--------------------------------------------------

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fanout upper limit: 200

connect to IO ports: YES

You can use the –all option to report data for all net patterns.

remove_net_search_pattern

You can eliminate patterns with the remove_net_search_pattern command. For

example:

remove_net_search_pattern –pattern pattern_number

To remove all patterns at once, use the remove_net_search_pattern command

with the –all option.

set_net_search_pattern_delay_estimation_options

Once the net patterns are created, you can use the

set_net_search_pattern_delay_estimation_options command with the

following options to apply specific layer assignments to the net patterns:

set_net_search_pattern_delay_estimation_options

-min_layer_name string

-max_layer_name string

-pattern integer

When you use the set_net_search_pattern_delay_estimation_options

command, Design Compiler Graphical assigns specific minimum and maximum layers to the nets matching the specific pattern.

The set_net_search_pattern_delay_estimation_options command does not

work if you try to assign layers that are ignored with the set_ignored_layers

command:

dc_shell-topo> set_ignored_layers -min_routing_layer METAL \

-max_routing_layer METAL5

Information: setting METAL6 as ignored_layer due to min_max layer

setting. (PSYN-178)

Information: setting METAL as min routing layer. (PSYN-179)

Information: setting METAL5 as max routing layer. (PSYN-179)

dc_shell-topo> create_net_search_pattern -fanout_lower_limit 50

Information: Assigning pattern id to be 1. (PAT-003)

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dc_shell-topo> set_net_search_pattern_delay_estimation_options \

-min_layer_name METAL5 -max_layer_name METAL6 -pattern 1

Error: Layer METAL6 is ignored, please choose other layers. (FOPT-

026)

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report_net_search_pattern_delay_estimation_options

You can use the report_net_search_pattern_delay_estimation_options

command, as shown, to report the specific layer assignment defined for a specific net pattern:

report_net_search_pattern_delay_estimation_options -pattern 1138

Delay estimation options for pattern: 1138

--------------------------------------------------

minimum routing layer id: M7

maximum routing layer id: M8

--------------------------------------------------

You can use the –all option to report data for all net patterns.

Layer constraints appear in the report issued by the

report_net_search_pattern_delay_estimation_options command only

when non-default values have been assigned.

get_matching_nets_for_pattern

You can retrieve nets that are assigned to a specific pattern by using the following command with the following options:

get_matching_nets_for_pattern

-pattern integer

-optimizable

-setup_slack_lower_limit float

-setup_slack_upper_limit float

-hold_slack_lower_limit float

-hold_slack_upper_limit float

-transition_lower_limit float

-transition_upper_limit float

To learn how many nets are assigned to a pattern, run the following command:

set pattern_count [sizeof_collection \

[get_matching_nets_for_pattern –pattern 314]]

set_net_search_pattern_priority

Nets are assigned to patterns based on the order in which the patterns are created. For example, if 10 patterns are created and one net matches multiple pattern definitions, by default that net gets assigned to the first pattern it matches. If you need to change the match priority, use the following command:

set_net_search_pattern_priority “10 1 2 3 4 5 6 7 8 9”

Or, more simply, use the following command:

set_net_search_pattern_priority “10”

To report the current rank of pattern match priorities, use the following command:

report_net_search_pattern_priority

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To completely reset all pattern match priorities, use the following command:

set_net_search_pattern_priority –default

Implementation With Design Compiler Graphical

You must use the –layer_optimization option with the compile_ultra command

to enable layer optimization.

The –layer_optimization option only works when you use it with the

–spg option, but it cannot be used with the –incremental option. This means that all

pattern-based layer constraints must be defined before you run the compile_ultra

–spg –layer_optimization command for the first time.

Here is an example of layer assignment implementation with Design Compiler Graphical:

dc_shell-topo> set net_pattern_1 [create_net_search_pattern \

-fanout_lower_limit 100 -fanout_upper_limit 200]

dc_shell-topo> set_net_search_pattern_delay_estimation_options \

-min_layer METAL7 –max_layer METAL8 \

-pattern $net_pattern_1

dc_shell-topo> compile_ultra –spg –layer_optimization

The patterns are evaluated during optimization immediately after high fanout net synthesis is performed in Design Compiler. All nets that match the patterns will get the minimum and maximum layer assigned at that time in the flow.

You will see the following information message in the log file:

Information: Assigning minimum and maximum layer constraints based on

pattern. (DCT-212)

Design Compiler does not check to see if too many nets are assigned to the same layer, which can lead to layer overutilization. You must consider this when you create the patterns.

At the time patterns are evaluated, if none of the nets match a single pattern, Design Compiler switches to automatic layer assignment. See the “Automatic Layer Optimization” section in this document for more details about automatic layer assignment.

Binary and ASCII Netlist Handoff to IC Compiler

When saving the design in binary format (a .ddc file or Milkyway database) in Design Compiler, the net layer assignments are saved as part of the design so that IC Compiler

can reuse them when you use the place_opt –spg command.

Even though it isn’t mandatory, it is recommended that you apply the same set of pattern layer assignments in IC Compiler that were used in Design Compiler by using the

–layer_optimization option with the place_opt command.

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Here is an example of a complete flow:

In IC Compiler, the restore_spg_placement command restores the layer

assignments as part of the physical guidance flow.

If you are handing off the design from Design Compiler to IC Compiler in ASCII format, you need to write out the nets that have been assigned to specific layers. You can do

this in Design Compiler with the report_net_routing_layer_constraints

command, as shown:

dc_shell-topo> report_net_routing_layer_constraints \

[get_nets -hierarchical] –output nets.layer_assignment.rpt

You can then source that file in IC Compiler to restore the minimum and maximum layer assignments done by Design Compiler.

The generated file contains a set of set_net_routing_layer_constraints

command constraints. The set_net_routing_layer_constraints command is

described in the “Layer Optimization Based on User Constraints” section of this document.

Layer Optimization Based on User Constraints

Layer optimization based on user constraints is available in Design Compiler Graphical beginning with the G-2012.06-SP2 release.

The following sections describe how to define a minimum and maximum layer constraint on a net and the flow in Design Compiler Graphical.

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set_net_routing_layer_constraints Command

You can apply a minimum and maximum routing layer constraint on specific nets with

the set_net_routing_layer_constraints command using the following options:

set_net_routing_layer_constraints

-min_layer_name string

-max_layer_name string

list_of_nets

After the command is applied, the design can be timed accordingly, meaning that you

can run the extract_rc –estimate_rc command, and it will reflect the new layer

assignments on those nets.

The recommended usage for this command is to apply it after you initially run the

compile_ultra –spg command. Otherwise, there is no guarantee that the nets for

which the minimum and maximum layer constraint is defined won’t be optimized away.

For additional information about this command, see the man page.


Using the set_net_routing_layer_constraints command requires the physical

guidance flow.

The recommended flow is as follows:

dc_shell-topo> compile_ultra -spg

dc_shell-topo> set_net_routing_layer_constraints \

-min_layer METAL7 –max_layer METAL8 \

[get_nets ]

dc_shell-topo> compile_ultra –spg –incremental

dc_shell-topo> write –f ddc –hier –ouput design.ddc

The set_net_routing_layer_constraints command is always respected

regardless of the set_ignored_layers setup. Therefore, defining METAL8 as an

ignored layer does not prevent nets from being assigned to the METAL8 layer with the

set_net_routing_layer_constraints command.

Design Compiler does not check for overutilization of the layers. It is your responsibility to provide consistent layer assignments with the

set_net_routing_layer_constraints command.


When using a binary format handoff from Design Compiler to IC Compiler, either a .ddc

file or a Milkyway database, you need to use the –spg option with the place_opt

command to retrieve the net layer assignments done with Design Compiler.

If you are handing off the design from Design Compiler to IC Compiler in ASCII format, you need to generate the list of nets that have been assigned minimum and maximum

layers by using the report_net_routing_layer_constraints command in

Design Compiler. You can then source the ASCII file in IC Compiler.

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See the “Binary and ASCII Netlist Handoff to IC Compiler” section in the “Layer Optimization Based on Net Patterns” section for more information about the

report_net_routing_layer_constraints command.

Automatic Layer Optimization

Automatic layer optimization is available in Design Compiler Graphical beginning with the G-2012.06-SP3 release. It provides a simple way to implement layer optimization; it does not require any user specification.


Automatic layer optimization is controlled by the –layer_optimization option of the

compile_ultra command. As stated earlier, this option requires that you use the

–spg option, and it does not work with the –incremental option.

Automatic layer optimization does not require any net pattern to be defined. It is mutually exclusive with net pattern based layer optimization. However, if you create minimum and maximum layer constraints on net patterns, but those patterns return no nets at the time they are evaluated, Design Compiler Graphical performs automatic layer optimization instead.

The following information is displayed during automatic layer optimization:

Automatic minimum/maximum layer assignment

------------------------------------------

Derived Minimum Lower Layer : M7

Derived Maximum Upper Layer : M8

------------------------------------------

Total 241 nets to be assigned.

Total 166 nets assigned with min/max constraint.

Total 166 nets assigned with min/max constraint by tool.

The two upper layers that are available are considered for automatic layer optimization.

Design Compiler respects the ignored layers defined by the set_ignored_layers

command. If the two upper layers do not show signification resistance variation (smaller resistance than the lower layers), automatic layer optimization is not applied. In this case, the following message is issued:

Not appropriate to run layer optimization.

When performing automatic layer optimization, Design Compiler Graphical does not assign more nets than the layer availability to avoid overutilization.

Constant nets and tristate nets cannot be assigned a minimum or maximum layer in automatic layer optimization mode.


When using a binary format handoff from Design Compiler to IC Compiler, either a .ddc

file or a Milkyway database, you need to use the –spg option with the place_opt

command to retrieve the net layer assignments done with Design Compiler.

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If you are handing off an ASCII file to IC Compiler, you need to generate the list of nets that have been assigned minimum and maximum layers by using the

report_net_routing_layer_constraints command in Design Compiler. After

you do this, the ASCII file can be sourced in IC Compiler.

See the “Binary and ASCII Netlist Handoff to IC Compiler” section in the “Layer Optimization Based on Net Patterns” section for more information about the

report_net_routing_layer_constraints command.

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