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1 Confidential Document Version 1.0 IPSP2.0 IPSP2.0 Data Sheet Data Sheet Data Sheet 1.0 1.0 1.0 Security-on-Chip IPsec Processor Security Core and Packet Processor for AH/ESP by RFC 2401 – IP Security Architecture Authentication Algorithm: MD5, SHA1 with HMAC • IP Authentication Header by RFC 2402 • HMAC-MD5-96 by RFC 2403 • HMAC-SHA-1-96 by RFC 2404 Encryption Algorithm : DES, 3DES, SEED, AES • The ESP DES-CBC Transform by RFC 1829 • ESP DES-CBC with Explicit IV by RFC 2405 • IP Encapsulating Security Payload (ESP) by RFC 2406 • The NULL Encryption Algorithm by RFC 2410 • 3DES is used "outer" chaining technique by RFC 2451 Supported Encryption Mode : ECB, CBC Core operation frequency : 33Mhz Maximum Performance: 150Mbps for (3DES + SHA-1) at 33MHz Op clock, with new SA per packet Features Internal Block diagram Packet Processing capability using advanced DMA and Bus technology PCI 2.1 Interface, 32-bit, 33/66 MHz, Initiator/Target Low-Power 3.3V Package: • 100pin LQFP for ASIC S/W support: • Linux Device Driver • NKLIPS(nSYSTech’s Kernel Linux IPsec) AH Engine ESP Engine Packet Processor PCI/DMA Interface Internal Buffer (8KBytes) MEM Controller

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Page 1: Data SheetData Sheet - 엔시스텍 datasheet.pdf · Data SheetData SheetData Sheet 1.01.01.0 ... IP Hdr AH Hdr ESP Hdr Data ESP trlr Original Data (Transport, ... 28h Card Bus CIS

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IPSP2.0IPSP2.0

Data SheetData SheetData Sheet1.01.01.0

Security-on-ChipIPsec Processor

Security Core and Packet Processor for AH/ESP by RFC2401 – IP Security Architecture

Authentication Algorithm: MD5, SHA1 with HMAC• IP Authentication Header by RFC 2402• HMAC-MD5-96 by RFC 2403• HMAC-SHA-1-96 by RFC 2404

Encryption Algorithm : DES, 3DES, SEED, AES• The ESP DES-CBC Transform by RFC 1829• ESP DES-CBC with Explicit IV by RFC 2405• IP Encapsulating Security Payload (ESP) by

RFC 2406• The NULL Encryption Algorithm by RFC 2410• 3DES is used "outer" chaining technique by RFC

2451

Supported Encryption Mode : ECB, CBC

Core operation frequency : 33Mhz

Maximum Performance:150Mbps for (3DES + SHA-1) at 33MHz Op clock, with new SA per packet

Features

Internal Block diagram

Packet Processing capability using advanced DMA andBus technology

PCI 2.1 Interface, 32-bit, 33/66 MHz, Initiator/Target

Low-Power 3.3V

Package:• 100pin LQFP for ASIC

S/W support:• Linux Device Driver• NKLIPS(nSYSTech’s Kernel Linux IPsec)

AH EngineESP Engine

PacketProcessor

PCI/DMAInterface

PCI/DMAInterface

Internal Buffer

(8KBytes)

Internal Buffer

(8KBytes)

MEMController

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Applications

IPSP2.0, nSYSTech’s High performance IPSec-compliant ASIC supports the following applications;• Standalone VPN Hardware, • Firewall integrating VPN,• Router integrating VPN• Broadband access devices such like, xDSL/Cable Modem

Internet

Remote

UserPOP

Branch Office

T1 to OC-3 56KbpsxDSL/Cable

T1 to T3 Firewall

POP

POP

Server Farm

Clients

RemoteRemoteUserUser

Branch OfficeBranch Office

Central SiteCentral Site

POP

Dedicated VPN

Firewall Based

T1 to T3

Router Based CPE Based

Branch OfficeBranch OfficeClientsClients

CPUCPU

FlashFlash

DRAMDRAM

IPSP2.0IPsec Processor

IPSP2.0IPsec Processor

LAN/WANInterface

LAN/WANInterface

LANInterface

LANInterface

DRAM

PCI Bridge &DRAM Controller

PCI Bridge &DRAM Controller

Typical Block Diagram of the VPN System incorporating IPSP2.0

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1. Overview

1.1 Data Operation Mode

1.1.1 Operation Restriction

Authentication, Encryption(decryption) core supports only one parameter bundle

1.1.2 Supported Modes and Data Structures

Original Data (Transport mode or Tunnel mode only)

IP Hdr Data

⇒ ESP only

AuthIP Hdr DataESP Hdr ESP trlr

⇒ AH only

IP Hdr DataAH Hdr

⇒ ESP(No authentication) + AH

IP Hdr DataAH Hdr ESP Hdr ESP trlr

Original Data (Transport, Tunnel Mixed Mode)

DataOuter IP Hdr Inner IP Hdr

⇒ AH(outer) + ESP(inner, No authentication)

Inner ESP Hdr

Inner ESP trlr

Outer AH Hdr DataOuter IP

HdrInner IP

Hdr

⇒ ESP(outer) + AH(inner) : Not Support Concurrent Operation because of AH Hdr.

DataOuter IP Hdr

Inner IP Hdr

Outer ESP Hdr

Inner AH Hdr Outer ESP trlr

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2. Pin Description

nSYS TechIPSP2.0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

81828384858687888990919293949596979899100

VDDMON14MON15INTA#

RST#CLK

GNT#REQ#AD31

VSSVDD

AD30AD29AD28AD27AD26AD25

CBE3#IDSEL

VSS

5049484746454443424140393837363534333231

VSSEECKEECSEEDIEEDOAD0AD1AD2AD3VDDVSSAD4AD5AD6AD7CBE0#AD8AD9AD10VDD

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

VSS

MO

N13

MO

N12

MO

N11

MO

N10

MO

N9

MO

N8

MO

N7

MO

N6

VD

DV

SSM

ON

5M

ON

4M

ON

3M

ON

2M

ON

1M

ON

0B

RST

#C

LK_M

DSC

AN

_CLK

VSS

MO

NSE

L2M

ON

SEL1

MO

NSE

L0TS

TMD

1TS

TMD

0SC

AN

ENEE

AN

1EE

AN

0V

DD

VD

DA

D24

AD

23

AD

22A

D21

AD

20A

D19

AD

18A

D17

VSS

VD

DC

BE2

#FR

AM

E#IR

DY

#TR

DY

#D

EVSE

L#ST

OP#

PER

R#

SER

R#

VSS

VD

DPA

RC

BE1

#A

D16

AD

15A

D14

AD

13A

D12

AD

11V

SS

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Name Type Pin Number Description

CLK I 86 PCI Clock: Provides timing for all transactions on PCI and is an input to every PCI device. The IPSP2.0 operates up to 66MHz

RST# I 85 PCI Reset: Used to bring PCI-specific registers, sequencers, and signals to a consistent state.Local Logic Reset.

REQ# O 88 Bus Request: Indicates to arbiter that this agent must use the bus. Every Master has its own GNT# and REQ#.

GNT# I 87 Bus Grant: Indicates to the agent that access to the bus is granted. Every master has its own REQ# and GNT#.

AD[31:0] I/O 89, 92~97,2~9, 24~29,32~34, 36~39,42~55(MSB first)

PCI Address/Data Bus: All multiplexed on the same PCI pins. The bus transaction consists of an Address phase, followed by one or more Data phases. The IPSP-1 supports Read and Write bursts in Master mode.

CBE#[3:0] I 98, 12, 23, 35(MSB first)

PCI Bus Command/Byte Enable: All multiplexed on the same PCI pins. During the Address phase of a transaction, defines thebus command. During the Data phase, used as byte enables. Refer to the PCI spec for further details.

FRAME# I/O 13 Cycle Frame: Driven by the current Master to indicate the beginning and duration of an access. FRAME# is asserted to indicate the bus transaction is beginning. While FRAME# is asserted, Data transfers continue. When FRAME# is de-asserted, the transaction is in the final Data phase.

IRDY# I/O 14 Initiator Ready: Indicates ability of the initiating agent (Bus Master) to complete the current Data phase of the transaction.

TRDY# I/O 15 Target Ready: Indicates ability of the Target agent (selected device) to complete the current Data phase of the transaction.

DEVSEL# I/O 16 Device Select: When actively driven, indicates the driving device has decoded its address as Target of current access. As an input, indicates whether any device on the bus is selected.

STOP# I/O 17 Stop: Indicates the current Target is requesting that the Master stop the current transaction

PERR# I/O 18 Parity Error: Reports data parity errors during all PCI transactions, except during a special cycle.

SERR# O 19 Systems Error: Reports address parity errors, data parity errors on the Special Cycle command, or any other system error where the result is catastrophic.

PAR I/O 22 Parity: Even parity across AD[31:0] and CBE#[3:0]. All PCI agents require parity generation. PAR is stable and valid one clock after the Address phase. For Data phases, PAR is stable and valid one clock after either IRDY# is asserted on a Write transaction or TRDY# is asserted on a Read transaction. Once PAR is valid, it remains valid until one clock after current Data phase completes.

IDSEL I 99 Initialization Device Select: Used as a chip select during Configuration Read and Write transactions

INTA# O 84 Interrupt: PCI Interrupt

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VCCO I 1,11,21,31,41,51, 71, 81, 91

Power Supply – Outer: 3.3V

GND I 10,20,30,40,50,60,70,80,90,100

Ground

EECS O 48 Serial EEPROM Chip Select

EEDO I 46 Serial EEPROM Data OUT

EEDI O 47 Serial EEPROM Data IN (TriState output)

EEAN I 53, 52(MSB first)

Serial EEPROM Mode Select : EEPROM access is composed of command, address, and data phase. To read correctly the parameter stored in EEPROM, the number of address of EEPROM device should be known to IPSP.Refer to the EEAN value in varying with EEPROM address number as follows.

EEAN[1:0] = 2’b00, when EEPROM A<n> = 5EEAN[1:0] = 2’b01, when EEPROM A<n> = 6EEAN[1:0] = 2’b10, when EEPROM A<n> = 7EEAN[1:0] = 2’b11, when EEPROM A<n> = 8.

Name Type Pin Number Description

EECK O 49 Serial EEPROM Data CLK

CLK_MD I 62 Core Clock Mode0 : Direct PCI Clock, 1 : PCI Clock / 2When PCI Clock is 66Mhz, CLK_MD should be set to 1For Core clock is 33MhzWhen PCI Clock is 33Mhz, CLK_MD should be set to 0For Core clock is 33Mhz

TSTMD I 56, 55 Test Mode Select (tied to GND)

MONSEL I 59, 58, 57 Test Monitoring Select (tied to GND)

MON O 83, 82, 79, 78,77, 76, 75, 74,73, 72, 69, 68,67, 66, 65, 64

Test Monitoring (NC)

BRST# I 63 Button Reset (tied to VCC)

SCAN_CLK I 61 Scan Test Clock (tied to GND)

SCANEN I 54 Scan Test Enable (tied to GND)

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3. Register Description

3.1 PCI Configuration Registers

Address

00h

31:24 23:16 15:8 7:0

Device ID Vendor ID

04h STATUS Register COMMAND Register

08h Class Code Revision ID

0Ch BIST Latency TimerHeader Type Cache Line Size

10h Base Address Register 0

14h Base Address Register 1

18h Base Address Register 2

1Ch Base Address Register 3

20h Base Address Register 4

24h Base Address Register 5

28h Card Bus CIS Pointer

2Ch Subsystem ID Subsystem Vendor ID

30h Expansion ROM Base Address

34h Capability Pointer

38h

3Ch Max Latency Interrupt PinMin Grant Interrupt Line

3.1.1 Vendor ID (00h)

Valid Vendor ID is allocated by PCI SIG.

Default: 1794h

3.1.2 Device ID (02h)

Allocated by the vendor.

Default: 1000h

3.1.3 COMMAND Register (04h)

Provides coarse control over the device’s ability

Bit 0: I/O spaceDefault 0; R/WWhen S/W is set to 1, the device IO address decoder responds to PCI IO accesses.

Bit 1: Memory spaceDefault 0; R/WWhen this bit is set to 1, the device responds to PCI memory accesses.

Bit 2: Master enableDefault 0; R/WWriting a 1 allows device to behave as a Bus Master.

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Bit 3: Monitor Special CycleDefault 0; Ronly; Not supportedWriting a 1 allows the device is enable to monitor for PCI special cycles.

Bit 4: MWI enableDefault 0; Ronly; Not SupportedWriting a 1, enables the memory write and invalidate mode for PCI Initiator

Bit 5: VGA palette snoop enableDefault 0; Ronly; Not Supported

Bit 6: Report parity ErrorDefault 0; R/WIf it is 1, the device can report parity errors by asserting PERR#. Otherwise, the device doesn’t assert PERR#. However, it still must set the Detected Parity Error Status bit in its Status Register

Bit 7: Address Stepping supportedDefault 0; Ronly

Bit 8: SERR enableDefault 0; R/WWhen it is 1, the device can drive the SERR# line. The bit 6 & this bit must be set to report address phase parity errors.

Bit9: Fast back-to-back enableDefault 0; Ronly

3.1.4 STATUS Register (06h)Records status information for PCI bus related eventsBit [3:0]: ReservedBit 4: Capabilities List

Default 0; RonlyIf enabled, the 1st new capability function ID is located at PCI configuration offset [40h].Can be written only from the Local bus.

Bit 5: 66MHz capableDefault 1; RonlyWhen it is 1, device is capable of running at 66MHz.

Bit 6: UDF supportedDefault 0; RonlyIf set to 1, this device supports user definable functions.

Bit 7: Fast back-to-backDefault 0; RonlyWriting a 1 indicates an adapter can accept fast back-to-back transmission.Check it later

Bit 8: Master Data Parity Error DetectedDefault 0; R/WcSet to 1 when three conditions are met

Core asserted PERR# and acknowledged PERR# assertedCore was Master for operation in which error occurredParity Error Response Bit in Command Register is set

Writing a 1 clears this bit to 0.Bit [10:9]: Device Select (DEVSEL#)

Default 01; RonlyMedium Speed Decoder

Bit 11: Signaled Target AbortDefault 0; R/WcSet to 1 when Core has signaled a Target Abort signal

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Bit 12: Received Target AbortDefault 0; R/WcSet to 1 when Core has received a Target Abort signal

Bit 13: Received Master AbortDefault 0; R/WcSet to 1 when Core has received a Master Abort signal

Bit 14: Signaled System ErrorDefault 0; R/WcSet to 1, Core has reported a system error on SERR#

Bit 15: Detected Parity ErrorDefault 0; R/WcSet to 1, Core has detected a PCI bus parity error, even if Parity Error Response bit in the command register is disabled.One of three conditions can cause this bit to be set.

• Core detected parity error during PCI address phase• Core detected data parity error when it was the Target of a write• Core detected data parity error when performing Master Read operation

3.1.5 Revision ID (08h)Default: 00h

3.1.6 Class Code (09h)Base Class Code: 10h, Subclass Code: 00h, Register Level: 00h

3.1.7 PCI Cache Line Size (0Ch)Bit [7:0] System Cache Line Size

Default 0; RonlySpecify the system cache line size in double word incrementsIf it is 0, the System use Memory_Write transaction instead of Memory_Write_Invalidate transfer.

3.1.8 PCI Bus Latency Timer (0Dh)[7:0] Latency Timer

Default 10h; R/WSpecify the number of CLKs (time) in Core, as a Bus master, can burst data on the PCI bus

3.1.9 PCI Bus Header Type (0Eh)Bit [6:0]: Configuration Layout Type

Default 0; RonlyHeader Type 0

Bit 7: Number of functionsDefault 0; RonlySingle function

3.1.10 PCI BIST(0Fh)Default all 0; RonlyNot supported

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3.1.11 Base Address Register 0~5 (10~24h)Specify the size of memory space required for PCI Device.Specify the base address of PCI device.Base Address Setup Mechanism

• Write all 1s bit into BAR of PCI device• Read BAR & calculate the weight value of 1st occurrence of 1 in BAR.• It is the required memory space for PCI device• And then Set the base address of PCI device.

PCI BAR0For memory space configuration of Local SideBit 0: Memory Space Indicator

Default 0; RonlyBit [2:1]: Register Location

Default 00; RonlyBit 3: Prefetchable

Default 0; RonlyBit [31:4]: Memory Base Address

Default at Local Init Value; R/WMemory base address for access to Local Memory Bank (16KBytes)

This BAR0 is initialized at reset time as Local Init Value = FFFC_E000h at Local Memory Space 16KBytes

PCI BAR1For IO space configuration for Local RegisterBit 0: Memory Space Indicator

Default 1; RonlyBit 1: ReservedBit [31:2]: I/O Base Address

Default at Local Init Value R/WI/O base address for access to Local Register

This BAR1 is initialized at reset time as Local Init Value = FFFF_FF01h at Local Register (256Bytes)

PCI BAR2, PCI BAR3, PCI BAR4, PCI BAR5Reserved

3.1.12 Cardbus CIS Pointer (28h)Default: 0h

3.1.13 Subsystem Vendor ID (2Ch)Unique Add-in board vendor IDDefault: 0000h

3.1.14 Subsystem ID (2Eh)Unique Add-in board device IDDefault: 0000h

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3.1.15 PCI Expansion ROM Base Register (30h)For access of expansion ROM for Local ROM.Bit 0: Address Decode Enable

Default 0; R/WWriting a 1 indicates a device accepts accesses to the Expansion ROM address.Writing a 0 indicates a device does not accepts accesses to Expansion ROM space

Bit [10:1]: ReservedBit [31:11]: Expansion ROM Base Address

Default 0; R/WUpper 21 bits

3.1.16 PCI Next_Cap Pointer (34h)[7:0] New Cap. Pointer

Default 00h; RonlyOffset into PCI Configuration Space

[31:8] Reserved

3.1.17 PCI Interrupt Line (3Ch)[7:0] Interrupt Line Routing Value

Default 0; R/WIndicate which input of system interrupt controller is connected to each interrupt line of the device.

3.1.18 PCI Interrupt Pin (3Dh)[7:0] Interrupt Pin Register

Default 1h; Ronly1 indicates INTA# is used.

3.1.19 PCI Min_Gnt (3Eh)[7:0] Min_Gnt

Default 0h; R/WLSSpecify how long a burst period device needs, assuming a clock rate of 33MHz, Value is a multiple of 1/4us increments.

3.1.20 PCI Max_Lat (3Fh)[7:0] Max_Lat

Default 0h; R/WLSSpecify how often the device must gain access to the PCI bus. Value is a multiple of 1/4us increments.

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3.2 Device Specific Registers

Address

40h

31:24 23:16 15:8 7:0

DMA_SADDR

44h DMA Control DMA DWORD

48h

4Ch

50h PCI Core Control

INT Enable INT StatusINT Control INT Status

PCI Core Status

54h Local I/F Status

DMA_* registers control and monitor the behavior of PCI Master at Local Side.INT_* register control the INTA# by which the local side indicates the critical status to the host.PCI_* register is confidential register set for controlling the action of PCI core.

3.2.1 DMA SADDR (40h)[31:0] DMA System Address

Default 0; R/WSpecify the DMA start address to the PCI Target.

3.2.2 DMA Control (44h)[8:0] DMA DWORD

Default 0; RonlySpecify the double word of transfer

[12:9] ReservedDefault 0; Ronly

[15:13] DMA_STATEDefault 0; RonlyRepresents the state of DMA block

[20:16] ReservedDefault 0; Ronly

[21] DMA EndDefault 0; RonlyRepresents that DMA transfer is finished.

[22] DMA WriteDefault 0; RonlySpecify the DMA Tx/Rx. DMA Tx is set when it is 1.

[23] DMA ReadyDefault 0; RonlyThe Local writes this bit to start DMA transfer after writing the DMA_SADDR, DMA_DWORD, DMA_Write.This bit is cleared after DMA transfer completion by the DMA controller.Indicates that DMA operation should start by using the DMA parameter given by the Local.This bit is valid when S/W CTRL is 0.

[26:24] ReservedDefault 0; Ronly

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[27] I/O CycleDefault 0; R/WIf it is 1, then DMA writes the I/O access Command. Otherwise, writes the Memory Access Command.

[28] SADDR IncrementDefault 1; R/WIf it is 1, then DMA increments the SADDR in each writing/reading data. Otherwise, DMA operates in the SADDR.

[29] S/W CTRLDefault 0; R/WIf it is 1, then DMA is controlled by the S/W Command such as SW_RDY, SW_STOP. Otherwise, Local controls the operation of DMA by the parameter given by the Local Side.

[30] S/W STOPDefault 0; R/WIf it is 1, then DMA aborts the transfer. DMA controller clears the internal FIFO data. This bit is valid only if the S/W CTRL bit is 1.

[31] S/W RDYDefault 0; R/WIf is 1, then DMA starts the operation after that the local side writes the DMA parameter. DMA controller clears the S/W RDY after completion of transfer. Note that the Local writes the parameter for DMA operation.This bit is valid only if the S/W CTRL bit is 1.

3.2.3 Interrupt Enable (4Bh) [refer to Interrupt Status][0] IEN_TABORT_RCV

Default 0; R/W If it is 0, then disable the TABORT_RCV Interrupt Status Register (ISR) & its Interrupt.

[1] IEN_DMA_ABORTDefault 0; R/W

[2] IEN_DMA_ENDDefault 0; R/W

[3] IEN_TABORTDefault 0; R/W

[4] IEN_MABORTDefault 0; R/W

[5] IEN_MERRDefault 0; R/W

[6] IEN_PERRDefault 0; R/W

[7] IEN_SERRDefault 0; R/W

3.2.4 Interrupt Control (4Ah) [refer to Interrupt Status][0] INT_DISABLE

Default 1; R/WIf it is 1, then disable the INTA#. However, ISR can be set.

[5:1] ReservedDefault 0; Ronly

[6] IEN_FIFO_ERRDefault 1; R/W

[7] IEN_LOCALDefault 0; R/W

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3.2.5 Interrupt Status (49h)[0] ISR_TABORT_RCV

Default 0; R/C (Cleared after reading)Represents that Master detects the target aborting the transaction.

[1] ISR_DMA_ABORTDefault 0; R/CRepresents that DMA is aborted.

[2] ISR_DMA_ENDDefault 0; R/CRepresents that DMA is finished.

[3] ISR_TABORTDefault 0; R/CRepresents that Target aborts the transaction.

[4] ISR_MABORTDefault 0; R/CRepresents that Master aborts the transaction

[5] ISR_MERRDefault 0; R/CRepresents that Master Parity Error is detected.

[6] ISR_PERRDefault 0; R/CRepresents that Data Parity Error is detected.

[7] ISR_SERRDefault 0; R/CRepresents that Address Parity Error is detected.

3.2.6 Interrupt Status (48h)[6] ISR_FIFO_ERR

Default 0; R/CRepresents that the FIFO error between PCI & Local block is detected. If this bit is 1, CPUshould reset the IPSP processor by writing the software reset field defined in the IPSP

encryption/decryption core.[7] ISR_LOCAL

Default 0; R/CRepresents that IPSP local interrupt is detected. IPSP encryption/decryption core generates the local interrupt. If this bit is 1, CPU should read the local interrupt status register definedin IPSP encryption/decryption core.

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3.3 Security Core Registers

Address

2000h

31:24 23:16 15:8 7:0

Control Register

2004h Interrupt Enable Register

2008h

200Ch

2010h Descriptor Start Address Register

DMA Polling Interval Register

2014h Local Status Register

Interrupt Status Register

2018h Current Download Descriptor Address

201Ch

2020h

2024h Upload Descriptor Data

Current Download Polling Address

2028h Download Descriptor Polling Data

Current Upload Descriptor Address

3.3.1 Control Register (2000h, R/W)Bit 0 : SRST : Software Reset

1 : Software Reset EnableAuto ClearedOnly Internal Core Logic is cleared. Register Values are not cleared.Default : 0

Bit 1 : ReservedDefault : 1

Bit 2 : REG_ENDIAN : Register Data Endian (0:bypass, 1: Endian change)For Register Access (Including Polling Address, Descriptor Clear)Default : 0 (Little Endian to Little Endian)

Bit 3 : MEM0_ENDIAN : Memory Group0 Endian (0:bypass, 1: Endian change)For Memory Access(Source Context, Source Data, Destination1 Data, Destination2 Data)Default : 1 (Big Endian to Little Endian)

Bit 4 : MEM1_ENDIAN : Memory Group1 Endian (0:bypass, 1: Endian change)For Memory Access (Descriptor, Command, Result)Default : 0 (Little Endian to Little Endian)

Bit[31:6] : Reserved (0) ※ Local Data Structure is Little Endian※ Endian Format

202Ch Revision Number

2030h DMA Polling Gap

BYTE0 BYTE1 BYTE2 BYTE3

BYTE3 BYTE2 BYTE1 BYTE0

31

31 1

1

Big Endian

Little Endian

2034h Polling Counter Clear Command

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3.3.2 Interrupt Enable Register (2004h, R/W)Bit 0 : DMA Download Page End Interrupt EnableBit 1 : DMA Upload Page End Interrupt EnableBit 2 : DMA Upload Multi Packet End Interrupt EnableBit[15:3] : Reserved (0)Bit [25:16] : Error Status Interrupt EnableBit[31:26] : Reserved (0) Default: 0

3.3.3 Interrupt Status Register (2008h, R)Bit 0 : DMA Download Page EndBit 1 : DMA Upload Page EndBit 2 : DMA Upload Multi Packet End

(Activated when Upload Packet which is set INT_REQ in Descriptor)Bit[15:3] : Reserved (0)Bit [25:16] : Error StatusBit 16 : ERR_NOTEND : Length Error (Total End is not set at Total End)Bit 17 : ERR_NOLST : Length Error (PKT_LST is not set at Total End)Bit 18 : ERR_ENC2MAC : ENC2MAC Error (ENC->MAC Data is not Empty)Bit 19 : ERR_DST2 : Dst2 Data length differ from DescriptorBit 20 : ERR_DST1 : Dst1 Data Length differ from DescriptorBit 21 : ERR_ENC0ST : Packet Start with ENC Length 0Bit 22 : ERR_NOSECST : Packet Start with ENC or MAC DisabledBit 23 : ERR_OWST : Start Packet Input in Security engine Started alreadyBit 24 : ERR_NOST : No Start Packet Input After Security Engine Processing EndBit 25 : ERR_ENCWID : Encryption Input Data Width Error((T)DES:2DW, SEED, AES:4DW)

Bit[31:26] : Reserved (0) - When Error Reported Software Reset should be asserted by Software

Error Status occurs if Software does not meet this deviceDefault : 0

3.3.4 DMA Poling Interval Register (200Ch, R/W)Bit[31:0] : Descriptor Valid Check Polling Interval RegisterInterval Period = Core Clock Period * Register Value※ Default : 100(decimal)

3.3.5 Descriptor Start Address Register (2010h, R/W)Bit[31:0] : Descriptor Start Address from System CPU※ Default : 0

3.3.6 Local Status Register (2014h, R) (For Test)Bit [3:0] : Packet Processor State

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Packet Processor End for Current Page1001PKT_PROC_END

SEC Result Write1000SEC_RSLT_WR

SEC MAC Result Write0111SEC_MAC_WR

Security Core Running0110SEC_PROC

Check Start Error0101CHK_STERR

Start Error Flag Generation0100GEN_STERR

Read Source Context0011RD_SCON

Read Command0010RD_CMD

Read Descriptor0001RD_DSCR

IDLE State0000PKT_IDLE

CommentsState ValueState Name

Polling Download Descriptor State 1110RD_POLL

DMA Load Descriptor and parameter Set 1111LDARM

DMA Read Destination 2 Data1010DMA_RDDST2

DMA Read Results 1011DMA_RDRSLT

DMA Operation End1100DMA_RDDONE

Upload Descriptor Valid clear State 1101WR_UPDSCR

DMA Read Destination 1 Data1001DMA_RDDST1

DMA Read Descriptor1000DMA_RDDSCR

DMA Write Data Done0111DMA_WRDONE

DMA Write Source Data0110DMA_WRSRC

DMA Write Source Context0101DMA_WRSCON

DMA Download Read Command0100LD_WRCMD

DMA Download Write Command0011DMA_WRCMD

DMA Download Read Descriptor0010LD_WRDSCR

DMA Download Write Descriptor0001DMA_WRDSCR

DMA IDLE0000DMA_IDLE

CommentsState ValueState Name

Bit [11:8] : Memory StatusBit 8 : DMA Ready to Read Page 0Bit 9 : DMA Ready to Read Page 1Bit 10 : Ownership of Page 0Bit 11 : Ownership of Page 1

Bit [7:4] : DMA Control State

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Memory Status (Bit2,0 or Bit3,1)00 : Ready to DMA Write01 : Ready to DMA Read1x : Security Engine Processing

Bit[12] : SEC Processed Page(SEC_PAGE)Bit[13] : Upload DMA End page(DMA_RPAGE)Bit[14] : Download DMA End page(DMA_WPAGE) Bit[15] : LOC_BSY : Local Operation BusyBit[30:16] : Reserved (0)Bit[31] : Local Reset State(SRST is Not Completed)

(After Assert SRST, Check this bit ‘0’ for Normal Operation Start )3.3.7 Current Download Descriptor Address (2018h, R) (For Test)

Bit[31:0] : Current Downloaded Descriptor AddressDefault : 0

3.3.8 Current Upload Descriptor Address (201Ch, R) (For Test)Bit[31:0] : Current Uploaded Descriptor AddressDefault : 0

3.3.9 Current Download Polling Address (2020h, R) (For Test)Bit[31:0] : Current Downloaded Polling AddressDefault : 0

3.3.10 Upload Descriptor Data (2024h, R) (For Test)Bit[31:0] : Uploaded Descriptor DataDefault : 0

3.3.11 Download Descriptor Polling Data (2028h, R) (For Test)Bit[31:0] : Downloaded Descriptor polling DataDefault : 0

3.3.12 Revision Number (202Ch, R) [Year(2B), month(1B), version(1B)] : 0x20020002

3.3.13 DMA Polling Gap (2030h, R/W)Bit[31:0] : Descriptor Valid Check 1st Polling Gap RegisterInterval Period = Core Clock Period * Register Value※ Default : 16(decimal)

3.3.14 Polling Counter Clear Command (2034h, R/W)Bit 0 : It can be used to immediately polling data download If new data is prepared and no wait until

polling counter expiredBit[31:1] : Reserved (0)Default : 0

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4. EEPROM I/F

4.1 Programmed Parameter

IPSP processor has a EEPROM Interface operating in the value which can be set by the system vendor. All parameters described below line can be loaded at the power-up of device if a programmed EEPROM is attached. All PCI transactions are retried by the IPSP processor before loading all parameter from the EEPROM.

At first, IPSP reads the MSB of DEVICE_ID[7:0]. Then IPSP reads continually the bit value stored in EEPROM to LSB of INIT_LINE[7:0].

DEVICE_ID[15:0]VENDOR_ID[15:0]CLASS_CODE[23:0]REVISION_ID[7:0]SUB_SYSTEM_ID[15:0]SUB_VENDOR_ID[15:0]LATENCY[7:0]MAX_LATENCY[7:0]MIN_GRANT[7:0]INT_LINE[7:0]

4.2 Parameter Reading Status RegisterEEPROM I/F provides the status register defined in the configuration space of IPSP processor to indicate

the status of EEPROM reading operation.

Configuration Address at 54h has three bit register as follows.

bit[2] represents that EEPROM doesn’t exist

bit[1] represents that EEPROM doesn’t programmed

bit[0] represents that EEPROM loading is finished

Address

54h

31:24 23:16 15:8 7:0

2 1 0

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5. Operation Description

5.1 Data Structures5.1.1 Internal Memory (Packet Buffer) Structure

Descriptor(56Bytes)

Not Used(8Bytes)

Command(20Bytes)

Source(1536Bytes)

Destination1ENC Data

(1536Bytes)

Destination2MAC Data(20Bytes)

Result(16Bytes)

0x0000

0x0037

0x0038

0x003F

Not Used(12Bytes)

0x0040

0x0053

0x0054

0x005F

0x00C0

0x07FF

0x0DFF0x0E00

0x0F7F

Not Used(320Bytes)

0x06BF

0x06C0

Not Used(44Bytes)

Not Used(384Bytes)

Not Used(48Bytes)

0x0F930x0F94

0x0FBF

0x0FCF0x0FD0

0x0FFF

0x0800

0x0F80

0x0FC0

For Data width = Byte

SRC Context(68Bytes)

Not Used(28Bytes)

0x0060

0x00A30x00A4

0x00BF

Descriptor (0x0000)

Command (0x0040)

Source Context (0x0060)

Source (0x00C0)

Destination1 (0x0800)

Destination2 (0x0F80)

Result (0x0FC0)

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5.1.2 Descriptor Structure

DWORD0

31:24 23:16 15:8 7:0

DWORD1 CMD Length →

DWORD2 Command Block Start Pointer

Flags

DWORD3

DWORD4 Source Context Block Start Pointer

SRC Context Length

DWORD5

DWORD6 Source Data Block Start Pointer

SRC Data Length

DWORD7

DWORD8 Destination ENC Data Block Start Pointer

DST ENC Data Length

DWORD9

DWORD10 Destination MAC Data Block Start Pointer

DST MAC Data Length →

DWORD11

DWORD12 Result Block Start Pointer

Result Length →

DWORD13 Next Descriptor Start Pointer

Flags of DWORD0

DWORD0, bit0 : Valid

DWORD0, bit1 : Start (Start of Packet)

DWORD0, bit2 : Last (Last fragment of Large Packet)

DWORD0, bit3 : INT_REQ (Interrupt Generation Request)

Length (32bit word Base)

DWORD1 : Typical 20

DWORD3 : Typical 68

DWORD5, DWORD7 : Max 1536

DWORD9 : Max 5 (MD5(SHA1)-96:12, MD5:16, SHA1:20)

DWORD11 : Typical 16

Descriptor Usage

The unit of all length field is DWORD

For the packet larger than 1500 bytes, the packet is fragmented and multiple descriptors are used;

Command Block for only the 1st fragment of the packet is used and the command blocks for the other continuous fragments are ignored. Therefore, Total Source Countand Total Destination Count should be set to the number of DWORD for the entire packet, in order to meet the proper Packet Engine Operation.

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Source Context Block for only the 1st fragment is used.

Descriptor entries for Source Data Block, Destination ENC Data Block and Result Block (DWORD5, 6, 7, 8,11,12) are used regardless of the Start/Last bits (DWORD0)

Destination MAC Data Block are used for only the last fragment of packet. Corresponding blocks for the other fragments are ignored.

Both the Start and Last bit of DWORD0 must be set for the packet smaller than 1500 bytes.

After IPSP-1 completes the DMA write processing for a packet or a fragment of packet, it clears the Valid bit (DWORD0) of the corresponding descriptor in main memory.

If the value of Next Descriptor Start Pointer is 0x0, IPSP-1 enters IDLE State after current DMA operation, and re-triggered when Descriptor Start Address Register is written.

If Next Descriptor is not 0 than polling Next Descriptor while valid bit is set

5.1.3 Command Structure

DWORD0

31:24 23:16 15:8 7:0

Base Command Flags →

DWORD1 MAC Command Flags →

DWORD2 End Pointer+1

DWORD3 ENC Command Flags →

DWORD4

Start Pointer

End Pointer+1 Start Pointer

Base Command Structure (DWORD0)

DWORD0, bit0 : ENC_EN (ENC Core Enable)

DWORD0, bit1 : MAC_EN (MAC Core Enable)

MAC Command Structure (DWORD1, 2)

DWORD1,bit0 : NEW_KEY (HMAC Key Changed)

DWORD1,bit1 : HMAC_EN (HMAC Feature Enable)

DWORD1,bit2 : HASH_MD (Hash Algorithm Select, 0 : MD5, 1 : SHA1)

DWORD1,bit3 : TRUNC_EN (Hash Result Write format, 0 : normal, 1 : 96bits)

DWORD2,bit[13:0] : Start Pointer for AH processing

DWORD2,bit[29:16] : (End Pointer + 1) AH processing

Encryption Command Structure (DWORD3, 4)

DWORD3, bit0 : NEW_KEY (ENC Key Changed)

DWORD3, bit1 : NEW_IV (ENC IV Value Changed)

DWORD3, bit2 : ENC_DEC (ENC/DEC Mode), 0:Encryption, 1:Decryption

DWORD3, bit3 : ENC_OPMD (ENC Operation Mode), 0:ECB, 1:CBC

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DWORD3, bit[5:4] : ENC_ALGMD (ENC Algorithm Mode ),

0:DES, 1:3DES, 2:SEED, 3:AES

DWORD3, bit6 : ENC_KEYMD (ENC 3DES key Mode), 0:2 Key, 1: 3Key

DWORD3, bit[8:7] : ENC_KEYLEN(Encryption AES Key Length mode),

0:128bits,1:192bits,2:256bits

DWORD4, bit[15:0] : Start Pointer for ESP processing

DWORD4, bit[31:16] : (End Pointer + 1) for ESP processing

5.1.4 Source Context Structure

DWORD0~ DWORD4

31:24 23:16 15:8 7:0

HMAC_KEY(MD5 : 128 or SHA1 : 160bits)

DWORD5~ DWORD12

ENC_KEY(DES : 64bits, 3DES/ SEED/AES : 128bits, 3DES/AES : 192bits, AES : 256bits)

DWORD13~ DWORD16

ENC_IV(DES/3DES : 64 or SEED/AES : 128bits)

5.1.5 Result Structure

DWORD0

31:24 23:16 15:8 7:0

Basic Result Flags →

DWORD1

DWORD2

DWORD3

Error Status Flags

MAC Total Packet Read Counter ENC Total Packet Read CounterMAC Current Packet

Read CounterDestination MAC Data Write Counter →Destination ENC Data

Write CounterENC Current Packet

Read Counter

Base Result Structure

DWORD0, bit0 : TPE_FLAG : SEC Engine Processing End

DWORD0, bit1 : CPE_FLAG : Current Packet End by Source Count

DWORD0, bit16 : ERR_NOTEND : Length Error (Total End is not set at PKT_LST)

DWORD0, bit17 : ERR_NOLST : Length Error (PKT_LST is not set at Total End)

DWORD0, bit18 : ERR_ENC2MAC : ENC2MAC Error (ENC->MAC Data is not Empty)

DWORD0, bit19 : ERR_DST2 : Dst2 Write Data differ from Descriptor

DWORD0, bit20 : ERR_DST1 : Dst1 Write Data differ from Descriptor

DWORD0, bit21 : ENC0ST : Packet Start with ENC Length 0

DWORD0, bit22 : NOSECST : Packet Start with ENC or MAC Disabled

DWORD0, bit23 : ERR_OWST : Start Packet Input in Security engine Started already

DWORD0, bit24 : ERR_NOST : No Start Packet Input After Security Engine Processing End

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DWORD0, bit25 : ERR_ENCWID : Encryption Input Data Width Error

((T)DES : 2DW, SEED,AES : 4DW)

DWORD1,bit[15:0] : ENC Total Packet Read Counter

DWORD1,bit[31:16] : MAC Total Packet Read Counter

MAC Result Structure

DWORD2, bit[18:16] : Destination MAC Write Data Counter

DWORD2, bit[8:0] : MAC Current Packet Read Counter

ENC Result Structure

DWORD3, bit[24:16] : Destination ENC Write Data Counter

DWORD3, bit[8:0] : ENC Current Packet Read Counter

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5.2 Operations

Start

CPU write Descriptor Start Address Register

Polling Valid bit of the Descriptor

IPSP read in the Descriptor from systemmemory and write it to internal memory

IPSP read Command Block from system memory and write it to internal memory

Packet Processor analyze Command Block and set the parameters for Packet Engine

DMA Read Source Data from system memory and write them to internal memory

Packet Engine processes data, and write result to internal Memory

DMA read Destination Data Block and ResultBlock from internal memory , write them to

system memory and free buffer

IPSP clears the Valid bit of the current Descriptor in system memory.

Next Descriptor Start Pointer

0x0

Empty buffer exist

Yes

A

A

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6. Core Performance

Type Performance

MD5 170.5 Mbps SHA1 143.7 Mbps

DES 501.3 Mbps

3DES 172.9 Mbps

SEED 122.6 Mbps

DES+SHA1 139.0 Mbps DES+MD5 162.3 Mbps

3DES+SHA1 140.4 Mbps

3DES(ENC)+MD5 154.6 Mbps

SEED(ENC)+SHA1 111.6 Mbps

SEED(ENC)+MD5 113.8 Mbps

6.1 Test Conditions- Calculation Area : From Local Buffer Memory Write done To Security Processed Data Write done

- Packet Length : 1504Bytes

- Core Operation Clock : 33MHz

- HMAC Mode Active

- Encryption CBC Mode

- TDES : 3Key Mode

- Not Included PCI Interface access time

Type Performance

AES(128key) 365 .9 Mbps

AES(192key) 312.3 Mbps

AES(256key) 272.3 Mbps

3DES(DEC)+MD5 165.7 Mbps

SEED(DEC)+MD5 122.5 Mbps

SEED(DEC)+SHA1 122.5 Mbps AES(128key)+MD5 168.0 Mbps

AES(128key)+SHA1 142.2 Mbps AES(192key)+MD5 167.5 Mbps

AES(192key)+SHA1 142.1 Mbps AES(256key)+MD5 167.3 Mbps

AES(256key)+SHA1 141.3 Mbps

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7. Chip Dimensions

seePin Detail

AA

A

21

L

L

c

θ

Pin Detail1

y

Dimension in inchSymbol

A

A

A

b

c

D

E

H

H

L

L

- - 0.130 - - 3.30

Min Nom Max Min Nom Max

Dimension in metric (mm)

0.0041

2

D

E

1

-

0.112

0.012

0.006

0.551

0.787

0.026

0.740

0.976

0.047

0.094

-

-

-

0.117

0.016

0.010

0.556

0.792

0.032

0.752

0.988

0.055

0.103

0.004

12

0.10

2.73

0.25

0.10

13.87

19.87

0.50

18.49

24.49

1.00

2.21

-

0

-

2.85

0.30

0.15

14.00

20.00

0.65

18.80

24.80

1.20

2.40

-

-

-

2.97

0.40

0.25

14.13

20.13

0.80

19.10

25.10

1.40

2.62

0.10

12

0.107

0.010

0.004

0.546

0.782

0.020

0.728

0.964

0.039

0.087

-

0˚ ˚ ˚ ˚

e

nSYS

Tec h

IPSP2

1

100 81

80

51

5031

30

H

D

E H

b

D

E

e

QFP

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seePin Detail

AA

A

21

L

L

c

θ

Pin Detail1

y

Dimension in inchSymbol

A

A

A

b

c

D

E

H

H

L

L

y

θ

- - 0.063 - - 1.60

Min Nom Max Min Nom Max

Dimension in metric (mm)

0.0041

2

D

E

1

-

0.055

0.220

0.006

0.551

0.787

0.026

0.630

0.866

0.024

0.040

-

-

-

0.057

0.270

0.010

0.555

0.791

-

0.634

0.870

0.300

-

0.005

7

0.10

1.35

0.22

0.10

13.90

19.90

-

15.90

21.90

0.45

-

-

0

-

1.40

0.30

0.15

14.00

20.00

0.65

16.00

22.00

0.60

1.00

-

-

-

1.45

0.38

0.25

14.10

20.10

-

16.10

22.10

0.75

-

0.0767

0.548

0.170

0.004

0.547

0.783

-

0.626

0.856

0.014

-

-

0˚ ˚ ˚ ˚

e

nSYS

Tech

IPSP2

1

100 81

80

51

5031

30

H

D

E H

b

D

E

e

LQFP

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8. Electrical Specification

AC and DC Information1. DC CharacteristicsThe I/O library of TCB773S provides TTL and CMOS interface options. Recommended operating conditions and electrical characteristics are summarized in the following table.

VOL

VOH

VT-

VT+

VT

VIH

VIL

VDD

Parameter

0.2V0.2V0.2V0.2V0.2V0.2V

0.9V1.05V

1.9V2.15V

1.4V1.65V

3.3V

Typ.

2.4V2.4V2.4V2.4V2.4V2.4V

2.0V0.7VDD

3.0V

Min.

0.4V0.4V0.4V0.4V0.4V0.4V

Type Pxx02x: IOH = 2mAType Pxx04x: IOH = 4mAType Pxx08x: IOH = 8mAType Pxx12x: IOH = 12mAType Pxx16x: IOH = 16mAType Pxx24x: IOH = 24mA

Output Low Voltage

VDDVDDVDDVDDVDDVDD

Type Pxx02x: IOH = -2mAType Pxx04x: IOH = -4mAType Pxx08x: IOH = -8mAType Pxx12x: IOH = -12mAType Pxx16x: IOH = -16mAType Pxx24x: IOH = -24mA

Output High Voltage

TTL CompatibleCMOS Compatible

Schmitt Trig. high to low Threshold

TTL CompatibleCMOS Compatible

Schmitt Trig. low to high threshold point

TTL CompatibleCMOS Compatible

Threshold Point

TTL CompatibleCMOS Compatible

Input High Voltage

0.8V0.3VDD

TTL CompatibleCMOS Compatible

Input Low Voltage

3.6VSupply Voltage

Max.Condition

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2. AC CharacteristicsTiming information contained in this databook is measured at typical condition, whereas

VDD = 3.3V

Temperature = 25 C

Process – typical case

Transition time (from 0.1 VDD to 0.9 VDD or vice versa ) = 0.1ns

Propagation Delay

The propagation delay is measured from the 50% point of the input to the 50% point of theoutput. For storage elements, the propagation delay is measured from the 50% point of the rising or falling edge of clock (or enable signal) to the 50% of the output Level shifters and schmitt triggers have different threshold points for VIH and VIL. Please refer to the individual data sheet for this information.

The propagation delay information provided for each cell in this databook is for estimation only. A rough rule of thumb to include the interconnect loads while calculating the delay is to double the input load. That is, to estimate the delay of a gate driving one fanout, look up the delays values with 2 standard loads in the delay table. The extra one load is to count for the interconnect load.

Voltage, Temperature and Process Derating Factors

Delays shown in the databook are based on normal conditions (25 , 3.3V, normal process).The actual delays of each cell are a complex function of operating environment, process conditions, input slope and output loading. If the worse case or the best case delays of the cells are not provided, the derating factors presented here (provided with TSMC design kits) can be used to estimate the delay in predicted conditions.

The following derating factors are normalized averaged over a representive group of commonly used cells under a variety of process, temperature, and voltage conditions.

Power Supply Voltage Derating Factors (KV)

The power supply voltage vs. derating factor can be shown as:

0.937

3.6V

1.000

3.3V

1.084

3.0V

1.201

2.7V

0.8891.371KV

3.9V2.4VVoltage

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Junction Temperature Derating Factors (Kt)

junction temperature vs. derating factor can be shown as:

1.0000.9830.9560.9130.8700.830Kt

150 C125 C100 C75 C55 C40 CTemperature Factor

1.177

15 C

1.132

0 C

1.088

-25 C

1.053

-50 C

1.2281.026Kt

25 C-75 CTemperature Factor

(under the condition VDD = 3.3V)

Process Derating Factors (Kp)

0.7971.0001.258Kp

FastTypicalSlowProcess Factor

(under the condition VDD = 3.3V)

A derating factor is simply a multiplier of nominal delays. Propagation delays at other than typical conditions can be estimated using the following equation:

tDELAY = tDELAY (nominal )x Kv x Kt x Kp

Kv = derating factor for VDD

Kt = derating factor for junction temperature

Kp = derating factor for process

Example:

For a specific cell with tDELAY = 1.0ns obtained from datasheet (typical case), its propagation delay in a worse case condition defined as:

VDD = 3.3V,

junction temperature = 100 C ,

slow process,

can be obtained as: tDELAY (w. c.) = 1.00 x 1.084x 1.132 x 1.258=1.544(ns).

That is, the propagation delay in worse case should be roughly scaled by 1.544 factor.

Definitions of Storage Element Timing Constraints

This section defines the timing constraints for storage elements.Setup Time : The minimum time interval a signal must be stable at a specified input before the active clock edge occurs or the enable signal finishes.

Hold Time : The minimum time interval a signal must be stable at a specified input after the active clock edge occurs or the enable signal finishes.

High/Low-Minimum Signal Width : The time interval between the 50% points of the leading and trailing edges of the HIGH or LOW of a pulse waveform.

Release – Release Time for Clear or Set : The minimum time Clear or Set is released before the clock transitions activated.

Removal – Removal Time for Clear or Set : The minimum time the clock transition is effective before Clear or Set activated.

Page 32: Data SheetData Sheet - 엔시스텍 datasheet.pdf · Data SheetData SheetData Sheet 1.01.01.0 ... IP Hdr AH Hdr ESP Hdr Data ESP trlr Original Data (Transport, ... 28h Card Bus CIS

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Confidential

Document Version 1.0

8. Application Notes

CBE3#

MO

N6

AD1

C8

104

MO

N3

3.3P

CIV

CC

3.3V

3.3PCIVCC

AD

20

3.3P

CIV

CC

MON14

3.3P

CIV

CC

AD6

AD

18

C3

104

3.3P

CIV

CC

AD

15

AD30

AD

22

C7

104

AD9

AD

14

AD27

C5

104

3.3PCIVCC

AD4

AD

21

R33.9K

MO

N13

C1

104

STOP#

C2

104

MO

N10

MO

N2

C4

104

3.3P

CIV

CC

CBE2#

AD25

CBE1#

AD

23

RST#

R5 1K

AD

13

3.3PCIVCC

SW1

SW DIP-5

12345

109876

FRAME#

RN1

4.7K

1 2 3 45678

AD29

C9

104

AD

24

PAR

MON15

AD8

IDSEL

DEVSEL#

AD26 CBE0#

MO

N11

CBE0#

GNT#

3.3V

R1

4.7K

AD

19

AD7

AD

16

MO

N0

R21K

AD

11

SW2 SW PUSHBUTTON

AD[0:31]

3.3V

MO

N7

AD

17

TRDY#

AD3

3.3V

MO

N12

AD

12

R6 1K

IRDY#

AD2

PERR#

3.3V

MO

N9

U2

93LC56B

1234 5

8CSSKDIDO VSS

VCC

CLK

MO

N1

AD28

AD10

R43.9K

AD5

AD0

MO

N8

INTA#

MO

N4

IPSP-2nSYS Tech

U1

IPSP-2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

3132333435363738394041424344454647484950

515253545556575859606162636465666768697071727374757677787980

81828384858687888990919293949596979899

100

VC

CA

D24

AD

23A

D22

AD

21A

D20

AD

19A

D18

AD

17V

SS

VC

CC

BE

2#FR

AM

E#

IRD

Y#

TRD

Y#

DE

VS

EL#

STO

P#

PE

RR

#S

ER

R#

VS

SV

CC

PA

RC

BE

1#A

D16

AD

15A

D14

AD

13A

D12

AD

11V

SS

VCCAD10AD9AD8

CBE0#AD7AD6AD5AD4VSSVCCAD3AD2AD1AD0

EEDOEEDI

EECSEECK

VSS

VC

CE

EA

N0

EE

AN

1S

CA

NE

NTS

TMD

0TS

TMD

1M

ON

SE

L0M

ON

SE

L1M

ON

SE

L2V

SS

SC

AN

_CLK

CLK

_MD

BR

ST#

MO

N0

MO

N1

MO

N2

MO

N3

MO

N4

MO

N5

VS

SV

CC

MO

N6

MO

N7

MO

N8

MO

N9

MO

N10

MO

N11

MO

N12

MO

N13

VS

S

VCCMON14MON15INTA#RST#CLKGNT#REQ#AD31VSSVCCAD30AD29AD28AD27AD26AD25CBE3#IDSELVSS

AD31

SERR#

MO

N5

REQ#

C6

104

3.3PCIVCC