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1 Jean-Luc Poupat (Airbus Defense and Space) DASIA 2018 DAHLIA Very High Performance Microprocessor for Space Applications Context & Objectives DAHLIA is an answer to the H2020 topic COMPET-1-2016: Critical Space Technologies for European Strategic Non-DependenceDAHLIA is an ARM-based System on Chip implemented in 28nm FDSOI technology designed to boost competitiveness and ensure strategic non dependence of future European Space equipment. DAHLIA brings to reality what was still a dream few years ago, addressing the new expectations and new mindset of Space industry in a single chip. DASIA 2018 DAHLIA 2

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Page 1: DASIA 2018 DAHLIA - Copie (2)dahlia-h2020.eu/wp-content/uploads/2018/06/DASIA... · DAHLIA is an ARM-based System on Chip implemented in 28nm FDSOI technology designed to boost competitiveness

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Jean-Luc Poupat (Airbus Defense and Space)DASIA 2018

DAHLIAVery High Performance Microprocessor for Space Applications

Context & Objectives

DAHLIA is an answer to the H2020 topic “COMPET-1-2016: Critical Space Technologies for European Strategic Non-Dependence”

DAHLIA is an ARM-based System on Chip implemented in 28nm FDSOI technology designed to boost competitiveness and ensure strategic non dependence of future European Space equipment.

DAHLIA brings to reality what was still a dream few years ago, addressing the new expectations and new mindset of Space industry in a single chip.

DASIA 2018 DAHLIA2

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IntroductionDAHLIA Key FeaturesARM TechnologyConclusion

Context & Objectives

DAHLIA is an answer to the H2020 topic “COMPET-1-2016: Critical Space Technologies for European Strategic Non-Dependence”

DAHLIA is an ARM-based System on Chip implemented in 28nm FDSOI technology designed to boost competitiveness and ensure strategic non dependence of future European Space equipment.

DAHLIA brings to reality what was still a dream few years ago, addressing the new expectations and new mindset of Space industry in a single chip.

DASIA 2018 DAHLIA4

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Organization

7 partners from 4 countries involving the main actors of European Space industry

ST France, coordinator

Airbus D&S Germany & France

Thales Alenia Space Italy & France

ISD Greece & NanoXplore France

ESA and CNES are also part of an Advisory Group

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Development Plan

Kick-Off in 2017

Development in 2017-2018-2019

SoC FPGA prototyping end 2018

DAHLIA protoypes available end 2019

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IntroductionDAHLIA Key FeaturesARM TechnologyConclusion

FeaturesSoC ServicesSoC Services

DMA ControllersDMA Controllers

Debug & TraceDebug & Trace

Enhanced Internal AXI Interconnect Cross‐BarEnhanced Internal AXI Interconnect Cross‐Bar

ScalabilityScalability

Embedded FPGAEmbedded FPGA

External Memory InterfaceExternal Memory Interface

DDR w/ECCDDR w/ECC

Clocks & PLLClocks & PLL

ConnectivityConnectivity

CCSDS OBTCCSDS OBT

FLASH w/ECCFLASH w/ECC

On chip MemoryOn chip Memory

eRAM w/ECCeRAM w/ECC

eROMw/ECCeROMw/ECC

GPIOGPIO

UARTUART

CAN, SPICAN, SPI

1553 BC & RT1553 BC & RT SpW RMAPSpW RMAP

HSSL (SpFi)HSSL (SpFi)

CCSDS TM & TCCCSDS TM & TC

GNSSGNSS

ARM‐based Real Time CPUARM‐based Real Time CPU

Cortex‐R52Cortex‐R52 Cortex‐R52Cortex‐R52 Cortex‐R52Cortex‐R52 Cortex‐R52Cortex‐R52

SecuritySecurity

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V&T MonitoringV&T Monitoring

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STM 28nm FDSOI Technology

• Intrinsically immune to Latch-up• Reduced pitch size providing good dose tolerance • Very good immunity to SEU

• 28nm FDSOI is combined with RHBD solutions such as Hardened DFF, EDAC on memories or Embedded Configuration Memory Integrity Check (CMIC) for the embedded FPGA

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Designed for ultimate performances

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Up to 600 MHz per core with 2.2 DMIPS/MHz more than 1000 DMIPS per core

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Designed for ultimate performances

DASIA 2018 DAHLIA11

Enhanced Internal AXI Interconnect Cross‐BarEnhanced Internal AXI Interconnect Cross‐Bar

Master 1Master 1 Master 2Master 2

Slave 1Slave 1 Slave 2Slave 2 Slave 3Slave 3

Optimized Network Interconnect Architecture based on AXI with QoS

Master 1Master 1

Slave 3Slave 3

Enhanced AXI Interconnect Cross‐BarEnhanced AXI Interconnect Cross‐Bar

Designed for ultimate performances

DASIA 2018 DAHLIA12

Enhanced Internal AXI Interconnect Cross‐BarEnhanced Internal AXI Interconnect Cross‐Bar

Master 1Master 1 Master 2Master 2

Slave 1Slave 1 Slave 2Slave 2 Slave 3Slave 3

Optimized Network Interconnect Architecture based on AXI with QoS

Master 1Master 1

Slave 3Slave 3

Master 2Master 2

Slave 2Slave 2

Enhanced AXI Interconnect Cross‐BarEnhanced AXI Interconnect Cross‐Bar

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IntroductionDAHLIA Key FeaturesARM TechnologyConclusion

Why looking at ARM ?

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Why looking at ARM ?

Wide dissemination of ARM CPUs in embedded systems Available as an RTL IP Core with full access to source code ARM ecosystem Code density better that its competitors Many development languages European technology (UK & FR) Low power Now focused on safety critical applications

with the highest level of certification

New SW development & environment ARM market business plan Radiation assessment

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ARM technology selection

DASIA 2018 DAHLIA16

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ARM Cortex-R family

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Cortex-R52

• ARM’s most advanced processor for safety

• Dedicated for safety applications including automotive, industrial and healthcare

• Simplifies integration of software in complex safety systems

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Cortex-R52

Safety features dedicated to random errors

• ECC protected memory

• Software BIST libraries

• Error management

• Level 2 MPU

• New privilege level

• …

DASIA 2018 DAHLIA19

Cortex-R52 simplifies real-time SW isolation

• ARMv8-R introduces new privilege level

• Create ‘sandboxes’ protected from other SW

• Monitor / Hypervisor manages SW separation and simplifies isolation of tasks

• Real time switch rapidly between tasks and ‘sandboxes’

• Simplified integration of complex SW from multiple sources

Optimized for TSP

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IntroductionDAHLIA Key FeaturesARM TechnologyConclusion

DAHLIA Keypoints

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Powerful combination of innovative technology

adapted for Space

Optimized to support time and space partitioning for centralized avionics

Designed to face the new challenges of Space such as

mega-constellations

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DASIA 2018 DAHLIA23

DASIA 2018 DAHLIA24

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Conclusion

The DAHLIA H2020 project covers the development of a rad-hard high performance quad-core ARM R52 SoC in 28nm FDSOI technology, with eFPGA for flexibility and key IPs.

It will enable faster and cost-efficient development of products for multiple platform and payload Space applications.

Beyond Space applications, DAHLIA will enable the convergence with terrestrial applications benefiting from the strong ARM ecosystem.

DAHLIA brings to reality what was still a dream few years ago, addressing the new expectations and new mindset of Space industry in a single chip.

DASIA 2018 DAHLIA25

dahlia-h2020.eu

Copyright Airbus Defence and Space

More details on DAHLIA are available the project website