D Flip Flop

D flip-flop is Modified form of SR flip-flop

In the basic SR flip flop circuit the indeterminate input condition of "SET" = logic "0" and "RESET" = logic "0" is forbidden.

In SR Flip Flop when R=S=0 or R=S=1 , the outputs Q and Q' either don't change or they are indeterminate(Invalid)

Clk S R Qn +1

0 X X Qn1 0 0 Qn1 0 1 01 1 0 11 1 1 invali

d

• Truth Table of SR Flip-Flop

Construction

In order to overcome the shortcomings of RS flip flop , the D flip flop was designed .

The D flip-flop is the most important of the clocked flip-flops as it ensures that inputs S and R are never equal to one at the same time.

D-type flip-flops are constructed from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for a single D (data) input.

Symbol &Circuit Diagram(using Nand Gates)

Truth table Of D Flip Flop Clk D Qn +1

0 x Qn

1 0 0

1 1 1

Characteristic Table & Equation

Q D Q(n+1)

0 0 0

0 1 1

1 0 0

1 1 1

1

1

0 1

0

1

D

Q

Q(t+1)=D

Working of D-F F D=0

0 0

0

0

0

1

1

1

1

1

Clk D Qn +1

0 x Qn

1 0 0

1 1 1

Working of D FF when D=1

Clk D Qn +1

0 x Qn

1 0 0

1 1 1

1

1

1

1

100

00

1

Advantages

Simplify Complex Circuits

Less chance of mistakes

Intermidiate state is Eliminated

Applications

Data transfer Counters Registers Frequency divider circuits