csci 641 – eeng 641 1 csci-641/eeng-641 computer architecture khurram kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 641 – EENG 641 1

CSCI-641/EENG-641

Computer Architecture

Khurram Kazi



Course Outline

CSCI 641 – EENG 641 2

Studying Computer architecture from different perspective Processors such as

General Purpose Processors (RISC) Specialty processors (Network Processors, security processors … )

Single Board Computers Typical PC architecture Buses (AMBA Bus) Memory architectures

SRAM, DRAM, Non-volatile RAM (Flash, SD Card), Hard Disk … Addressing

Inputs/Outputs USB, HDMI, Video Port, Mouse, Keyboard …

Hardware design simulations VHDL (VHSIC Hardware Description Language)

Firmware Assembly Language

Assembly Language <> Hardware functional blocks



Desired outcomes

CSCI 641 – EENG 641 3

Have a solid fundamental understanding of processors’ architectures

Memory and I/O architectures Instruction level parallelism and related it to pipelining Calculate the throughput with and without stalls Hardware and Assembly language design fundamentals Using processors to build single board computers Partitioning of a design in hardware and firmware/software



Recommend Books

CSCI 641 – EENG 641 4

1. Computer Architecture: A Quantitative Approach, 4th Edition, Morgan Kaufman Publishers, Elsevier, 2007, ISBN: 0-12-370490-1

2. Digital Design and Computer Architecture, David Harris and Sarah Harris, Elsevier, 2007, ISBN 13: 978-0-120370497-9

3. HDL Programming Fundamentals; VHDL and Verilog, Nazeih, B. Botros, Da Vinci Engineering Press, 2006, ISBN: 1-58450-855-8



Software Tools Used

CSCI 641 – EENG 641 5

Mentor Graphics ModelSimVHDL simulatorYou can download student version of it from http://model.com/content/modelsim-pe-

student-edition-hdl-simulationWill be using it extensivelyWill be using it extensivelyRISC instruction set simulatorhttp://sourceforge.net/projects/spimsimulator/

files/



Grading Policy

CSCI 641 – EENG 641 6

Homework/Short Quizzes 30%1 Midterm Test 30%Final Project 40%Will start to discuss Final Projects towards

the mid-semesterOral and written communication skills will

be stressed in this course and taken into account in the final grade

Cheating/ plagiarism Cheating/ plagiarism Automatic F Automatic F



CSCI 641 EENG 641 7

Do’s and Don’ts for the Final Project

DO NOT use any off the shelf general purpose microprocessor or any other circuit taken from the publicly available information base and claim it is your work. I will know if you did!!

Come up with your own functional idea and Implement it. Be creative! Have a system’s perspective and see how your design fits in the system.

By mid semester have a good idea of your project

Team of 2 students working on the same project is allowed. Each team member’s task within the project should

be explicitly defined.



CSCI 641 – EENG 641 8

Teamwork Encouraged: How much collaboration is acceptable

Since time will be short, I would encourage you to help out your fellow students with the “Usage of the Tools” but not the Design. Informing me of the help received is strongly encouraged, i.e. give credit where credit is due!!

Helping fellow students with Tools usage and class participation will be rewarded in the final grade.



CSCI 641 – EENG 641 9

Block Diagram of a Generic Processor

Central Processing Unit

Registers

ALU Control Unit Clock

Memory Storage Unit I/O Device #1 I/O Device #1

Dat

a bu

s

Addr

ess

Bus

Cont

rol B

us



CSCI 641 – EENG 641 10

Basic Microcomputer Design Clock: Synchronizes internal operations of the CPU with

other components of the system ALU: performs arithmetic operations such as +, -, *, /, and

logic operations such as AND, OR, NOT … Memory Storage: Instructions and data are held while

computer program is running. Receives request for data from CPU, transfers data from RAM to CPU, or CPU into memory

Bus: is a group of wires that transfer data from one part of the computer to another. Data bus: transfers instructions and data between CPU and memory Control bus: synchronizes actions of all devices attached to the

system bus Address bus: holds address of the instructions and data when the

currently executing instruction transfers data between CPU and memory



CSCI 641 – EENG 641 11

Instruction Execution Cycle Fetch: The control unit fetches instruction from instruction

queue and increments the instruction pointer (IP), AKA, Program Counter

Decode: Control Unit decodes the instruction’s function to determine what the instruction will do and sends the appropriate signals to the ALU

Fetch Operands: If instruction uses an input operand located in memory, the control unit uses a read operation to retrieve the operand and copy it into internal registers.

Execute: ALU executes the instruction using the named registers and internal registers as operands and sends the output to the named registers and/or memory. ALU then updates status flags to indicate the processor state

Store output operand: If the output operand is in memory, the control unit uses a write operation to store the data



CSCI 641 – EENG 641 12

Testbench (GeneratorIn C or HDL)

Testbench (AnalyzerIn C or HDL)

HDL Design

(VHDL or Verilog

Reference Model( In C or Functional HDL)

HDL (Hardware Description Language) can typically be either VHDL or Verilog

Typical HDL Design Environment



CSCI 641 – EENG 641 13

Overview of VHDL

Library and Library Declarations Entity DeclarationArchitectureConfiguration



CSCI 641 – EENG 641 14

Overview of VHDL

Package (typically compiled into the destination library) contains commonly used declarationsConstants maybe defined hereEnumerated data types (Red, Green, Blue)Combinatorial functions (performing a

decode function; returns single value)Procedures (can return multiple values)Component declarations



CSCI 641 – EENG 641 15

Overview of VHDL

Package (typically compiled into the destination library) contains commonly used declarationsConstants maybe defined hereEnumerated data types (Red, Green, Blue)Combinatorial functions (performing a

decode function; returns single value)Procedures (can return multiple values)Component declarations



CSCI 641 EENG 641 16

Overview of VHDL: Example of Library Declaration

LIBRARY library_name; --commentsUSE library_name.package_name.package_parts; -- VHDL is case

-- insesitiveTypically there are three different libraries used in a design1) ieee.std_logic_1164 (from the ieee library)2) standard (from the std library)3) work (work library) std_logic_1164: Specifies the STD_LOGIC (8 levels) and the

STD_ULOGIC (9 levels) multi-values logic systems std: It is a resource library (data types, text i/o, etc.) work: This is where the design is saved

Library ieee; -- A semi-colon (;) indicates the end of a statement or a declaration

USE ieee.std_logic_1164.all; -- double dash indicates a comment.

Library std;USE std.standard.all;

Library work;USE work.all;



CSCI 641 – EENG 641 17

Overview of VHDL: Entity

EntityDefines the component name, its inputs and

outputs (I/Os) and related declarations. Can use same Entity for different architecture

to study various design trade offs.Use std_logic and std_logic_vector(n downto 0):

they are synthesis friendly.Avoid enumerated type of I/Os. Avoid using port type buffer or bidir (unless you have

to)




Overview of VHDL: Syntax of an Entity

1. ENTITY entity_name ISPORT (

port_name : signal_mode signal type;port_name : signal_mode signal type;……….);

END entity_name;

2. ENTITY nand_gate ISPORT ( a: IN std_logic; b: IN std_logic; x: OUT std_logic);

END nand_gate;or3. ENTITY FiveInput_nand_gate IS

PORT ( a: IN std_logic_vector (4 downto 0); x: OUT std_logic);

END FiveInput_nand_gate;




Overview of VHDL: Architecture

ArchitectureDefines the functionality of the designNormally consists of processes and concurrent

signal assignmentsSynchronous and/or combinatorial logic can be

inferred from the way functionality is defined in the Processes.

Avoid nested loopsAvoid generate statements with large indices Always think hardware when developing code! One way of looking at is how would you implement the digital

design on the breadboard; mimic the same thought process in writing VHDL code




Overview of VHDL: Syntax of an Architecture

ARCHITECTURE architecture_name OF entity_name IS[declarations]

BEGIN(code)

END architecture_name;

ARCHITECTURE myarch OF nand_gate ISBEGIN

x <= a NAND b;END myarch;



CSCI 641 – EENG 641 21

Overview of VHDL: Basic Components of an

Architecture

Primarily Architecture consists of Process Concurrent Statements

Code in VHDL is inherently concurrent (parallel) All processes and concurrent statements are evaluated in parallel (i.e.

at the same time) Code inside the process is executed sequentially

The code execution is based on sensitivity list (signals that act as triggers in the execution of the respective process

Process can describe Asynchronous (combinatorial logic) Synchronous (clocked logic)

Concurrent Statements Typically combinatorial logic is implemented using concurrent

statements



CSCI 641 – EENG 641 22

Overview of VHDL

ConfigurationPrimarily used during the simulations

If there are multiple architectures for the same entity, the “configuration” can be used to instruct the simulator which architecture should be used during the simulation.



CSCI 641 – EENG 641 23

Some useful practices

Organize Your Design WorkspaceDefine naming convention (especially if

multiple designers are on the projectCompletely Specify Sensitivity ListsTry to separate combinatorial logic from

sequential logic



CSCI 641 – EENG 641 24

Clk D

0 1

0 1

Truth table

t 1 t 2 t 3 t 4

Time

Clock

D

Q

Timing diagram

Q(t+1)

Q(t)

D flip-flop

D Q

Clock

Graphical symbol

0 – Q(t)1 –




LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESS ( Resetn, Clock ) BEGIN

IF Resetn = '0' THEN Q <= '0' ;

ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

D flip-flop with asynchronous reset

D Q

Clock

Resetn




8-bit register with asynchronous resetLIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY reg8 ISPORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;

Resetb, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;

END reg8 ;

ARCHITECTURE Behavior OF reg8 ISBEGIN

PROCESS ( Resetb, Clock )BEGIN

IF Resetb = '0' THENQ <= "00000000" ;

ELSIF Clock'EVENT AND Clock = '1' THENQ <= D ;

END IF ;END PROCESS ;

END Behavior ;`

Resetn

Clock

reg8

8 8

D Q




N-bit register with asynchronous resetLIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY regn ISGENERIC ( N : INTEGER := 16 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Resetb, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END regn ;

ARCHITECTURE Behavior OF regn ISBEGIN

PROCESS ( Resetb, Clock )BEGIN

IF Resetb = '0' THENQ <= (OTHERS => '0') ;

ELSIF Clock'EVENT AND Clock = '1' THENQ <= D ;

END IF ;END PROCESS ;

END Behavior ;

Resetn

Clock

regn

N N

D Q




LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY regn ISGENERIC ( N : INTEGER := 8 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

resetb, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END regn ;

ARCHITECTURE Behavior OF regn ISBEGIN

PROCESS (Clock)BEGIN

if (resetb = ‘0’) then Q <= (others <= ‘0’);

elsif (Clock'EVENT AND Clock = '1' ) THENIF Enable = '1' THEN

Q <= D ;END IF ;

END IF;END PROCESS ;

END Behavior ;

N-bit register with reset

QD

Enable

Clock

regn

N N




LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all ;

ENTITY upcount ISPORT ( Clock, Resetn, Enable : IN STD_LOGIC ;

Q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)) ;END upcount ;

8-bit up-counter with asynchronous reset (1)

Q

Enable

Clockupcount

8

Resetn




ARCHITECTURE Behavior OF upcount ISSIGNAL Count : integer ;

BEGINPROCESS ( Clock, Resetn )BEGIN

IF Resetn = '0' THENCount <= 0 ;

ELSIF (Clock'EVENT AND Clock = '1') THENIF Enable = '1' THEN Count <= Count + 1 ;END IF ;

END IF ;END PROCESS ;Q <= conv_std_logic_vector (Count, 8) ;

END Behavior ;

8-bit up-counter with asynchronous reset (2)

Q

Enable

Clockupcount

4

Resetn




Shift Registers




Shift register

D QSin

Clock

D Q D Q D Q

Q(3) Q(2) Q(1) Q(0)

Enable




Shift Register With Parallel Load

D(3)

D Q

Clock

Enable

SinD(2)

D Q

D(1)

D Q

D(0)

D Q

Q(0)Q(1)Q(2)Q(3)

Load





ENTITY shift4 ISPORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

Enable : IN STD_LOGIC ;Load : IN STD_LOGIC ;Sin : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END shift4 ;

4-bit shift register with parallel load (1)

Q

Enable

Clockshift4

4

D

Load

Sin

4




ARCHITECTURE Behavior_1 OF shift4 ISBEGIN


IF Clock'EVENT AND Clock = '1' THENIF Load = '1' THEN

Q <= D ;ELSIF Enable = ‘1’ THEN

Q(0) <= Q(1) ;Q(1) <= Q(2); Q(2) <= Q(3) ; Q(3) <= Sin;

END IF ;END IF ;

END PROCESS ;END Behavior_1 ;

4-bit shift register with parallel load (2)

Q

Enable

Clockshift4

4

D

Load

Sin

4

Another way of writing the code

Q(2 downto 0) <= Q(3 downto 1)

Q(3) <= Sin;





ENTITY shiftn ISGENERIC ( N : INTEGER := 8 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Enable : IN STD_LOGIC ;Load : IN STD_LOGIC ;Sin : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END shiftn ;

N-bit shift register with parallel load (1)

Q

Enable

Clockshiftn

N

D

Load

Sin

NVHDL allows this, but not recommended when writing code for synthesis




ARCHITECTURE Behavior OF shiftn ISBEGIN


IF (Clock'EVENT AND Clock = '1' ) THENIF Load = '1' THEN

Q <= D ;ELSIF Enable = ‘1’ THEN

Genbits: FOR i IN 0 TO N-2 LOOPQ(i) <= Q(i+1) ;

END LOOP ;Q(N-1) <= Sin ;

END IF;END IF ;

END PROCESS ;END Behavior ;

N-bit shift register with parallel load (2)

Q

Enable

Clockshiftn

N

D

Load

Sin

N

Keep in mind this shift register DOES NOT have reset.




4 bit Shift Register (1)

library ieee;use ieee.std_logic_1164.all;ENTITY shiftreg is generic(N : integer := 4); port(clk : in STD_LOGIC;

sin : in STD_LOGIC; enable : in STD_LOGIC;

SOUT : out std_logic);end shiftreg;

architecture ssr of shiftreg isbeginp0: process (clk, enable)variable REG : std_logic_vector(N-1 downto 0); begin if (ENABLE = '0') then

SOUT <= '0'; REG := (others => '0');elsif rising_edge(CLK) then

REG := REG(N-2 downto 0) & SIN; SOUT <= REG(N-1); end if;end process p0;end ssr;




LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all ;

ENTITY upcount ISPORT (Clock, :IN STD_LOGIC; Resetn : IN STD_LOGIC;Enable : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);Decode_7 : OUT STD_LOGIC) ;END upcount ; ARCHITECTURE Behavior OF upcount IS

SIGNAL Count : integer ;BEGIN

PROCESS ( Clock, Resetn )BEGIN IF Resetn = '0' THEN Count <= 0 ; ELSIF (Clock'EVENT AND Clock = '1') THEN IF Enable = '1' THEN

Count <= Count + 1 ; END IF; END IF ;END PROCESS ;Q <= conv_std_logic_vector (Count, 8) ;

8-bit up-counter with some decoded outputsRawDecode: Process (count)Begin

IF (count = 7) then Decode_7 <= ‘1’;ELSE Decode_7 <= ‘0’;END IF;

END Process;END Behavior ;

ClockedDecode: Process (clk)Begin if (clock’event and clock = ‘1’) then

IF (count = 7) then Decode_7 <= ‘1’;ELSE Decode_7 <= ‘0’;END IF;

end if;END Process;

What is the difference between the 2 processes?




Arrays

Arrays are collection of objects of the same type. They can be one-dimensional (1D), two-dimensional (2D), or one-dimensional-by-one-dimensional (1Dx1D).

0 0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 0 1 1

0 1 1 0 0 1

Scalar 1D 1D x 1D0 1 0 1

1 0 0 0

0 1 0 0

1 0 1 0

2D data arays




Arrays Scalars: BIT, STD_LOGIC, STD_ULOGIC and

BOOLEAN Vectors: BIT_VECTOR, STD_LOGIC_VECTOR,

STD_ULOGIC_VECTOR, INTEGER, SIGNED, and UNSIGNED

There are no pre-defined 2D or 1D x 1D arrays Hence need to be specified by the user To do so, a TYPE must be first defined, then

the new SIGNAL, VARIABLE or CONSTANT can be declared using that data type.




Arrays: Syntax of defining an array

To specify a new array type:TYPE type_name IS ARRAY (specificaiton) of data_type;

To make use of the new array type:SIGNAL signal_name: type_name [:= initial value];

Example:TYPE row IS ARRAY (7 downto 0) OF STD_LOGIC; -- 1D arrayTYPE matrix IS ARRAY (0 to 3) of row; -- 1Dx1D arraySIGNAL x: matrix -- 1Dx1D signal




Arrays: Syntax of defining an array

Another way of constructing the 1Dx1D arrayTYPE matrix IS ARRAY (0 to 4) of STD_LOGIC_VECTOR (7 DOWNTO 0)

Example: 2D arrayThe array below is truly two-dimensional. Notice that its construction is not based on vectors, but rather entirely on scalars

TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) of STD_LOGIC; --2D array




ROM (Read Only Memory)LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY rom is GENERIC ( bits: INTEGER := 8 -- # of bits per word

words: INTEGER := 8 ); -- # of words in the memory PORT ( addr : IN INTEGER RANGE 0 to words - 1;

data : OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));END rom;ARCHITECTURE rom of rom IS TYPE vector_array is ARRAY (0 to words -1) of STD_LOGIC_VECTOR (bits-1 DOWNTO 0);

CONSTANT memory: vector_array := ( "00000000","00000010","00000100","00001000","00010000","00100000","00000010","01000000","10000000",);

BEGIN

data <= memory(addr);END rom;




RAM (Random Access Memory)LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY ram is GENERIC ( bits: INTEGER := 8 -- # of bits per word

words: INTEGER := 8 ); -- # of words in the memory PORT ( wr_ena : IN STD_LOGIC; -- write enable

clk : IN STD_LOGIC; -- clock addr : IN INTEGER RANGE 0 to words -1; data_in: : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0); data_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0));

END ram

ARCHITECTURE ram of ram IS TYPE vector_array is ARRAY (0 to words -1) of STD_LOGIC_VECTOR (bits-1 DOWNTO 0); signal memory: vector_array;

BEGIN PROCESS (clk, wr_ena) BEGIN

IF (clk'EVENT AND clk = '1') THEN IF (wr_ena = '1') THEN memory(addr) <= data_in; END IF;END IF;

END PROCESS; data_out <= memory(addr);END ram;

csci 641 – eeng 641 1 csci-641/eeng-641 computer architecture khurram kazi

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