ELECTRICAL ENGINEERING DEPARTMENTCalifornia Polytechnic State University

CPE/EE 229/269 Computer Design and Assembly Language Programming (3/1) Winter 2007Instructor: James G. HarrisPrerequisite: CPE/EE 129/169. Concurrent: CPE/EE 269 Laboratory (same lecture and lab enrollment)Objective: This course is the second in a sequence of three digital design courses: CPE/EE 129/169, CPE/EE 229/269, and CPE/EE 329, each four units consisting of three units of lecture and one unit of laboratory. Students enrolled in CPE/EE 229 will be enrolled in the laboratory section with the same lecture instructor. Therefore, the lecture and laboratory will be integrated together, and only one grade will assigned for each. In addition, all sections will be taught with the material developed by Dr. Richard Sandige as presented below. See tentative course outline for details. Textbook: Richard S. Sandige, Fundamentals of Computer Design with VHDL and Assembly Language Programming, Copyright 2007; available from El Corral Bookstore under CPE 229/269 READER for about $35. References recommended: Sudhakar Yalamanchili, VHDL: A Starter's Guide (2nd, paperback), Prentice-Hall, 2004M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals, Prentice-Hall, latest editionCourse Website References: http://www.ee.calpoly.edu/~jharris prepared by instructor for specific lecture and lab information for these CPE/EE 229/269 enrollment sections.http://www.ee.calpoly.edu/~rsandige prepared by Dr. Richard Sandige for supplemental materials for CPE/EE 229/269. Required Xilinx Support: It is your responsibility to get the ISE WebPACK up and running so you can use it. Download and install the latest version of the free ISE WebPACK at http://www.xilinx.com/support/mysupport.htm. Click on Download and go to ISE WebPACK and click on Download. It is very important that you get this software up and running immediately so you can use it on you own computer for writing programs in VHDL. You may find interesting information on the following Xilinx University Program web site at the following URL: http://www.xilinx.com/univ/index.htm Xilinx Tutorials: For a tutorial by Xilinx and other tutorials on the web, click on Help then Tutorials on the Menu Bar in Xilinx - Project Navigator, also see http://toolbox.xilinx.com/docsan/xilinx8/books/manuals.pdf. Required Lab Equipment: The experiments will be performed on the Digilent Nexys board which you must purchase. The Digilent Nexys board is about $99. You can contact the IEEE Student Branch (20-115) to purchase the Nexys board.Laboratory Assignments: For the laboratory component of the course, students will work in two person groups, and perform the experiments per the schedule presented in the course outline below. Each group is expected to perform the work at home and in the laboratory, using the downloaded free ISE WebPACK and purchased Digilent Nexys board. Course Homework: The same homework will be assigned by both instructors of CPE/EE 229/269 this quarter. In these sections, the weekly homework assignments will be collected, corrected, graded, and returned. Students are encouraged to work in study groups, but each student must turn in their own work. Late homework will not be accepted.Course exams: There will be two midterm exams following the tentative course outline below to be specified later, and one comprehensive final. Grades: The grade will be based upon the following proportion; note that improvement or degradation in student performance over the quarter will be used to resolve borderline cases:

Homework 5%Laboratory Experiments 25%

Two Midterms (20% each)* 40%Final Exam 30%

* These sections will follow the same offer (repeated verbatim below) extended by Dr. Sandige in his student handout CPE/EE 229/269 to his classes; contact Dr. Sandige directly to receive any credit:

"If you are the first person to report a technical error in the READER, you will earn 1 point credit. It is to your advantage to read and study the READER and report all errors that you fine directly to me. You may also report errors by e-mail. You better make it in a timely fashion or someone else may get the 1 point credit. The credit adds up but does not count as part of the 20% of you Laboratory Reports or the 40% of your Final Exam. [Note that Dr. Sandige is using a different grading proportion; for these sections the points only count towards the two midterm proportion.] You may also earn credit for grammatical errors at the rate of 3 grammatical errors = 1 technical error. Spelling errors are ok but not commas and periods. If you make a good suggestion that can improve the READER, it might be worth 1 technical error."Office Hours: MWF 910-1000; MW 210-300; 20-305 x65708; email: jharris@calpoly.edu. I will be in lab (20-100) Tuesday from 8-11 and 12-3, and can be available after the opening discussion on a non-interference basis with the lab students in that section taking priority. Other times available by arrangement.Notes to the student: This is the first time that the course and laboratory materials have been used. It is expected that there may be situations that have not been anticipated, and that changes will have to be made to maximize learning. Therefore, this syllabus and the course outline are tentative, and may be changed; any changes or modifications will be discussed with the students and documented. In addition, there may be times that the instructor must be absent from the class in order to participate in national engineering education activities; other assistance will be provided during these periods. Your patience and understanding are appreciated.

CPE/EE 229/269 COURSE OUTLINE - tentative Winter 2007

Week Reading(sections) CommentsM 1/8 1.1-11, 2.1-2.5 introduction; review of combinational and sequential logic circuits; design of

combinational logic circuits; state machinesT 1/9 exp 0: first experiment, first week, ee 269 - download documentation from

http://www.ee.calpoly.edu/~rsandige/CPE269ExperimentR.doc (bring your Nexys board)M 1/15 HolidayT 1/16 1.12 exp c1 - designing and testing a display decimal decoder circuit with vectorsW 1/17 2.5-12, 3.1-8 HW 1 due; design of counters; mealy and moore architecture for finite state

machinesM 1/22 3.8-10, 4.1-10 HW 2 due; metastability; computer architecture; instruction set (ISA) and

programmer's register model (PRM); very basic computer 1 (VBC1); EASY1 assembler for VBC1T 1/23 2.13 exp c2 – designing a cylon robot eye circuitM 1/29 5.1-11, 6.1-8 HW 3 due; VBC1 assembly language programming; mux and bus steering

circuits; loadable register circuits; designing VBC1 input and output circuitsT 1/30 3.11 exp c3 – designing an up(0-4)/down(9-5) 10 state counter systemM 2/5 7.1-6 HW 4 due; instruction memory and loading program counter design; debouncing

circuitsT 2/6 6.9 exp c4 - designing and testing VBC1 (data path unit)M 2/12 8.1-6 HW 5 due; VBC1 multiplexed display system: 4-to-1 mux, hex decoder,

counter, and 2-to-4 decoderT 2/13 7.7 exp c5 - designing and testing VBC1 (instruction memory unit)F 2/16 HolidayM 2/19 9.1-9.13 HW 6 due; instruction decoderT 2/20 8.7 exp c6 - designing and testing VBC1 (monitor systems)M 2/26 10.1-8 HW 7 due; arithmetic logic unit; shifter circuits: barrel and shift registersT 2/27 9.14 exp c7 - designing and testing VBC1 (instruction decoder)M 3/5 11.1-4 HW 8 due; integration of VBC1 subsystems; load, single step and run frequency

integration; T 3/6 10.9 exp c8 - designing and testing VBC1 (arithmetic logic unit)M 3/12 11.4 HW 9 due; two pulse circuit for instruction cycle; VBC1 verification testingT 3/13 11.5 exp c9 - designing and testing VBC1 (final hardware design)

Final Exam – Comprehensive