cosc 3330/6308 solutions to first problem set
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COSC 3330/6308 Solutions to First Problem Set. Jehan-François Pâris September 2012. First problem (I). A program consists of two parts, namely One part is purely sequential and takes 64 s to complete Another part takes 1,024 s when run on a uniprocessor architecture - PowerPoint PPT PresentationTRANSCRIPT
COSC 3330/6308Solutions to
First Problem Set
Jehan-François PârisSeptember 2012
First problem (I)
A program consists of two parts, namely– One part is purely sequential and takes 64 s to
complete – Another part takes 1,024 s when run on a
uniprocessor architectureCan be easily decomposed into two or more
parallel tasksSpeedup would be proportional to the number
of tasks executing in parallel.
First problem (II)
What would be the speedups that the program would achieve if it was to run on computers with 2, 4, 8, 16, and 32 processors?
What would be the maximum speedup that the program would achieve if it was to run on a computer with an unlimited number of processors?
Answer (I)
Will use Amdahl's law
in
on
TTTT
Speedup
Answer (II)
Sequential Part (s)
Number of Proc.
Other Part (s)
Total (s)
Speedup
64 1 1,024 1,088 NA
64 2 512 576 1.889
64 4 256 320 3.400
64 8 128 192 5.667
64 16 64 128 8.500
64 32 32 96 11.333
64 infinity 0 64 17.000
Second problem
Simplify the two following logical expressions:
– ABC'D' + AB'D' + ACD + CD
– (A BC) (B + A)
using both algebra and Karnaugh maps.
First expression (I)
ABC'D' + AB'D' + ACD + CD =
ABC'D' + AB'D' + CD =
ABC'D' + AB'D' + AB'C'D' + CD =
AC'D' + AB'D' + CD
First expression (II)
C'D' C'D CD CD'
A’B’ 0 0 1 0
A’B 0 0 1 0
AB 1 0 1 0
AB’ 1 0 1 1
AC'D' + AB'D' +CD
Second expression (I)
(A BC) (B + A) =
(A(BC)' + A'BC) (A + B) =
(AB' + AC' + A'BC) (A + B) =
AB' + AC' + A'BC + ABC' =
AB' +AC' +A'BC
Second expression (II)
A B C BC A BC A+ B PRODUCT
F F F F F F F
F F T F F F F
F T F F F T F
F T T T T T T A'BC
T F F F T T T AB'C'
T F T F T T T AB'C
T T F F T T T ABC'
T T T T F T F
Second expression (III)
B'C' B'C BC BC'
A’ 0 0 1 0
A 1 1 0 1
AB' + AC' +A'BC
Second expression (IV)
A'B' A'B AB AB'
C’ 0 0 1 1
C 0 1 0 1
AB' + AC' +A'BC
Third problem
Simplify the expression
– (ABC)' (A + DE)' (A BC) (B + E)
and convert it to a form that can be represented using a programmable logic array.
Answer (I)
(ABC)' (A + DE)' (A BC) (B + E) Let us do it in two parts
– (ABC)' (A + DE)' =(A' + B' + C')(A'(DE)') =(A' + B' + C')(A'(D' +E') =A'(D' +E') + A'B'(D' +E') +A’C’(D’ +E’) =A'D' +A'E'
Answer (II)
The second part is – (A BC) (B + E) =
(A(BC)' + A'BC)(B + E) =(AB' + AC' + A'BC)(B + E) =ABC' + A'BC + AB'E + AC'E + A'BCE
Answer (III)
The product is– (A'D' +A'E')
(ABC' + A'BC + AB'E + AC'E + A'BCE) =A'BCD' + A'BCE' + A'BCD'E = A'BCD' + A'BCE'
Sum of products can be represented by a PLA
I checked the answer on a spreadsheetwith 25 rows and 14 columns
Fourth problem
Implement the double implication operation:– A B = AB +A’B’
using only NAND gates.
NAND gates
A nand B = (AB)' = A' + B'
nand (A) nand nand(B) = (A'B')' = A + B
nand(A nand B) = (AB)'' = AB
nand(nand(A) nand nand(B)) =(A' B')'' = A'B'
Answer
AB
A'+B'
A
B
A+B((A + B)(A' + B')' =(A + B)' + (A' + B')' =A'B' +AB
I started with a solution havingmore NANDs and simplified it
Fifth problem
Build a regular D flip-flop using an R’S’ latch, that is, an RS latch with inverted values for R and S, and as few NOR gates as possible.
NOR gates
A nor B = (A + B)' = A' B'
nor (A) nor nor(B) = (A' + B')' = AB
nor(A nor B) = (A+B)'' = A + B
nor(nor(A) nor nor(B)) =(A' + B')'' = A' + B'
From S'R' latch to D flip-flop
S'R' has three inputs– S' sets latch when S' = 0
and clock = 1– R' resets latch when R' = 0
and clock = 1 D flip-flop
– Stores a 1 at clock transition when input is 1– Stores a 0 at clock transition when input is 0
S'
R'
Q'
Q
Clock
D flip-flop using an S-R latch
X
Clock
S
R
Q
Q'
Clock
D flip-flop using an S'-R' latch
X
Clock
S'
R'
Q
Q'
Clock
Introducing NORs
X
Clock
S'
R'
Q
Q'
Clock
(Clock+Clock')'=ClockClock'
Note
The solution is fairly simple because we assumed that the R'S' latch had a clock entry
Solution for R'S' latch without clock input is more complex
Q
Q’R’
S’
Sixth problem (I)
Build a synchronous sequential circuit with– Two inputs, respectively named P—for
plus—and M—for minus– Two outputs respectively named O—for
overflow—and U—for underflow
Sixth problem (II)
The transitions are:
Answer
Eight states– Three flip-flops X Y Z
Will consider separately– How P inputs affect X, Y, Z– How M inputs affect X, Y, Z– When counters outputs O and U
How P inputs affect Z
Y'Z' Y'Z YZ YZ'
P'X' 0 1 1 0
P'X 0 1 1 0
PX 1 0 0 1
PX’ 1 0 0 1
Solution
Z = P'Z + PZ' – Will use a T flip-flop triggered by P
How P inputs affect Y
Y'Z' Y'Z YZ YZ'
P'X' 0 0 1 1
P'X 0 0 1 1
PX 0 1 0 1
PX’ 0 1 0 1
Solution
Y = P'Y + PYZ' + PY'Z – Will use a T flip-flop triggered by PZ
How P inputs affect X
Y'Z' Y'Z YZ YZ'
P'X' 0 0 0 0
P'X 1 1 1 1
PX 1 1 0 1
PX’ 0 0 1 0
Solution
X = P'X + PXY' + PXZ' + PX'YZ – Will use a T flip-flop triggered by PYZ
How M inputs affect Z
Y'Z' Y'Z YZ YZ'
M'X' 0 1 1 0
M'X 0 1 1 0
MX 1 0 0 1
MX’ 1 0 0 1
Solution
Z = M'Z + MZ' – Will use a T flip-flop triggered by M
How M inputs affect Y
Y'Z' Y'Z YZ YZ'
M'X' 0 0 1 1
M'X 0 0 1 1
MX 1 0 1 0
MX’ 1 0 1 0
Solution
Y = M'Y + MYZ + M Y'Z' – Will use a T flip-flop triggered by MZ'
How M inputs affect X
Y'Z' Y'Z YZ YZ'
M'X' 0 0 0 0
M'X 1 1 1 1
MX 0 1 1 1
MX’ 1 0 0 0
Solution
X = M'X + MXY + MXZ +MX'Y'Z' – Will use a T flip-flop triggered by MY'Z'
How P inputs affect O
Y'Z' Y'Z YZ YZ'
P'X' 0 0 0 0
P'X 0 0 0 0
PX 0 0 1 0
PX’ 1 0 0 0
Solution
O = PXYZ
How M inputs affect U
Y'Z' Y'Z YZ YZ'
M'X' 0 0 0 0
M'X 0 0 0 0
MX 0 0 0 0
MX’ 1 0 0 0
Solution
U = MX'Y'Z' – Will use a T flip-flop triggered by MY'Z'
Summary
Flip-flops– Z: T flip-flop triggered by P + M– Y: T flip-flop triggered by PZ + MZ'– X: T flip-flop triggered by PYZ + MY'Z'
Outputs– O = PXYZ– U = MX'Y'Z'