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PRESENTATION ON:VERILOG-2001,SYSTEM VERILOG AND VERILOG-AMS

PRESENTED BY:TOYA NATH ACHARYA

ME in Communication EngineeringKathmandu University

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WHAT IS VERILOG?

Hardware Description LanguageThe Verilog HDL is an IEEE standard - number 1364

Used in the design, verification, and implementation ofdigital logic chips at the register transfer level (RTL) level

of abstraction

Used for verification through simulation, for timinganalysis, for test analysis (testability analysis and faultgrading) and for logic synthesis.

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HISTORY OFVERILOG:

Beginingo Invented during

1983/1984 at5/14/12

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FEATURE OF VERILOG-2001 :oComma used in sensitive list

always @ (a, b, c, d, e) in verilog-2001

always @ (a or b or c or d or e) in earlier versiono Combinational logic sensitive list

always @ (*) in verilog-2001always @ (a or b or c or d or e) in earlier version

o

In Verilog 1995, default data type is net and its width is 1bit. In Verilog 2001 the default data type is wire and

width is adjusted automatically.o Register data types

reg b, c, d = 0; in earlier versionreg signed b, c, d = 0; in verilog-2001

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CONTD......o New operators

> : shift right, to be used on signed data type** : exponential power operator

o Port Declaration

module memory_v95 ( read, write);input read; output write;module memory_v2001 (input read, output write)

o

Multi Dimensions Arrayreg [7:0] address; in earlier versionreg [15:0] array [0:255][0:255]; in verilog-2001

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CONTD......o A function with added automatic keyword allows thefunction to be called recursively.o

Generate Blocks is possible to use it for loopsto produce multiple instants.oFile IO

In Verilog 1995, file IO was limited to reading

hex files into memory array using readmemhand writing file using $display and $monitor.But in Verilog 2001, following operations canperformed.

C or C++ type file operation (likechecking end of file)

Reading charaters from file from a fixedlocation

Reading a formated lines in file5/14/1266


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FEATURE OF SYSTEM-VERILOG :o Combines the features of Hardware Description Languages

such as Verilog and VHDL with features from specialized

Hardware Verification Languages, together with featuresfrom C and C++

o Improves the productivity,readability,and reusability ofverilog based code.

o

SystemVerilog adds important new constructs to Verilog-2001, including

Supports the C built-in types, with the meaninggiven by the implementation C compiler

SystemVerilog adds string, and class data types SystemVerilog offers several integer data types,

representing a hybrid of both Verilog and C datatypes such as int,longint etc

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CONTD....

Integer types use integer arithmetic and can besigned orunsigned

The realdata type is from Verilog-2001, and is thesame as a C double. The shortreal data type is aSystemVerilog data type, and is the same as a Cfloat

SystemVerilog includes a string data type, whichis a variable size, dynamically allocated array of

bytes Operator overloading

jump statements,returns,break, continue void functions

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CONTD....

default arguments pass by reference

Interfaces to encapsulate communication Clocking blocks to support cycle-based

methodologies Program blocks for describing tests

The procedural assignment operators (


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FEATURE OF VERILOG -AMS:o Derived from IEEE std 1364-2005 Verilog HDL.o Consists of the complete IEEE std 1364-2005 Verilog HDL

specification, an analog equivalent for describing analogsystems ( Verilog-A ), and extensions to both for specifyingthe full Verilog-AMS HDL

o applicable to both electrical and non-electrical systems

descriptiono used to describe discrete (digital) systems and mixed-signal

systemso Features:

Signals of both analog and digital types can bedeclared in the same module initial, always, and analog procedural blocks

can appear in the same module

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CONTD........

both analog and digital signal values can beaccessed from any context (analog or digital) in the

same module digital signal values can be set (write ) from any

context outside of an analog procedural block analog potentials and flows can only receive

contributions (write operations) from inside ananalog procedural block

when hierarchical connections are of mixed type(i.e., analog signal connected to digital port or

digital signal connected to analog port), user-defined connection modules are automaticallyinserted to perform signal value conversion

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SYSTEM,FLOW AND POTENTIAL:

Fig: System

Fig: Kirchhoffs law 5/14/121212


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PROGRAMMING ...o Verilog/AMS is a superset of the Verilog digital HDL so all

statements in digital domain work as in Verilogo

In analog domain, some new operators are defined, forexample the "


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PROGRAMMING ...

omodule voltage_amplifier (out, in);input in;

output out;voltage out, // Discipline voltage defined elsewhere

in; // with access function V()parameter real GAIN_V = 10.0;

analogV(out)


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SYNTAX FOR ANALOG PROCEDURAL BLOCK

o analog_construct ::=analog analog_statement

|analog initial analog_function_statementanalog_statement ::=

{ attribute_instance } analog_loop_generate_statement| { attribute_instance } analog_loop_statement

| { attribute_instance } analog_case_statement| { attribute_instance } contribution_statement| { attribute_instance } indirect_contribution_statement| { attribute_instance } analog_event_control_statement

analog_statement_or_null ::=analog_statement| { attribute_instance } ;

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CO C S C C O S S


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CONNECT SPECIFICATION STATEMENTSo specification of which connect module is used, including

parameterization, for bridging given discrete and continuous

disciplineo connectrules_declaration ::=connectrules connectrules_identifier ;{ connectrules_item }

endconnectrulesconnectrules_item ::=connect_insertion| connect_resolution

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CONNECT SPECIFICATION EXAMPLE


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CONNECT SPECIFICATION EXAMPLE

connectmodule elect_to_logic(el,cm);input el; output cm; reg cm;

electrical el; ddiscrete cm;endmodule

connectmodulelogic_to_elect(cm,el);

input cm; output el;ddiscrete cm; electrical el;analogV(el)


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REFERENCES:

oLanguage Reference ManualAnalog & Mixed-Signal Extension to Verilog HDL

Version 2.3.1 June 1, 2009 Accellerao Language Reference Manual

SystemVerilog 3.1aAccelleras Extensions to Verilog

o

http://www.asic-world.com

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http://www.asic-world.com/http://www.asic-world.com/


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THANKYOU !!!

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