Comparison of microprocessors: a graphical approach

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  • Euromicro, 1977 North-Holland Publishing Co., Amsterdam


    DoAspinall, MoHoBarton, E.L.Dagless

    Dept . o f E lec t r i ca l & E lec t ron ic Eng ineer ing , Un ivers i ty Co l lege , Swansea , Wa les , UoK.


    Selecting a microprocessor for a particular application is a task frequently faced today. Manufacturers usually present hardware character- istics consistently, but vary considerably in the way they describe instruction sets, which makes microprocessor comparison tedious and time- consuming. The high cost of software production suggests that care should be taken to choose the correct instruction set for a particular applica- tion.

    This paper discusses briefly how various features of the instruction set, such as general layout, size of processor state vector, range of address- ing modes, bit-handling capability, and range of control orders, affect the ease with which the device may be progrcx~med.

    Current aids to facilitate the comparison of instruction sets are discussed, and the case is made for a less detailed, graphical method to help in the initial stages of microprocessor selec- tion.

    The problems involved in presenting a graphical description of the instruction set are outlined, and solutions are proposed.

    Finally, a BASIC program is described which, given a sur~ary of a device's instruction set in a concise form, produces a graphical representa- tion of it.


    Th is paper i s the resu l t o f work wh ich has been car r ied out to p roduce a graph ica l method o f ins t ruc t ion set representat ion as an a id to mic ro - p rocessor comparison.

    Severa l i te ra t ions were requ i red to choose the present char t fo rmat , and some o f the arguments fo r and aga ins t d i f fe rent layouts a re out l ined be low.

    The char ts p roduced have been used in severa l mic roprocessor workshops , to p resent an overv iew of the instruction sets of various devices, with- out resorting to manufacturers' descriptions, and have been well received.

    Work has also been undertaken to speed up the production of charts by employing a BASIC program A brief descript ion of this is given at the end of the paper .


    I t may be s ta t ing the obv ious to say that any program act ion wh ich the mic roprocessor per fo rms must be wr i t ten in te rms o f the ins t ruc t ion set ; but th i s shows jus t how impor tant that d imens ion i s . Knowledge o f the ins t ruc t ion set imp l ies knowledge o f p rocessor w id th , reg is te r layout , and memory address ing capab i l i ty , as we l l as the range and t iming o f funct ions wh ich can be per - fo rmed. There are cer ta in features o f an ins t ruc - t ion set wh ich prov ide a use fu l ind icat ion o f i t s su i tab i l i ty fo r a par t i cu la r purpose , and wh ich are wor thy o f fu r ther d i scuss ion .

    F ive years ago , i t wou ld have seemed unusua l fo r a log ic des igner to be asked to choose a compute~ yet today such a task i s qu i te commonplace . The mic roprocessor ch ip has made the processor jus t another item in the designer's armoury of compo- nents. Unfortunately, the IO00-fold drop in the price of processors has not been matched by a similar reduction in their complexity

    The microprocessor chosen for a part icular appl ication must have the correct hardware characteristics, just as for any other electronic component. Microprocessor manufacturers usual ly list these characterist ics - e.go, power supplies, clock inputs required - in a reasonably standard form.

    However , what makes mic roprocessors more complex than o ther components i s the i r added d imens ion - ins t ruc t ion set , the presentat ion o f wh ich i s not s tandard ised . S ince the product ion o f the so f tware const i tu tes a ma jor cos t o f deve lop ing a microprocessor -based sys tem, bet ter s tandard - i sa t ion cou ld be advantageous .


    2 .1 Genera l Layout

    A we l l l a id out ins t ruc t ion set , i . e . one wh ich does not p lace apparent ly a rb i t ra ry res t r i c t ions on the funct ion /operand 1 /operand 2 combinat ions wh ich are ava i lab le , reduces the t ime necessary to become fami l ia r w i th the processor .

    2 .2 P rocessor Width

    The w idth o f the processor determines the accuracy to wh ich ar i thmet ic can be per fo rmed. Doub le length work ing may be requ i red , and "Add w i th Car ry" o r "Subt rac t w i th Bor roW' ins t ruc t ions wou ld fac i l i ta te th i s .

    Where non-ar i thmet ic p rocess ing i s be ing car r ied out , p rocessor w id th may be cons idered as the number o f I /O s igna ls wh ich can be processed in para l le l .

    2 .3 P rocessor S ta te (Vector )

    P rocessor s ta te [2 ] i s the in fo rmat ion he ld in


    the processor between ins t ruc t ions . The s i ze o f the processor s ta te depends on the number o f on - ch ip reg is te rs ava i lab le , inc lud ing genera l reg i - s te rs , p rogram counter , index reg is te rs , s tack po in ters (o r hardware s tack) and s ta tus reg is te rs .

    A programmer work ing a t mach ine leve l can use a se t o f on -ch ip reg is te rs as i f they were the s im- p le var iab les o f a h igh- leve l language, p rov ided there a re su f f i c ient fo r each one to be ass igned a mean ing fo r the durat ion o f the a lgor i thm. I f access to these reg is te rs i s much fas ter than to ma in memory, a cons iderab le inc rease in execut ion speed may be ach ieved . However , when the proces~ or s ta te i s la rge , there a re more reg is te rs to be saved when dea l ing w i th a context change.

    I t may be noted that compi le rs a re un l i ke ly to take advantage o f fas t on -ch ip reg is te rs because o f the inconven ience o f dea l ing w i th the i r l im i ted address space ( typ ica l ly ~8) [6 ]

    2 .4 . Range o f Address ing Modes

    Every operand wh ich i s invo lved in an operat ion per fo rmed by a mic roprocessor res ides on the ch ip , in ma in memory, o f in an input /output por t . Neg- lec t ing speed requ i rements , a p rocessor o f fe r ing s imp ly d i rec t address ing o f a l l these locat ions wou ld be ab le to execute the same a lgor i thms as one w i th a more soph is t i ca ted ins t ruc t ion set . However , improvements to the bas ic ins t ruc t ion set a re o f ten made, and take two main fo rms :

    ( i ) S ing le o rders a re prov ided to g ive access to data s t ruc tures , such as s tacks and tab les , where normal ly severa l o rders would be requ i red .

    ( i i ) Shor t o rders , w i th one or more operands imp- l i ed , a re in t roduced to save space , as i t i s not a lways necessary to spec i fy exp l i c i ty the address o f a l l the operands . For such orders , the 'number o f addresses per ins t r - uc t ion ' i s sa id to be reduced .

    These improvements amount to the prov is ion o f add i t iona l address ing modes impl ied, ind i rect , indexed, and auto increment /autodecrement - and can great ly s impl i fy the programming of cer ta in types of rout ine. These modes are cons idered in more detai l below.

    2.4 .1 .Implied Addressing

    To per fo rm an operat ion such as A + B + C, where A, B and C res ide in ma in memory, a th ree-address o rder wou ld seem su i tab le . Such orders a re not usua l on mic roprocessors because o f the ch ip com- p lex i ty wh ich would be invo lved ; in any case , severa l s to re accesses wou ld be requ i red to read an order conta in ing so many address b i t s . There - ~ore , ins t ruc t ions w i th some operands imp l ied are o f ten found. In fac t , cer ta in a lgor i thms are neat ly imp lemented us ing th i s type o f ins t ruc t ion , when the s tack i s an imp l ied operand . For example , cons ider eva luat ing

    A * B - C * D (a l l operands in ma in memory)

    In reverse Po l i sh :


    In code :






    A (I address: stack + A)

    B (i address: stack + stack * B)

    C (i address: stack + C)

    D (I address: stack + stack * D)

    (O address : s tack s tack -s tack)

    The resu l t i s le f t on the top o f the s tack . Addressing

    I n ind i rec t address ing , the address o f the oper - and i s he ld in a reg is te r o r a memory locat ion , not in the ins t ruc t ion i t se l f . A l te r ing the address a l lows the same p iece o f code to access d i f fe rent ma in memory locat ions .

    2.4 .3 .Indexed Addressing

    This is an extens ion of ind i rect address ing. In this case, the operand address is formed by add- ing a va lue ( typ ica l ly 8 bits) f rom the instruc- t ion to the contents of an index reg is ter (typi- ca l ly 16 bits). As an example of an appl icat ion, cons ider a rout ine to access cor respond ing ent r - i es in severa l tab les ; assume that the index reg is te r i s used as a po in ter to s tep down the f i r s t tab le . An ent ry in that tab le may be accessed , us ing ind i rec t address ing v ia the index reg is te r . The cor respond ing ent r ies in the o ther tab les may be accessed , us ing indexed address ing , where the va lue in the ins t ruc t ion determines wh ich tab le i s used .

    2 .4 .4 . Autoincrement/Autodecrement Addressing

    Usua l ly , the on ly hardware - imp lemented s tack to be found in a mic roprocessor i s the one used in terna l ly to save subrout ine re turn addresses . P rogrammers o f ten requ i re to use a s tack fo r o ther purposes , such as sav ing add i t iona l va lues when nest ing subrout ines , o r eva luat ing express - ions ( see Sect ion 2 .4 .1 ) . P rogrammer-access ib le hardware s tacks a re ra re , and se ldom deeper than 16 leve ls . So f tware - imp lemented s tacks a re there - fo re o f ten employed . An area o f ma in memory i s used to ho ld the s tack ent r ies , and a reg is te r ( s tack po in ter ) i s used to po in t to the top -o f - s tack ent ry . To PUSH an i tem onto the s tack , the s tack po in ter i s decremented (o r inc remented) , and the i tem wr i t ten to the locat ion wh ich i t now addresses . To POP an i tem o f f the s tack , read- ing i s per fo rmed before the s tack po in ter i s inc remented (o r decremented) . The s tack i tems are sa id to be accessed us ing auto inorement /auto - decrement address ing . In th i s paper , that te rm i s reserved fo r the predecrement /post increment and pre increment /postdecrement combinat ions which are requ i red fo r t rue s tack operat ions .

    Severa l var ia t ions a re poss ib le : the s tack may increase or decrease in memory address f rom top


    to bot tom, and the po in ter may po in t to the top i tem or to the next empty space .

    2 .5 .B i t Hand l ing

    H i t man ipu la t ion i s inva luab le in the rea l - t ime app l i ca t ions fo r wh ich mic roprocessors a re most o f ten used . Sh i f t ins t ruc t ions a re use fu l here , espec ia l l y the ra re ly found var iab le - length sh i f t s wh ich a l low easy access to any b i t in , say , a va l - ue read in f rom some externa l dev ice .

    2 .6 .T rans fer o f Cont ro l

    The d i scuss ion so fa r has been concerned w i th operat iona l o rders ra ther than cont ro l o rders . Cont ro l o rders may be summar ized as re la t ive and abso lu te Jumps, re la t ive and abso lu te subrout ine ca l l s , and subrout ine re turns , a l l o f wh ich may be cond i t iona l o r uncond i t iona l .

    Re la t ive Jumps fac i l i ta te the wr i t ing o f re - locat - ab le code , wh i le the ab i l i ty to nest subrout ines to e reasonab le depth i s a feature wh ich many programmers wou ld look fo r . These comments app ly as much to la rger mach ines as they do to mic ro - processors.


    The rap id ly fa l l ing cos t o f mic roprocessor ch ips and memory has meant that generat ing code i s the major s ing le cos t in a mic roprocessor -based sys - tem. Never the less , i t cou ld be argued that the fa l l in memory cos t has a s ide e f fec t wh ich cou ld he lp redress the ba lance . Th is i sp that less care need be taken over wr i t ing conc ise programs; there - fo re less programmer t ime i s needed, and there i s a l so the poss ib i l i ty o f us ing a compi le r to a l low h igh- leve l p rogramming.

    In many cases, the number of systems to be pro- duced would not be large enough to Justify the use of a compiler. In any case, work at machine level is almost always necessary when commission- ing the finished system, and so a little care over the choice of microprocessor can save a great deal of effort st production time.


    The main prob lem wi th compar ing microprocessor ins t ruct ion sets i s the lack o f s t andard isat ion in the way that manufacturers descr ibe the i r dev- i ces . Terms such as ' immediate address ing ' , ' i nd i rec t address ing ' and 'auto - increment /auto - decrement ' have d i f fe rent mean ings fo r d i f fe rent manufacturers . Three prev ious ly proposed schemes wh ich might be used to he lp in the compar i son o f ins t ruct ion sets a re d i scussed here .

    The f i r s t was put fo rward in 1970 by Be l l and Newel l [1 ] , and i s known as the Ins t ruct ion Set P rocessor ( I SP) language. I t p rov ides a s tan- dard notat ion fo r represent ing exp l i c i t l y the reg is ter layout , memory space , and mach ine code

    structure of any processor already in existence or l ikely to be designed in the foreseeable future. I SP is primari ly a hardware description language; it describes the processor's hardware first, and then defines the order code in terms of operations between hardware elements.

    The second is the 'mnemo-nics' system, proposed bY Nicoud [4,5] in 1975; it is less general than I SP , be ing ang led spec i f i c ia l l y towards mic ro - p rocessors . The 'mnemo-n ics ' sys tem expresses a g iven microprocessor ' s ins t ruct ion set in te rms o f a s tandard assembly language. For each o f the s tandard mnemonics , the permi t ted operands are l i s ted , together w i th the i r representat ion in mach ine code . The hardware s t ruc ture o f the pro - cessor can be deduced by inspect ion o f the permi t - ted operands . A use fu l by -product o f th i s method i s that i t l eads to the concept o f a un iversa l assembler , capab le o f assembl ing f rom 'mnemo-n ics ' source in to mach ine code fo r any microprocessor . Th is wou ld great ly fac i l i ta te the runn ing o f benchmarks to compare severa l mic roprocessors accurate ly .

    The th i rd scheme i s a graph ica l method put fo rward by J .N icho ls [3 ] in 1975. The ins t ruct ions o f the processor a re p lo t ted on a matr ix showing source operands a long one ax is and operat ion /dest inat ion operand combinat ions a long the o ther . The reso lu - t ion a long the axes i s such that ac tua l reg is ter names are g iven ; the appropr ia te assembler mnemonic i s shown in each square on the matr ix cor respond ing to a va l id operat ion .

    The N icho ls mat r ix p rov ides a compact summary o f an ins t ruct ion set fo r a programmer work ing w i th an assembler . However , s ince the layout o f the axes i s d i f fe rent fo r each processor , the method does not a l low easy compar i son o f a number o f ins t ruct ion sets .

    I SP , 'mnemo-n ics ' and theNicho ls mat r ix~ a l l p rov ide a la rge amount o f in fo rmat ion about the microprocessor ' s ins t ruct ion set . Th is i s the leve l o f deta i l wh ich would be requ i red by a des igner who has nar rowed the cho ice down to ,say , two or th ree processors . To use any one o f these methods to he lp a t the in i t ia l se lec t ion s tage wou ld be waste fu l o f t ime. What i s requ i red i s a sys tem which presents on ly the in fo rmat ion requ i r - ed a t that s tage , p re ferab ly in g raph ica l fo rm, and i s there fore qu ick to use .


    5 .1 . Operat iona l Order s

    An operat iona l o rder i s one wh ich i s not concerned w i th t rans fer o f p rogram cont ro l . Any operat iona l o rder l i ke ly to be encountered in mic roprocessors can be expressed in one o f the fo l low ing fo rms :

    i ) OP1 OP l .u

    i i ) OP l OP2.u

    i i i ) OP l OP l .b .OP2


    where .u, .b, are unary and binary operators, and 0 P i, O P 2 are operands.

    I t fo l lows that any o f these orders may be repre - sented by ent r ies on a 2 -d imens iona l g r id w i th operators a long one ax is (ver t i ca l , say) , and operands (OP lon ly o r OP 1 /0P 2) a long the o ther ax i s (hor i zonta l ) . Cer ta in a reas o f the gr id , cor respond ing to a combinat ion o f 'OP l on ly ' operand and binary operator, are logically imposs- ible, and may be denoted by a cross in the appro- priate square

    It must be remembered that, to ease the compari- son of different devices, the layout of the axes should be independent of the microprocessor being represented~

    5.2. 'Operators' Axis

    The 'operators' axis presents few problems; it is simple to choose a list of operators which covers all those likely to be encountered. Certain rat- ional izations have to be performed; for example) no dist inct ion is made between MOVE, LOAD, STORE, PUSH, or POP operators; 'rotate' orders are categorized as ROTATE or ROTATE VARIABLE LENGTH, ignoring dist inct ions such as 'With Carry' or 'Without Carry'~

    The divis ion of operators into 'binary' and 'unary ) classes is trivial except in the case of the MOVE and EXCHANGE operators These are a special type of unary operator for which statement (i) above is meaningless Therefore any square corresponding to a combination of MOVE or EXCHANGE operators and 'OP i only' operand is also invalid

    5.3 . _~erands ' Ax is

    Dec id ing on a layout fo r the 'operands ' ax i s i s ra ther more compl i ca ted . Operands tend not to be as s tandard ized as operators ; there i s cons ider - ab le var ia t ion in reg is te r numbers and w idths , memory address ing modes , and s tack fac i l i t i es . To ass i s t w i th the group ing , i t i s use fu l to look in more deta i l a t the operands invo lved , and a t how they are se lec ted by the ins t ruc t ion word . Tab le 1 shows the main c lasses o f operand .

    A l low ing a l l poss ib le combinat ions , the number o f 'OP 1 /OP 2 ' co lumns to be accommodated by the hor i zonta l ax i s wou ld be :

    7~ (OP l ~ OP2) 2~ 5~

    +6 (OP 1 = O, 2)

    ( immediate/ immediate is invalid, as writ ing to the current instruction is not encouraged)


    Note that combinations 1/2 (say) and 2/1 share one column. Some method is needed to indicate which ordering is meant. Spl itt ing each grid square into an upper and a lower section achieves this. An entry in the upper half would mean that O P I/O P 2 are as shown by the column heading; an entry in the lower half would mean that O P I /OP2 are reversed (see Fig.l).

    The number of 'O P 1 only' columns = 6; (immediate mode operands are invalid here). The total of thirty-three columns can be accommodated quite easily across the page.

    Ref Name

    immedia te

    reg is te r (on -ch ip )




    autoincrement and


    hardware stack











    G or f/G

    M or f/M

    G/M or M/M'or F/G/M or F/M/M' or G/M/M' or G/G'/M

    f + G/M or f + G/M/M' or G/M + f/M' or f + (f'/G)JM

    or f + (f'/G)/M/M' or f ' /G/M + f/M'

    G~/M or G~/M/M' or (f/G):/M or (f/G):/M/M'

    s t

    Key to descr ip t ion : f , fw

    G ,G '


    st +

    / @'/

    Tab le 1

    a re f ie lds in the ins t ruc t ion ;

    a re on-ch ip reg is te rs ;

    a re locat ions in the main memory;

    i s an i tem on a hardware s tack ;

    has i t s usua l mean ing ; means ' se lec ts ' ; ( less b ind ing than '+ ' )

    means ' se lec t , then increment (decrement ) ' when used as a source operand; 'decrement ( inc rement ) , then se lec t ' when used as a dest inat ion operand , i .e . a so f tware s tack

    : Operan d Addressin~ Mechanisms


    5o3.1o Possibility of Increasing Number o~Operand Types

    Even w i th operands grouped in to on ly seven cate - gor ies , the char t s t i l l g ives a reasonab le amount o f in fo rmat ion about the features d i scussed above , i .e . p resence o f hardware s tack , index ing , and auto - inc rement /auto -decremento However, no i n fo rmat ion i s g iven about the number o f genera l reg is te rs ava i lab le fo r use in d i rec t reg is te r mode, fo r se lec t ing memory in ind i rec t and auto modes , o r fo r index ing in indexed mode Refer r - ing back to the l i s t o f operand types , i t can be seen that cer ta in groups subd iv ide fu r ther qu i te natura l ly , accord ing to these c r i te r ia

    For example , in g roup 1 (Tab le 1 ) , ' f /G ' means that a f ie ld in the ins t ruc t ion word i s used to se lec t G, and so there must be more than one G ava i lab le fo r the order . 'G ' means that there i s no cho ice o f reg is te r ; i t i s imp l ied Groups 2, 3, 4, and 5 can be sp l i t s imi la r ly . The number o f operand types fo l low ing such a subd iv i s ion wou ld be 12, and so the to ta l number o f co lumns requ i red wou ld be :

    12~ +11 +i i = 88 2! 10!

    (The w idth o f an operat ion i s de f ined as the smal le r o f the w idths o f OP 1 and OP 2) . Sp l i t - t ing each square in to th ree sect ions f rom le f t to r ight a l lows th i s w id th in fo rmat ion to be shown on the gr id The cent re o f the th ree sect ions in the square cor responds to an operat ion w idth equa l to the processor w id th The le f t and r ight sec - t ions cor respond to operat ion w idths less than and greater than the processor w id th , respect ive ly ( see F ig . l ) .

    53.3 Arrangement of Columns

    The ar rangement o f co lumns across the page has not yet been d i scussed . Idea l ly , the pat tern o f f i l l ed - in squares shou ld have a use fu l mean ing , even be fore the co lumn head ings a re read . 'Number o f addresses per ins t ruc t ion ' i s a su i tab le para - meter by wh ich to group the co lumns , fo r the reasons out l ined ear l ie r .

    5 .4= Procedure fo r F i l l i ng - in the Char t

    There are two approaches to f i l l i ng - in the char t The f i r s t approach works pure ly f rom a textua l descr ip t ion o f the ins t ruc t ion set , and requ i res no in fo rmat ion about the layout o f f i e lds in the mach ine code .

    Certain columns could be omitted if they were found to be permanently empty. Even so, the num- ber of columns would be too large to fit easily onto a page.

    The method cur rent ly in use i s a compromise ; g roup 1 a lone has been sp l i t ( in to G imp l ied and Gf ) , and 'ST unary ' has been omi t ted , g iv ing a co lumn count o f 41 ,

    The second approach a ims to make the char t re f lec t the s t ruc ture o f the mach ine code .

    Cons ider the fo l low ing three ins t ruc t ions , where A, B, C a re on-ch ip reg is te rs :

    A A (m/c code 01010010)

    B + B (m/c code Iii01011)

    C C (m/c code 01111001)

    operation width

    ~ OP1 and OP2 as shown by column heading

    OP1 and OP2 reversed

    < ~ > processor width

    Separate ly , each order i s o f the O-address type (G G.u) , but under the f i r s t approach they would be merged to fo rm a compound order :

    11 B B C C wh ich i s o f the 1 -address type ( ( f /G) + ( f /G) .u ) .

    The second approach would not merge the two orders as no f ie ld can be ident i f ied in the mach ine code as cor respond ing to f , the group o f b i t s wh ich se lec ts reg is te r A, B o r Co

    E i~. l : Key to Ent r ies w i th in a Gr id Square .

    5.3.2 Indicating O~eration Width

    So fa r , operat ions o f d i f fe rent w id ths have been lumped together For example , an operat ion add- ing two 16-b i t reg is te rs , o r two 8 -b i t reg is te rs , o r add ing a Car ry b i t in to an 8 -b i t reg is te r , wou ld a l l be ind icated by the same square .

    I t i s fe l t that the f i r s t method i s p re ferab le as most users a re in teres ted in what range o f operat ions can be per fo rmed, regard less o f the layout o f the mach ine code requ i red Anyone con- cerned w i th deta i l s o f the mach ine code (assembler wr i te rs , fo r example) , wou ld be bet ter served by systems such as I S P or mnemo-nics.

    5.5 . Cont ro l Orders

    Cont ro l o rders requ i re a separate gr id , fo r which the requ i rements a re more s imp le . The orders


    cons is t o f jumps and subrout ine ca l l s , wh ich can be cond i t iona l o r uncond i t iona l , and re la t ive or abso lu te ; and subrout ine re turns , wh ich can be cond i t iona l o r uncond i t iona l .

    ( i ) operand def in i t ions

    ( i i ) o rder de f in i t ions

    The re turns are spec ia l cases in that they have no operand f ie ld , and need on ly be shown on the gr id as present , o r not . The o ther o rders may be represented as :

    P C ~ P C + operand ( re la t ive)

    P C ~ operand (abso lu te )

    In the re la t ive case , the operand f ie ld may rep- resent a pos i t ive or negat ive va lue . Note that subrout ine ca l l s imp ly that PC i s a l so saved on a s tack . The depth o f th i s shou ld be shown on the char t .

    The y ax is o f the gr id , then , represents the fo l low ing operators :

    { jump } f cond i t iona l t . { re la t ive}

    ca l l ~uncond i t iona l ~ abso lu te

    / cond i t iona l ~ re turn " [ uncond i t iona l ]

    The x ax is represents the operand types . The number of columns required is, of course, much less than for the other grid, as combinations of operand types need not he represented At least six columns are needed - one for each of the groups 0 to 5 above; some of these groups may be subdivided, as described earlier, in which case II columns would be required.

    In the case of control orders, the 'width' of the operation shows the amount of choice al lowed for jump destination It is therefore useful to split each column into three sections, from left to right, as for the other grid, to indicate width of operation.


    F i l l ing - in gr ids i s a ted ious task , and any auto - mat ion wh ich can be prov ided i s we lcome. A program has been wr i t ten in BASIC to run on a PDP-11 , to he lp in th i s respect . G iven a summary o f an ins t ruct ion set , i t p roduces the cor respond ing char t on a Tekt ron ix 4010-1 VDU. Hard cop ies can be made if required

    The translat ion of the manufacturer's information into a form readable by the program has to be performed manually In writ ing the program, the aim was to make this stage as simple as possible, and also to ensure that different people perform- ing the same translat ion would produce identical charts.

    F igure 2 shows the program input necessary to produce the INTEL 8008 'operat iona l o rders ' char t shown in F ig3 . The two main e lements a re :

    #NAME INTEL 8008 ~WIDTH 8 #0PERAND5 00008 N 10008 Q/G.A , B, C, D .E ,H ,L 10108 Q/G. B, C, D, E ,H ,L 30008 G.HL/M. 0 :64K- I 70008 G.A #MACROS MOO 100 300 000 t O O0 Ol 03 04 08 10 11 #0RDEhS 0 13100100 1 13100300 2 13300100 3 13100000 4 13300000 5 15101 6 16101 7 17700 8 FOV00M00


    F igo2o Typ ica l Input to BASIC Program.

    Each operand def in i t ion cons is ts o f a numer ica l operand ident i f ie r (conta in ing operand type and ser ia l number ) , a f ie ld showing the operand w idth and a symbol i c descr ip t ion o f the address ing s t ructure wh ich se lec ts the operand (cog . Q /GoA,B ,C) .The program ignores th i s las t f ie ld . For example , the l ine

    1 0 1 0 8 Q/GoB,C ,D,E ,H ,L

    wou ld be in terpreted as :

    operand type: 1 (wh ich means" f /G" ) ] oper and ser ia l number : 0 1 ~dent i f ie r

    w id th : 08 b i t s

    symbol i c representat ion : Q /G.B ,C ,D ,E ,H jL

    (here , 'Q ' means a f ie ld in the f i r s t byte o f an ins t ruct ion) .

    Each order de f in i t ion cons is ts o f a re ference number fo l lowed by a two- o r th ree- f ie ld code . The f ie lds in the code are :

    a 2 -d ig i t operator code;

    one or two 3 -d ig i t operand ident i f ie rs .

    For example , the l ine

    2 13300100






    SUB i 3 SUB I














    W O A D D R E S S

    ;M Mi MvIMa f M Mi ~ Ma P Mi v Ma F Mv ~ F Ma

    I I I I I I ! ! ! ! ! ! !1 I I I

    F!!!!rr!!l i, "' llltlllill I]li

    _rJl i lli II11

    : I::II:'NIo~I.M;I I,Gp IX IX IX I>CK1 " I "





    ~-IGPI ~M iMiI ,',1 ~l P IG'I .YM, I'.' IN, Io'oE~:' ISsTT I;', '1"1 I '1 I I I I I I I I I I k

    'l'l I'1 I,,~n"~ ,I.I I.I I l l I''~,,,~

    i i i iii I I I t I I I IN

    iil'i I ii i ltltl















    T W O A O O R E S Sl

    Gf M MI MY Ma I

    P G,f M .~M~ M~ P I . .~ "~M, E .~:~ ~ E . , I,~ p M~ I I I I l : : l ' l l l l ' | : l ' | l : "

    : i : | i : : i | : : .i : , : | i .. i u,

    :i:" -=I ,. . :: " :i ' | ':: | _-

    Illl III | ii | I I iii [] | | ii.I | I I | | | I I I| | I I


    Gf MIMi IMv Ma Gim ST Gim i ST Gin UN LI~ DNIUN JR F Gf ~H Mi MY Ma F GfmMINi MvIM . . . . I STIST I U~


    x x x x x l i D < x ~ Bx XXIX x X. . I I Ix Xx x x I I I:x

    x>< X>~X x X I>< ~YX x X b,< X~ X I>< ~ x X I B XXxx I I XXX x X

    X~XX x X I><

    X XxN IX XX]X K X I I IX

    mJ, lm M, mlm I I n I

    I I ~ I II

    ' ill im n i NI n i i n i i H I m u m n | i n m m I I I

    F IGo3. 'Operat iona l Orders ' Char ts fo r INTEL 8008 and DEC LS I -11 .


    would be in terpreted as :

    re fe rence number : 2

    operator code: 13 (wh ich means "MOVE")

    operand 1 ident i f ie r : 300

    operand 2 ident i f ie r : 100

    6 FHoSumner . The Appl icat ion of Paging, Seg- mentat ion and Virtual Memory, in: Infotech State of the Art Report 2, Giant Computers, (Infotech, U.Ko, 1971) 255-274.

    The most powerful property of the system is its abil ity to accept macros in any field within an order definitions The input data may contain definit ions of operator macros and operand macros This faci l ity is part icular ly valuable where the microprocessor being represented has a well struc- tured i ns t ruct ion set, ioeo, one which can be represented in a few lines of the form (operators) combined with (operands) combined with (operands)o The program expands the macros before producing the grid. The same pattern will be produced whether macros are used or not; they merely provide a means of saving time for the person doing the translation~

    Figure 3 shows 'operational orders' charts for the INTEL 8008 and the DEC LSI-IIo (To improve clarity for publication, they have been redrawn from the program output with the number of operators reduced)


    The graph ica l method out l ined in th i s paper a l lows a qu ick compar i son o f severa l mic roprocessors to be made a t a genera l leve l ; the BASIC program reduces the t ime needed to t rans fer in fo rmat ion f rom the manufacturer ' s handbook onto the char t .

    Future enhancements may include the addit ion of information on instruction t iming, input/output facilities, and the physical character i s t i cs of a device


    Io CoG.Bell et al A New Architecture for Mini- computers - The DEC PDP-II, AFIPS SJCC (1970)657-675o

    2. C.GoBell & A.Newello Computer Structures : Readings and Examples, (McGraw-Hill, New York, 1971).

    3. JNichols The Source-Destinat ion Matr ix for Instruction Set Presentation, Digest of Papers~ IEEE Compcon 75 Spring (1975) 61-63~

    4. J .DoNicoud Common Instruction Mnemonics for Microprocessors, Euromicro News le t te~ i, (1975) 3, 22-29

    5. J .DoNicoud A Common Microprocessor Assembly Language, in: MSami, J.Wilmink, R.Zaks (eds.), Second Symposium on Micro~rocessing and Microprogramming, (North Holland, Amsterdam, 1976), 213-22Oo


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