Comparison of microprocessors: a graphical approach

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<ul><li><p> Euromicro, 1977 North-Holland Publishing Co., Amsterdam </p><p>COMPARISON OF MICROPROCESSORS : A GRAPHICAL APPROACH </p><p>DoAspinall, MoHoBarton, E.L.Dagless </p><p>Dept . o f E lec t r i ca l &amp; E lec t ron ic Eng ineer ing , Un ivers i ty Co l lege , Swansea , Wa les , UoK. </p><p>ABSTRACT </p><p>Selecting a microprocessor for a particular application is a task frequently faced today. Manufacturers usually present hardware character- istics consistently, but vary considerably in the way they describe instruction sets, which makes microprocessor comparison tedious and time- consuming. The high cost of software production suggests that care should be taken to choose the correct instruction set for a particular applica- tion. </p><p>This paper discusses briefly how various features of the instruction set, such as general layout, size of processor state vector, range of address- ing modes, bit-handling capability, and range of control orders, affect the ease with which the device may be progrcx~med. </p><p>Current aids to facilitate the comparison of instruction sets are discussed, and the case is made for a less detailed, graphical method to help in the initial stages of microprocessor selec- tion. </p><p>The problems involved in presenting a graphical description of the instruction set are outlined, and solutions are proposed. </p><p>Finally, a BASIC program is described which, given a sur~ary of a device's instruction set in a concise form, produces a graphical representa- tion of it. </p><p>io INTRODUCTION </p><p>Th is paper i s the resu l t o f work wh ich has been car r ied out to p roduce a graph ica l method o f ins t ruc t ion set representat ion as an a id to mic ro - p rocessor comparison. </p><p>Severa l i te ra t ions were requ i red to choose the present char t fo rmat , and some o f the arguments fo r and aga ins t d i f fe rent layouts a re out l ined be low. </p><p>The char ts p roduced have been used in severa l mic roprocessor workshops , to p resent an overv iew of the instruction sets of various devices, with- out resorting to manufacturers' descriptions, and have been well received. </p><p>Work has also been undertaken to speed up the production of charts by employing a BASIC program A brief descript ion of this is given at the end of the paper . </p><p>2. THE IMPORTANCE OF THE INSTRucTIoN SET </p><p>I t may be s ta t ing the obv ious to say that any program act ion wh ich the mic roprocessor per fo rms must be wr i t ten in te rms o f the ins t ruc t ion set ; but th i s shows jus t how impor tant that d imens ion i s . Knowledge o f the ins t ruc t ion set imp l ies knowledge o f p rocessor w id th , reg is te r layout , and memory address ing capab i l i ty , as we l l as the range and t iming o f funct ions wh ich can be per - fo rmed. There are cer ta in features o f an ins t ruc - t ion set wh ich prov ide a use fu l ind icat ion o f i t s su i tab i l i ty fo r a par t i cu la r purpose , and wh ich are wor thy o f fu r ther d i scuss ion . </p><p>F ive years ago , i t wou ld have seemed unusua l fo r a log ic des igner to be asked to choose a compute~ yet today such a task i s qu i te commonplace . The mic roprocessor ch ip has made the processor jus t another item in the designer's armoury of compo- nents. Unfortunately, the IO00-fold drop in the price of processors has not been matched by a similar reduction in their complexity </p><p>The microprocessor chosen for a part icular appl ication must have the correct hardware characteristics, just as for any other electronic component. Microprocessor manufacturers usual ly list these characterist ics - e.go, power supplies, clock inputs required - in a reasonably standard form. </p><p>However , what makes mic roprocessors more complex than o ther components i s the i r added d imens ion - ins t ruc t ion set , the presentat ion o f wh ich i s not s tandard ised . S ince the product ion o f the so f tware const i tu tes a ma jor cos t o f deve lop ing a microprocessor -based sys tem, bet ter s tandard - i sa t ion cou ld be advantageous . </p><p>84 </p><p>2 .1 Genera l Layout </p><p>A we l l l a id out ins t ruc t ion set , i . e . one wh ich does not p lace apparent ly a rb i t ra ry res t r i c t ions on the funct ion /operand 1 /operand 2 combinat ions wh ich are ava i lab le , reduces the t ime necessary to become fami l ia r w i th the processor . </p><p>2 .2 P rocessor Width </p><p>The w idth o f the processor determines the accuracy to wh ich ar i thmet ic can be per fo rmed. Doub le length work ing may be requ i red , and "Add w i th Car ry" o r "Subt rac t w i th Bor roW' ins t ruc t ions wou ld fac i l i ta te th i s . </p><p>Where non-ar i thmet ic p rocess ing i s be ing car r ied out , p rocessor w id th may be cons idered as the number o f I /O s igna ls wh ich can be processed in para l le l . </p><p>2 .3 P rocessor S ta te (Vector ) </p><p>P rocessor s ta te [2 ] i s the in fo rmat ion he ld in </p></li><li><p>COMPARISON OF MICROPROCESSORS : A GRAPHICAL APPROACH ~5 </p><p>the processor between ins t ruc t ions . The s i ze o f the processor s ta te depends on the number o f on - ch ip reg is te rs ava i lab le , inc lud ing genera l reg i - s te rs , p rogram counter , index reg is te rs , s tack po in ters (o r hardware s tack) and s ta tus reg is te rs . </p><p>A programmer work ing a t mach ine leve l can use a se t o f on -ch ip reg is te rs as i f they were the s im- p le var iab les o f a h igh- leve l language, p rov ided there a re su f f i c ient fo r each one to be ass igned a mean ing fo r the durat ion o f the a lgor i thm. I f access to these reg is te rs i s much fas ter than to ma in memory, a cons iderab le inc rease in execut ion speed may be ach ieved . However , when the proces~ or s ta te i s la rge , there a re more reg is te rs to be saved when dea l ing w i th a context change. </p><p>I t may be noted that compi le rs a re un l i ke ly to take advantage o f fas t on -ch ip reg is te rs because o f the inconven ience o f dea l ing w i th the i r l im i ted address space ( typ ica l ly ~8) [6 ] </p><p>2 .4 . Range o f Address ing Modes </p><p>Every operand wh ich i s invo lved in an operat ion per fo rmed by a mic roprocessor res ides on the ch ip , in ma in memory, o f in an input /output por t . Neg- lec t ing speed requ i rements , a p rocessor o f fe r ing s imp ly d i rec t address ing o f a l l these locat ions wou ld be ab le to execute the same a lgor i thms as one w i th a more soph is t i ca ted ins t ruc t ion set . However , improvements to the bas ic ins t ruc t ion set a re o f ten made, and take two main fo rms : </p><p>( i ) S ing le o rders a re prov ided to g ive access to data s t ruc tures , such as s tacks and tab les , where normal ly severa l o rders would be requ i red . </p><p>( i i ) Shor t o rders , w i th one or more operands imp- l i ed , a re in t roduced to save space , as i t i s not a lways necessary to spec i fy exp l i c i ty the address o f a l l the operands . For such orders , the 'number o f addresses per ins t r - uc t ion ' i s sa id to be reduced . </p><p>These improvements amount to the prov is ion o f add i t iona l address ing modes impl ied, ind i rect , indexed, and auto increment /autodecrement - and can great ly s impl i fy the programming of cer ta in types of rout ine. These modes are cons idered in more detai l below. </p><p>2.4 .1 .Implied Addressing </p><p>To per fo rm an operat ion such as A + B + C, where A, B and C res ide in ma in memory, a th ree-address o rder wou ld seem su i tab le . Such orders a re not usua l on mic roprocessors because o f the ch ip com- p lex i ty wh ich would be invo lved ; in any case , severa l s to re accesses wou ld be requ i red to read an order conta in ing so many address b i t s . There - ~ore , ins t ruc t ions w i th some operands imp l ied are o f ten found. In fac t , cer ta in a lgor i thms are neat ly imp lemented us ing th i s type o f ins t ruc t ion , when the s tack i s an imp l ied operand . For example , cons ider eva luat ing </p><p>A * B - C * D (a l l operands in ma in memory) </p><p>In reverse Po l i sh : </p><p>AB*CD*- </p><p>In code : </p><p>PUSH </p><p>MUL </p><p>PUSH </p><p>MUL </p><p>RSUB </p><p>A (I address: stack + A) </p><p>B (i address: stack + stack * B) </p><p>C (i address: stack + C) </p><p>D (I address: stack + stack * D) </p><p>(O address : s tack s tack -s tack) </p><p>The resu l t i s le f t on the top o f the s tack . </p><p> Addressing </p><p>I n ind i rec t address ing , the address o f the oper - and i s he ld in a reg is te r o r a memory locat ion , not in the ins t ruc t ion i t se l f . A l te r ing the address a l lows the same p iece o f code to access d i f fe rent ma in memory locat ions . </p><p>2.4 .3 .Indexed Addressing </p><p>This is an extens ion of ind i rect address ing. In this case, the operand address is formed by add- ing a va lue ( typ ica l ly 8 bits) f rom the instruc- t ion to the contents of an index reg is ter (typi- ca l ly 16 bits). As an example of an appl icat ion, cons ider a rout ine to access cor respond ing ent r - i es in severa l tab les ; assume that the index reg is te r i s used as a po in ter to s tep down the f i r s t tab le . An ent ry in that tab le may be accessed , us ing ind i rec t address ing v ia the index reg is te r . The cor respond ing ent r ies in the o ther tab les may be accessed , us ing indexed address ing , where the va lue in the ins t ruc t ion determines wh ich tab le i s used . </p><p>2 .4 .4 . Autoincrement/Autodecrement Addressing </p><p>Usua l ly , the on ly hardware - imp lemented s tack to be found in a mic roprocessor i s the one used in terna l ly to save subrout ine re turn addresses . P rogrammers o f ten requ i re to use a s tack fo r o ther purposes , such as sav ing add i t iona l va lues when nest ing subrout ines , o r eva luat ing express - ions ( see Sect ion 2 .4 .1 ) . P rogrammer-access ib le hardware s tacks a re ra re , and se ldom deeper than 16 leve ls . So f tware - imp lemented s tacks a re there - fo re o f ten employed . An area o f ma in memory i s used to ho ld the s tack ent r ies , and a reg is te r ( s tack po in ter ) i s used to po in t to the top -o f - s tack ent ry . To PUSH an i tem onto the s tack , the s tack po in ter i s decremented (o r inc remented) , and the i tem wr i t ten to the locat ion wh ich i t now addresses . To POP an i tem o f f the s tack , read- ing i s per fo rmed before the s tack po in ter i s inc remented (o r decremented) . The s tack i tems are sa id to be accessed us ing auto inorement /auto - decrement address ing . In th i s paper , that te rm i s reserved fo r the predecrement /post increment and pre increment /postdecrement combinat ions which are requ i red fo r t rue s tack operat ions . </p><p>Severa l var ia t ions a re poss ib le : the s tack may increase or decrease in memory address f rom top </p></li><li><p>86 D. ASPINALL, M.H. BARTON, E.L. DAGLESS </p><p>to bot tom, and the po in ter may po in t to the top i tem or to the next empty space . </p><p>2 .5 .B i t Hand l ing </p><p>H i t man ipu la t ion i s inva luab le in the rea l - t ime app l i ca t ions fo r wh ich mic roprocessors a re most o f ten used . Sh i f t ins t ruc t ions a re use fu l here , espec ia l l y the ra re ly found var iab le - length sh i f t s wh ich a l low easy access to any b i t in , say , a va l - ue read in f rom some externa l dev ice . </p><p>2 .6 .T rans fer o f Cont ro l </p><p>The d i scuss ion so fa r has been concerned w i th operat iona l o rders ra ther than cont ro l o rders . Cont ro l o rders may be summar ized as re la t ive and abso lu te Jumps, re la t ive and abso lu te subrout ine ca l l s , and subrout ine re turns , a l l o f wh ich may be cond i t iona l o r uncond i t iona l . </p><p>Re la t ive Jumps fac i l i ta te the wr i t ing o f re - locat - ab le code , wh i le the ab i l i ty to nest subrout ines to e reasonab le depth i s a feature wh ich many programmers wou ld look fo r . These comments app ly as much to la rger mach ines as they do to mic ro - processors. </p><p>3. ECONOMIC CONSIDERATIONS </p><p>The rap id ly fa l l ing cos t o f mic roprocessor ch ips and memory has meant that generat ing code i s the major s ing le cos t in a mic roprocessor -based sys - tem. Never the less , i t cou ld be argued that the fa l l in memory cos t has a s ide e f fec t wh ich cou ld he lp redress the ba lance . Th is i sp that less care need be taken over wr i t ing conc ise programs; there - fo re less programmer t ime i s needed, and there i s a l so the poss ib i l i ty o f us ing a compi le r to a l low h igh- leve l p rogramming. </p><p>In many cases, the number of systems to be pro- duced would not be large enough to Justify the use of a compiler. In any case, work at machine level is almost always necessary when commission- ing the finished system, and so a little care over the choice of microprocessor can save a great deal of effort st production time. </p><p>4. SCHEMES TO AID THE COMPARISON OF INSTRUCTION SETS </p><p>The main prob lem wi th compar ing microprocessor ins t ruct ion sets i s the lack o f s t andard isat ion in the way that manufacturers descr ibe the i r dev- i ces . Terms such as ' immediate address ing ' , ' i nd i rec t address ing ' and 'auto - increment /auto - decrement ' have d i f fe rent mean ings fo r d i f fe rent manufacturers . Three prev ious ly proposed schemes wh ich might be used to he lp in the compar i son o f ins t ruct ion sets a re d i scussed here . </p><p>The f i r s t was put fo rward in 1970 by Be l l and Newel l [1 ] , and i s known as the Ins t ruct ion Set P rocessor ( I SP) language. I t p rov ides a s tan- dard notat ion fo r represent ing exp l i c i t l y the reg is ter layout , memory space , and mach ine code </p><p>structure of any processor already in existence or l ikely to be designed in the foreseeable future. I SP is primari ly a hardware description language; it describes the processor's hardware first, and then defines the order code in terms of operations between hardware elements. </p><p>The second is the 'mnemo-nics' system, proposed bY Nicoud [4,5] in...</p></li></ul>