compact modeling ibm

IISc Bangalore, February 2008

© 2006 IBM Corporation

Compact Modeling

Josef WattsIBM Semiconductor Research and Development CenterJanuary 2008

IISc -- February 20082

IBM Semiconductor Research and Development Center – Joe Watts

What is a Compact Model?



Compact MOSFET Model

Jds = f1(Vds,Vgs)

Cgs=f3(Vgd, Vgs)Cgd=f2(Vgd, Vgs)

Gate

Drain Source

CompactModel

TCADModel



PowerPC microprocessor

2 cores

10 levels of wiring

7.9E8 transistors

65nm SOI MOSFET Transistorsstress liner, halos, gate tunneling,

floating body effects, self heating.



Compact Model

Design proceeds simultaneously at multiple levels of abstraction

Information passes from level to level via models

Logic Model

Timing Model



LayoutData

Circuit Simulator(PowerSPICE

HSPICESpectre)

Compact Model

Circuit Characteristics

(delay, gain, etc)

LayoutExtractor

Net list

Schematic DataNetlister

Design Information

Process Information Circuit Behavior



What does the simulator do? (DC Case)

Enforce Kirkoff's Laws– V1=V(R1)+V(R2)

– V(R2)=V(R3)

– I(V1) = I(R1)

– I(R1) = I(R2) + I(R3) V1

R1

R3R2



What does the simulator do? (DC case)Enforce Kirkoff's Laws– V1=V(R1)+V(R2)

– V(R2)=V(R3)

– I(V1) = I(R1)

– I(R1) = I(R2) + I(R3)

– Assign a voltage to every node—by construction voltage law is satisfied

– If I know I(X) as a function of V(X) I can test current law.

– That’s what the compact model supplies: I=f(V)

V1

R1

R3R2

V1

V3=0

V1

V2



What does the simulator do? (DC case)Enforce Kirkoff's Current Law– 0=fR1(V1-V2)-fR2(V2-V3)-fR3(V1-V2)

– Calculate current at each node

– This is the error vector E– If any element is not zero the

simulator must adjust the voltages to make all the errors sufficiently small.

V1

R1

R3R2

V1

V3=0

V1

V2



What does the simulator do? (DC case)

Adjust voltages to zero the errors

– Now I need derivatives of I w.r.t. V

– The Compact model supplies those also

]2[2

)3(2

)2(2

)1(]2[ VdV

RdIdV

RdIdV

RdIE Δ•⎟⎠⎞

⎜⎝⎛ −−=

V1R1

R3R2

V1

V3=0

V1

V2[ ]VJErr

=



What does the simulator do? (AC Case)

Same thing plus– Account for charge storage

in capacitors when the voltage is not constant

– Also account for emf in inductors when the current is not constant

– Compact model must supply L & C values.

V1

R1

C3R2



Charge Conservation

Consider the gate to source capacitance of a MOSFET.

C=C(Vgs, Vgd, Vbs)

Integrate around a loop and net delta Q equals zero

But ΔVgs=0 on segment 2 and C on segements 1 & 3 are not equal.

Charge accumulates on the gate

gs

V

Vsbdsgs dVVVVCQ ∫=

2

1

),,(

Cgs

Vg

Vb=-1Vb=0

1

3

2

The compact model must provide both Q and C



Kirkoff’s current law becomes

CdtdQ

tQtQdtI ii

=

−+⋅= ∑∑ − )()((0 1

To form Jacobian you need

Compact model must calculate:

I(V), dI(V)/dV, Q(V), dQ(V)/dV



Compact model complexity

I = V/R is a compact model for a resistor





I = V/(θ*(L-dL)/(W-dW))Add Geometric Scaling





I = V/((θo+TCR*(T-25))*(L-dL)/(W-dW))Add: Geometric Scaling

Temperature Scaling





I = V/((θo+TCR*(VTR+T-25))*(L-dL)/(W-dW)Jth = V*I Rth=Rth/(L*W)Add: Geometric Scaling

Temperature ScalingSelf Heating

RthJthTR



Compact Model Anatomy

BSIMSOI3.2

NFET

PFET

AVNFET

BR resistor

decouplingcapacitor

Annular Diode

OP resistorOP resistorWire_cap

Process Model

TechnologyModel

FET modelequations

Process or Statistical

model

FET modelparameters

Passive component models



Communication Example

Goal: A digital speed boost for .25u CMOS– Same ground rules

– Shorten Lpoly by lithography/etch change

– Shorter Leff• Smaller gate capacitance• Higher current

– Heavy Halo to control Vt roll-off• Same Vt means same Ioff



Scaling of the FET

Ldrawn is determine by lithography—what can you resolve on the mask

Lpoly is determined by Ldrawn + develop + etch

Leff is determine Lpoly + hot processes

Cg_total ~ Lpoly

Id ~ Leff

Gate

DrainDrainSource

P-N+

Mask

Ldrawn

Lpoly

Leff



Short Channel Vt

Long device VT determine by 1D electrostatics

Short Channel VT is determined by 2D electrostatics

GateDrainDrainSource

P-N+

Gate

DrainDrainSource

P-N+



Vt vs Leff

Lmin Leff

Thre

shol

d V

olta

ge

Vtmin



Add Halo ImplantsLong device has Vt mostly determined by Substrate doping

Halo blocks field lines from drain to source end of channel

Short device has Vt mostly determined by halo doping Gate

DrainDrainSource

P-P+N+

Gate

DrainDrainSource

P-P+N+



Vt vs Leff

Thre

shol

d V

olta

ge Halo

No Halo

Lmin Leff



The plan

Lpoly 8% less– Cg_total 8% less

Leff 12% less (at Lmin)– Id 8% more

Build same design as original process

Microprocessor frequency 16% more



Simulation results: Latches don’t work

Latch used NFET passgates

Output does not reach Vdd

At Vdd-Vt device shuts off

Next gate must switch completely with a “weak one” on input

Vsource

Data In

Clock=Vdd

Data Out



Vt vs Leff

Thre

shol

d V

olta

ge Halo

No Halo

Lmin Leff

Lmin + 2 grid points



Simulation results: Latches don’t work

Latch used NFET passgates

Pass transistors were longer than minimum

New NFET had more Vt rollup

New NFET had more body effect

Vsource

Idra

in

6s+, Lmin6s0, Lmin6s+, Llatch6s0, Llatch

Data=Vdd

Clock=Vdd



Model Build Flow

MeasureData

Fit ModelTo Data

TestData

TestFit Quality

GoodWafer

Hardware ModelStarts Here

CenterModel

Fit ProcessModel

Package for Simulator

Test ModelQuality

TestDistributions

Test in Simulator

DesignManual

DeviceTargets

TestTargets

Ship Model

Target ModelStarts Here

InstanceEffects

Test Inst.Effects



Hardware Models, Target Models and Everything In Between

←Hardware Model

←Target Model

←Hardware

Influenced Model

Golden chip: near nominal for all device specs

Hardware meets key device specs

Hardware usable for roll offOutput impedance, etc.

Hardware is very far from targets

No hardware exist



Hardware Measurements

Id for various– Vg– Vd– Vbody

Impact IonizationIgate currentSTI stress effectLiner StressNwell proximityCjCov

For SOI also need– Buried BJT– Diode– Body Resistance– Self Heating

For RF model– S parameters



Model Build Flow

MeasureData

Fit ModelTo Data

TestData

TestFit Quality

GoodWafer


CenterModel

Fit ProcessModel


Test ModelQuality

TestDistributions

Test in Simulator

DesignManual

DeviceTargets

TestTargets

Ship Model


InstanceEffects

Test Inst.Effects



Hardware Fitting

FET– We use standard models: can’t change the equations

– Certain parameters must have physical meanings

– One set of parameters must fit all sizes

– Find values of parameters that gives the best fit.

nonFET there are no standard models– You can change the equations

– You can change the model topology



Fitting by Local Optimization

Id

Vg

L=10

L=.12

Vd

Different parameters describe the physics of different regionsAdjust small groups of parameters to fit different regions

1st

4th

3rd

2nd




Vg

Id

L=10

L=.12

Vd




Vg

Id

L=10

L=.12

Vd

As each group of parameter is adjusted that set of data is well fitAnd each previously fit group gets a little worseThe result is multiple iterations to get an adquate fit



Global Optimization

Use a very Robust Optimizer to fit all the data in one pass

Requires a good fitness function to weight all the data properly

We use a genetic algorithm developed in house.



Genetic Algorithm

Mimics biological evolution

Operates on a “population” of solutions

Find the fitter individual solutions and breed the next generation

Repeat until you have a good enough solution



Genetic Algorithm: The life cycle

Patriarch

Create Population by Mutation

Assign Fitness to Each

IndividualBreed New Population

Test for Diversity

Hill Climbalgorithm



Fitness Function

Matching to currents Physical reasonablenessMathematical robustnessMatching to derivatives



Model Build Flow

MeasureData

Fit ModelTo Data

TestData

TestFit Quality

GoodWafer


CenterModel

Fit ProcessModel


Test ModelQuality

TestDistributions

Test in Simulator

DesignManual

DeviceTargets

TestTargets

Ship Model


InstanceEffects

Test Inst.Effects



Systematic, Random & Correlated

Systematic…P=P+ΔP(layout)– Using the layout, we can predict the magnitude and direction of the

effect and– The prediction is good for any lot though out the life of the programRandom Correlated…P=P+ΔP(layout)*global random #– Not systematic but– Using the layout, we can identify classes of devices which will have

the same magnitude and direction of effect.Random Uncorrelated…P=P+ΔP(layout)*local random #– Using the layout, we cannot know the magnitude and direction of the

effect and – We cannot predict how predict that the effect will be the same as any

other device on the chip.The classification depends not on the physics but how much knowledge is available to the designer !



Nwell Proximity Effect

STI stress Effect

Random Dopant Fluctuation

Liner Stress

Corner Rounding

Litho & Etch Effects

RX

NW

CA

PC

Are these two FETs Identical?



Nwell Proximity EffectSystematic

STI stress Effect


Liner Stress

Corner Rounding


RX

NW

CA

PC



Well Proximity Effect

Figure courtesy of P. Drennan, CICC 06




STI stress EffectSystematic


Liner Stress

Corner Rounding


NW

RX

CA

PC

SA

SASB

SB



GATE

Source Drain

Silicon

STI Stress

OxideOxide DrainSource

During processing STI is etched out and filled with oxide at a high temperature. After cooling mechanical stress is locked in.





Random Dopant FluctuationUncorrelated

Liner Stress

Corner Rounding


RX

NW

CA

PC

Major memory effect because of small device size




1/sqrt(W*Leff)[1/u]

Dopant atoms are randomly place

For small FETs there are few total atoms

Random variations are a larger fractional change

Vt M

ism

atch






Engineered StressSystematic

Corner Rounding


RX

NW

CA

PC

SA

SASB

SB

1 CA 2 CA

Adjacent PC



Layout-dependent Stress ModelDense Gate Array

Small Isolate FET

Product Like

MC or CA strapping

PFET BOne PC pair 0.315um pitch

PFET C19 PC pairs 0.315um pitch

PFET AIsolated PC

RX length

Parallel BP Edge

This dimension being varied on the x-axis of the plot

compression

tension

tension

Longitudinal DSL

MC or CA proximity

Parallel edge far away

d

d

compression

tension

tension

Transverse DSLPC proximity

Reference pfet layouts






Liner StressSystematic

Corner RoundingSystematic andCorrelated


RX

NW

CA

PC



Rounding (webbing) of corners makes part of the channel longerDelta W is used to modify the device behavior– Nominal and tolerance of

delta W can be effectedThis is a systematic effect—L always gets longerThis is a random correlated effect—size of the effect depends on poly to isolation alignment

Corner Rounding Model

RX

PC

width

RX

PC

width

Nominal alignment, small

effect

Misalignment can make effect bigger

or smaller






Liner StressSystematic

Corner RoundingUncorrelated

Litho & Etch EffectsCorrelated and Uncorrelated

RX

NW

CA

PC

Same Orientation

PCPitch

Close Proximity



Model Build Flow

MeasureData

Fit ModelTo Data

TestData

TestFit Quality

GoodWafer


CenterModel

Fit ProcessModel


Test ModelQuality

TestDistributions

Test in Simulator

DesignManual

DeviceTargets

TestTargets

Ship Model


InstanceEffects

Test Inst.Effects



Model Centering

My Chip

DM Targets

As Fit Model

CenteredModel



Model Build Flow

MeasureData

Fit ModelTo Data

TestData

TestFit Quality

GoodWafer


CenterModel

Fit ProcessModel


Test ModelQuality

TestDistributions

Test in Simulator

DesignManual

DeviceTargets

TestTargets

Ship Model


InstanceEffects

Test Inst.Effects



Bibliography

"Modeling of Variation in Submicron CMOS ULSI Technologies", S. Springer, et al IEEE Trans. On ED. Sept. 2006

“A simple yet accurate mismatch model for circuit simulation”, Z. Jin, et al. Nanotech 2006

“Modeling FET Variation Within a Chip as a Function of Circuit Design and Layout Choices”, Josef Watts,et al, Nanotech 2005

“Modeling MOSFET Process Variation using PSP”, J. Watts, et al, Nanotech 2007

“A comprehensive MOSFET mismatch model”, P. Drennan and C. McAndrew, IEDM 1999, p. 167-170

“On the correlations between process parameters in statistical modeling”, Slezak, et al, Nanotech 2004, Vol 2, pp144-146

“Statistical timing of parametric yield prediction of digital integrated circuits”, Jess, et al, DAC 2003, p932-937

Advanced Compact Models for MOSFETs, J. Watts, et al, Nanotech 2005

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