coen 451 week 11 (a. review of pass logic)users.encs.concordia.ca/~asim/coen...
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Page 1 of 21 Lecture#12 Overview
COEN 451 Week_11
(A. review of pass logic) Pass Gate Logic The pass gate logic uses the pass gate or transmission gate to build a logic circuit.
Reviewing these two devices:
nMOS pass gate
NMOS passes good logic ‘0’
CMOS
TRANSMISSION GATE (TG)
PMOS passes good logic ‘1’
Together they cover the range of input from “0” to “1”.
The logic is built around series and parallel pass gates followed by an inverter.
Examples
AND, NAND
C=1 OUT=A
C=0 OUT=NO OUTPUT (OPEN CIRCUIT)
A B F
0 0 0
0 1 0
1 0 0
1 1 1
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OR, NOR
A multiplexer
XOR
The ideal number of series pass gates is 4. More than this the delay will be impractical.
This is as a result of added series resistance and capacitance, rendering the circuit useless
for long chains. There is also charge distribution problems associated to such circuits.
Delay calculation
Consider the following circuit,
This is equivalent to:
A B F
0 0 0
0 1 1
1 0 1
1 1 1
C A B F C A B F
0 0 0 0 1 0 0 0
0 0 1 1 1 0 1 0
0 1 0 0 1 1 0 1
0 1 1 1 1 1 1 1
A B F
0 0 0
0 1 1
1 0 1
1 1 0
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where each transmission gate is represented by its lumped
equivalent RC delay.
For such a circuit, the NMOS and PMOS transistors are
modeled as resistances in parallel.
The resistance is obtained from the linear Id formula for NMOS and PMOS,
If,
eq
eq
nptnDDeq
tptn
tpDDptnDDn
eq
eq
GR
BBVVG
VV
VVBVVR
G
1
))((
),()(1
The capacitance is obtained by assuming both transistors’ drain capacitances to be in
parallel,
)(2 dpdneq CCC
2
)1(**
nnCRDelay eqeq
Where n is the number of sections/pass gates/transmission gates.
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Long chain of transmission gates is not desirable and is usually broken to small sections
with an inverter placed in between. If we have n transmission gates and m transmission
gates per sections, then the delay is:
buffereqeqeqm
nmnRC )1(]
2
)1([69.0
And the optimum value of m is: eqeq
bufferp
optRC
tm
7.1
Usually m cannot be too long, for CMOSIS4 (0.5um), it is about 3 to 4 transmission gate
per section.
The transmission gate can be of minimum sized transistors without affecting the
delay greatly. This also improves power, however it will affect the signal quality.
Four to one multiplexer using pass gates
The weak pull up at the end of the MUX is to supplement the current input to the inverter.
It is a weak pMOS with the smallest dimension or longer length. (Note that the
arrangement now is ratioed logic and the sizes of the transistors have to be calculated
for correct gate operation).
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Increasing Drive capability in steps
The current drive capability of an inverter can be made to increase by adding parallel
transistors in the pull-up or down section of an inverter instead of making the width
bigger. This technique enhances the modularity of the design.
Page 6 of 21 Lecture#12 Overview
Tri-state buffer
The following circuit describes the principle of a tri-state buffer (inverter). When EN is
“LOW” the circuit works as an inverter and when EN is “HIGH” the output is floating.
XOR-NOR based on transmission gates
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XNOR with driving output
XOR with driving output
Programmable Logic Array (PLA) design
Any combinational circuit can be described by a Sum of Products (SOP). Thus their
implementation is a two level structure of “AND” followed by an “OR”. Many
combinational circuits are designed in regular structures as PLAs
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Example
Implement the following functions using the PLA method
cbabcy
acy
baabcy
3
2
1
Conventional CMOS will be difficult to implement this function in terms of regularity.
We will use pseudo-NMOS to implement the above functions due to its simplicity of
construction. The actual design is simpler if it is done in an inverted form. So change the
design from AND-OR to a NOT-NOR-NOR-NOT design.
Consider y1,
)()(
)()(
1
1
1
1
1
bacbay
bacbay
baabcy
baabcy
baabcy
Inverted output
Inverted input NOR
NOR
The implementation is as follows:
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The transistor level implementation:
The CMOS layout implementation:
Page 10 of 21 Lecture#12 Overview
Latches, Flip Flops and Timing
Clocked sequential circuits using transmission gates
Single clock are not suitable for finite state machine applications.
Problem: Dependence of operation on the propagation delay of the combinational circuit
and the feedback path.
For correct operation, TW cl
That is, use a narrow clock pulse, to block the feedback path from changing the state
again (Impractical),. ie, select clW so that the signal does not go through the pass gate
(for the faster combinational block in the pipeline!).
Select Tcl so that the CL has enough time to settle time within one clock period
otherwise, the next clock comes and clocks un-settled values; putting these together,
TW cl
The first problem is remedied by using a two-clock system or use single clock and its
inverted version. The second problem is treated by making cl small either by parallelism
or pipelining or with somehow faster circuits (Carry look-ahead instead of ripple adder
for example).
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Let us have another look at the clock.
One single clock to synchronize operations
Suitable for simple applications
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Complementary single phase clocking
Race condition in single phase clocking can be avoided by using complementary single
phase clocking scheme.
Condition to achieve proper operation:
Tcl
Problem: Clock Skew
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Two-phase Non-Overlapping clocking
To eliminate race problem
The difference between the D-Latch and flip flop can be shown in the set of diagrams
below:
Page 14 of 21 Lecture#12 Overview
Page 15 of 21 Lecture#12 Overview
Determining the set up hold time for the Master Slave Flip-Flop
Data arrives at D, and passes through G4,G5,G6. because CP= “0”
Data waits at input of Gate G3 until the CP = ”1” when data travels to the slave.
We have to hold the data stable for a period when the clock is changing (worst case).
The widths of the clock have to be sufficient to allow the latching of the data in each
section of the Master-Slave arrangement thus:
Setup time=G4+G5+G6
Hold time=G1+G2
W1=G5+G6+G3
W2=G9+G10+G7
Cycle time=W1+W2
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Edge Triggered FlipFlop
Page 17 of 21 Lecture#12 Overview
CMOS latch circuits
a)Dynamic
b) Static latch with cross-coupled circuit
c) Static latch with clocked feedback
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d) Buffered static latch with clocked feedback
CMOS two phase double latch circuits
a)Dynamic
.
b) Static unbeffered
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c) Static buffered
.
D Flip-Flop with direct set and clear
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Data is accepted when C is low and transferred to the output on the positive-going
edge of the clock. The asynchronous clear direct and set direct are independent and
override the clock.
Input Output
SD CD D C O O’
H L X X H L
L H X X L H
H H X X H H
On+1 O’n+1
L L L
L H
L L H
H L
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JK Flip-Flop
Input Output
SD CD C J K O O’
H L X X X H L
L H X X X L H
H H X X X H H
On+1 O’n+1
L L
L L No Change
L L H L H L
L L L H L H
L L H H O’n On
.