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King Fahd University of Petroleum and MineralsKing Fahd University of Petroleum and Minerals

Computer Engineering Department


College of ComputerScience And Engineering


Multiplication & DivisionMultiplication & Division 1

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Lectures 5:

Multiplication & Division

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Multiplication Algorithm

Scho

ol A

ge

Alg

orithm

852x 456

6 x 852 x 100

5 x 852 x 101

4 x 852 x 102+

• Multiply the product by the order of the digit (x 10i)

Single Digit Multiplication

Multiplication by a power of the base (10i) is a Shift Left by i positions

Multiple Additions

Algorithm:

• Compute Partial Products• Multiply Multiplicand by EACH

DIGIT of Multiplier

• Add Partial Products

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Multiplication in Binary11010110

x 10011

1 x 11010110 x 20

1 x 11010110 x 21

0 x 11010110 x 22

0 x 11010110 x 23

1 x 11010110 x 24+

Because there are only two digits in binary (0 and 1). The multiplication algorithm becomes only:

• Add the Shifted Multiplicands

• Shift Multiplicand • Multiply Shifted Multiplicand by 1 or 0

Easy to Implement

A x 1 = A; A x 0 = 0

Addition of many operands?Issue: How to add more than two operands

at the same time ?

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Adding Partial ProductsIssue: How to add more than two operands at the same time ?

bits012

3031

Mu

ltiplier

Multiplicand 00000000h (0 on 32 bits)

31

+

+

31

+

+

31

31

• Uses many Adders• Need circuit that uses

one to few adders because of size limitations

• Parallel Multipliers are used in high performance, multiplication intensive, architectures like DSP (Digital Signal Processing).

TOO E

XPEN

SIVE

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Iterative SolutionFull Parallel Multiplier is too expensive

Solution

Iteratively add the partial products

Advantages

Uses ONEAdder Only

Inconvenients

Much Slower thanParallel Multiplication

Circuit

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First Multiplication Algorithm

Shift Right

Shift LeftMultiplicand

Multiplier

64-bit ALU

ProductWrite

64 bits

64 bits

32 bits

Control test

Shift the Multiplicand Left to realize the multiplication by the order of the digit

Shift the Multiplier right to get out each digit

LSB first and MSB last

Control the write of the product register to only add partial products corresponding to a multiplier digit equal to 1

Add the product register content to every potential

partial product (shifted multiplicand) all the time.

Result is only written when appropriate

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First Multiplication Algorithm(2)Start

Bit 0 of Multiplier = 0

?Product Product + Multiplicand

Shift Left Multiplicand with 1 bit

Shift Right Multiplier with 1 bit

32nd Repetition?

Done

=0=1

No: < 32 repetitions

Yes: 32 repetitions

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Multiplication Circuit Improvement

Current Circuit has• 64-bits Multiplier Register used to shift the Multiplier.

– Shifting the Multiplier means inserting 0s (known value).• Reserving bits for holding known values is a waste of resources

– Anytime, Register contains 32 data bits and 32 0s.– 100% overhead just to shift

• 64-bits Adder is not necessary because:– Addition is done between two 32 bits operands

• Either add lower bits of product with lower 0s of the shifted multiplier• Or add the higher bits of the product which are 0s with the leading

bits of the shifted multiplicand

Need to Reduce the cost of the Multiplication Circuit

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AnalogyMultiplication Method is the same.

Two Ways of Implementing the same algorithm

1. Shift the Multiplicand register forward and do not shift the Product register (what we have seen so far)

2. Shift the Product register backward and do not shift the Multiplicand register (the other method)

Similar to having two methods of making a moving scene in a movie

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Movie Making Tips

Is The Car Moving Forward or the Trees moving Backward ???

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Method 1

The Car is Moving Forward The Camera/Observer is attached to the car

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Method 2

• The Car is a Fake Car.• The Camera/Observer and the Fake Car are both

fixed• The trees are pictures fixed on a moving panel

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Shifting Backwards

10101101010110.+

0000000..

0000000...

1010110....

100000010+

100000010+

0100000010+

11001100010

101011010011x

10101100000000

+1010110

1010110+

0000000

1010110

100000010

+

0100000010

+00100000010

+

11001100010

101011010011x

10101100000000

+

01010110

0100000010

001000000100000000

000100000010

• Shift Multiplicand Left• No Shift for the Product

• No Shift for the Multiplicand• Shift the Product Right (Backward)

Multiplicand Multiplier Product

Product InitialMcand x 1 Shiftd 0 bits

Mcand x 1 Shiftd 1 bits

Mcand x 0

Mcand x 0

Mcand x 1 Shiftd 4 bits

Product InitialMcand x 1

Sh. Product RightMcand x 1




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Shift Right

Multiplicand

Multiplier

32-bit ALU

Product

Write

64 bits

32 bits

32 bits

Control test

Second Multiply Algorithm

Shift Right

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Start

Bit 0 of Multiplier = 0

?Product[63:32]

Product[63:32] + Multiplicand

Shift Right Product with 1 bit

Shift Right Multiplier with 1 bit

32nd Repetition?

Done

=0=1


Yes: 32 repetitions

Second Multiply Algorithm (2)

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Another Improvement

– The lower 32-bits 0s are shifted out as the Product register is shifted right

– Only the Upper 32-bits are added to the Multiplicand

– Initialize the 64-bit Product Register with 0s • In Second Multiplication Algorithm:

Merge the lower 32-bits of Product Register with Multiplier Register

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Third Multiply Algorithm Multiplier Register merged with lower 32 bits of Product register

Multiplicand

32-bit ALU

Product

Write

64 bits

32 bits

Control testShift Right

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Third Multiply Algorithm (2)

Start

Bit 0 of Product = 0

?Product[63:32]

Product[63:32] + Multiplicand

Shift Right Product with 1 bit

32nd Repetition?

Done

=0=1


Yes: 32 repetitions

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Signed Multiplication• Convert multiplier and multiplicand into

positive numbers

• Perform the multiplication

• Compute the sign of the product

• Apply the sign to the product by either complementing the product (<0) or leaving it as is (>0)

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Booth’s AlgorithmPrinciple: Minimization of Intermediate Additions byVirtually reducing multiplier

0 1 1 1 1 0End of run

Middle of run

Beginning of run

ii+3 i+2 i+1

Normal Method: Product = Product + Mcand.(2i+3 + 2i+2 + 2i+1 + 2i)

Booth’s Method: Product = Product + Mcand. (2i+4 -2i)

Current Bit Bit to the right Run Operation

1 0 Beginning of a run of 1s Subtract Multiplicand

1 1 Middle of a run of 1s Do Nothing

0 1 End of a run of 1s Add Multiplicand

0 0 Middle of run of 0s Do nothing

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Multiplication in MIPS• Separate pair of 32 bits registers to

contain the 64-bit product– Hi and Lo: 32 bits each. Result of

multiplication instructions always in Hi:Lo– 2 instructions to move the result from Hi/Lo to

MIPS registers: mflo and mfhi

• 2 Multiply instructions– mult: signed multiplication– multu: unsigned multiplication

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Division

827 21 8 < 21

827 21 82 > 21Find biggest digit d (from 1 to 9) which satisfies:

82 >= 21 x d

Determine d using:• Intuition (Guessing) when performed by a

Human• Algorithm that increases d until

• Either d x 21 > 82; use (d-1)• Or d = 9

82 > 21x182 > 21x282 > 21x382 < 21x 4Use (4-1) = 3

827 21

39- 63197

197 > 21x1……………………

197 > 21x8197 > 21x9Use 9

- 1898

Select One digit from Dividend to compare to Divisor

Smaller than Divisor, Consider Two digits

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Division Algorithm (in Decimal)

M = Leftmost Digit of Dividend

M >= DivisorShift Left Next Digit of

Dividend into MNo

Yes

d = 1

Shift Left Next Digit of Dividend into M

M <= d x Divisor d = 9No

d = d + 1No

d = d - 1

M = M – (d x Divisor)

Shift in d into Q

No MoreDigits in Dividend

YesYes

YesNo M: RemainderQ: Quotient

Start

Define M: temporary storage

Define Q: QuotientQ = 0

Done

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Division in Binary

001100111011 000000010101

Many steps before finding a number > DivisorPresence of leading 0s disturbs the conventional algorithm

000000011001 Extract digits from Dividend and Shift them to align them with Divisor

Every step the Extracted Digits are compared to the Divisor:If Divisor x 1 > Extracted Digits Shift in 0 in the QuotientIf Divisor x 1 <= Extracted Digits Shift in 1 in the Quotient

- 000000010101

000000000100000000100110

000001000111

- 000000010101

000000010001000000100011

- 000000010101

000000001110000000011101

- 000000010101

000000001000

In binary, d can only take the value 0 or 1.Means:Divisor x d <= Extracted Digits from Dividendd = 1

Quotient Register: Shift Left Serial In from LSB

Method of Extracting Digits from Dividend not Practical in Context of Logic Circuits

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Forced AlignmentTo Force the Alignment of the Dividend and the Divisor:

• Multiply the Divisor by 2n (Shift Left by n), n being the number of bits of both the Dividend and the Divisor

• Shift right (divide by 2) the Divisor until Divisor <= Dividend

000000010101000000000000

000000000000001100111011

000000001010100000000000000000000101010000000000000000000010101000000000000000000001010100000000000000000000101010000000000000000000010101000000000000000000001010100000

< 0 >= 0

Rest of the Algorithm Remains the Same

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First Division Algorithm

Shift Left

Shift rightDivisor

Quotient

64-bit ALU

RemainderWrite

64 bits

64 bits

32 bits

Control test

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First Division Algorithm (2)Start

Test Remainder

Shift Quotient to left setting the new rightmost bit to 1

Shift Right Divisor with 1 bit

33rd Repetition?Done

Remainder < 0

No: < 33 repetitionsYes: 33 repetitions

Remainder Remainder - Divisor

Remainder ≥ 0

Restore original value of RemainderRemainder Remainder + Divisor

Shift Quotient to left setting the new rightmost bit to 1

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Division Algorithm Improvement

• Current Circuit has• 64-bits Divisor Register used to shift the Divisor.

– Shifting the Divisor means inserting 0s (known value).• Reserving bits for holding known values is a waste of

resources– Anytime, Register contains 32 data bits and 32 0s.– 100% overhead just to shift

• 64-bits ALU is not necessary because:– Subtraction is done between two 32 bits operands

(after alignment of Divisor and Dividend)

Need to Reduce the cost of the Division Circuit

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Shifting Dividend ForwardShifting the Divisor Backward (Right) and

Fixing the Dividend/Remainder is equivalent to:

Fixing the Divisor and Shifting the Dividend/Remainder Forward (Left)

Similar to the Analogy made in improving the Multiplication Algorithm

In Second Method:• Dividend/Remainder Register still 64-bits, initialized with Dividend

aligned right with upper 32-bits initialized to 0• Divisor Register is reduced to 32-bits and is not shifted.

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Second Division Algorithm

Shift Left

Divisor

Quotient

32-bit ALU

Remainder Write

64 bits

32 bits

32 bits

Control testShift Left

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Another Improvement

In Second Algorithm:• Remainder Register upper 32-bits initialized to 0s• Remainder Register is shifted left 32 times.• 0s are inserted in the LSB of the Remainder Register• Lower 32 bits end-up with 0s• Quotient Register: 32-bit LSB serial-in left shift register• Data is progressively shifted-in in the Quotient Register

Merge the lower 32-bits of Remainder Register

with Quotient Register

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Final Division Algorithm

Divisor

32-bit ALU

Remainder Write

64 bits

32 bits

Control testShift Right

Shift Left

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Division in MIPS• Separate pair of 32 bits registers to contain the

64-bit remainder:– Hi and Lo: 32 bits each. – Lo: Contains Quotient– Hi: Contains Remainder– 2 instructions to move the result from Hi/Lo to MIPS

registers: mflo and mfhi

• 2 Divide instructions– div: signed division– divu: unsigned division

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