cmos soi technology

Design of Distributed Amplifiers in 130 nmCMOS SOI Technology

EMIC Laboratory

Mehdi SI MOUSSA

Outline

Motivations & Challenges

Distributed amplification

Designed circuits

EMIC Laboratory

Designed circuits

Performances vs. Temperature

Conclusions

Historical motivation: radiation hardness

- small cross section for ionizing particles

Present motivation: enhanced performance

- higher speed

- lower power

New design options:

Gate

Source Drain

Why SOI CMOS

Buried oxide

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- high resistivity substrates

- bonding to “exotic” substrates

(e.g. quartz)

- multiple-gate (double, triple, etc.) devices

MOSFET transistor on Bulk CMOS

Silicon substrate)Silicon substrate

MOSFET transistor on SOI CMOS

At same power consumption:Speed > 15 %

At same speed:Power consumption < 30 %

Where SOI is being used?

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Where SOI is being used?

EMIC Laboratory

How about RF in SOI ???

Motivations

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(International Technology Roadmap for Semiconductors, ITRS 2003)

Motivations

• Use of CMOS for full integration ( low cost ).

• UWB Networks require broadband circuits.

• High speed needed beyond 10 GHz.

• Increase of the cut-off frequencies in CMOS/SOI transistors.

350CMOS Bulk

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0

50

100

150

200

250

300

0 50 100 150 200 250 300

Lpoly (nm)

Fm

ax (

GH

z)

CMOS BulkCMOS SOICMOS SOI DTMOSST-M. - Floating-BodyST-M. - Body-Contact[IBM:04]

[Crolles II Alliance:04]

[Intel:04]

[IMEC:04]

[ST-M.:04]

[ST-M.:04]

Challenges

• Quality of Passive structures, key to success: High-performance

passives on lossy silicon substrate.

• Performances vs. temperature.

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Goal of this work:

investigate the capabilities of SOI CMOS process

for wideband applications

CMOS vs. SOI

- Reduced parasitic capacitances lead to higher frequency devices.

- Lower leakage current.- High-resistivity SOI wafers Low losses.

- Low-cost and mature technology.- Low-Voltage-Low-Power consumption. - Mixed analog-digital circuits (one-chip).- High degree of integration.

CMOS Bulk & SOI TechnologyCMOS Bulk & SOI Technology SOI TechnologySOI Technology

EMIC Laboratory

MOSFETMOSFET BulkBulk MOSFETMOSFET SOISOI

Distributed Amplification (1)

• Wideband amplification is important for many systems: Ultra Wide Band (UWB) transceivers, optical communication …

• Distributed Amplification would allow us to operate close to ft, enhancing CMOS microwave potential.

Ld L L L /2L /2 L L L /2L /2

EMIC Laboratory

Vout

Vin

Vout

Vin

Ld Ld Ld Ld/2Ld/2

Lg/2 Lg Lg/2Lg

Gate line

Drain line

Ld Ld Ld/2Ld/2

Lg/2 Lg Lg/2Lg

Gate line

Drain lineTermination

Termination

Z0

Z0

Termination

Z0

Z0


Question : How to reduce the parasitic elements effects ?

Solution : the input and output capacitances of the transistors are

combined with lumped inductors to form artificial transmission lines.

Birth of the Distributed Amplifier

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Historical invented by Percival in 1936 landmark paper by Ginzton et al. in 1948 Reappearance since about 1980 (GaAs technology) Now: CMOS implementation

• Limited Gain- Bandwidth product in conventional circuit design.

• Placing devices in parallel manner gm but BW

•Cascading the active devices multiplicative gain + need of


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interstage circuit matching networks.

• Distributed Amplification adds FET’s gain without combining their

input capacitance.

Topology

Two artificial transmission lines (gate and drain lines) are coupledthrough common-source transistor devices.

Characteristics : Flat frequency response from DC to several GHz.


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Relaxed gain-bandwidth trade-off:

Gain added up by active devices.

Bandwidth limited by loaded transmission lines.

Vdrain

Zd

VgateZg

Input

Output

Gate Line

Drain Line

(1) (2)

(3)

(4)


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Gate Line (2)

Operating

•The forward wave (from (1) to (2)) on the gate line is amplified by each

transistor.

•Each transistor adds power in phase to signal at each tap point on the

drain line.

•The forward traveling wave on the gate line and the backward (to (3)) onthe drain line are absorbed by terminations matched to loadcharacteristic impedance of the gate and drain lines.

• FET’s Cgs increases with transistor size.

• Distributed Amplification adds FET’s gain without combining their

input capacitance.

• Absorbs input/output capacitance as part of the lumped elements of an

Design Issues

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“Artificial Transmission Line”

• Uses line delay equalization to add signals constructively at the FET’s

drain.

•Passives require high Q to minimize losses.

STEP 1: Specifications

STEP 2 : Choose a topology

STEP 3 : Choose an active device

Design methodology

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STEP 4 : Power and noise figure matching conditions

STEP 5 : Choose a bias circuit

STEP 6 : Basic circuit simulation and optimization

Satisfied specifications

No

STEP 7 : Final layout

End

Yes

• Gain : 7 dB.

• Bandwidth : 0.5 – 20 GHz .

Specifications

State-of-the art - CMOS technology - (2003)

Reference Ft/Fmax (GHz) Topology Gain (dB) BW (GHz)

[Lui et al.:2003]

CMOS bulk 180 nm70/58

3 cascode stages,

Inductances7.3 0.1-22 GHz

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• Number of transistors : 4. (Most of the designed DAs use 4 transistors)

• Active elements: 130 nm SOI Floating Body transistors. (ST Microelectronics)

• Passive elements : TFMS (Thin Film Micro Strip) line.

• Bias : use the voltage values which provide the maximum gm.

Transmission line

TFMS on 130 nm SOI CMOS Technology

Mulilayered-dielectric (oxide/nitride)

AlucapCopper (M6)

Copper (M1 + VIA1 + M2)

2.9 µm

W

0.9 µm1.78 µm

ADVANTAGES

Electrical characteristics are independent of substrate resistivity:

possible use of low or high resistivity substrate

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Si Substrate

Buried Oxide

Copper (M1 + VIA1 + M2)

STI (oxide)

resistivity substrate

DRAWBACKS

High impedance (narrow

conductor):

high metallic losses

Reduction of metallic losses with ALUCAP stacked on Cu-6

Common source distributed amplifier (1)

130 nm SOI CSDA

Transistors Floating Body

WT = 60 x 2

Fmax = 83 GHz

Gate line L = 400 µm

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Gate line

Output

RF pad

Cg

Cd

Input

RF pad

Transistors

Drain line

Gate line

Output

RF pad

Cg

Cd

Input

RF pad

TransistorsTransistors

Drain line


W= 4.5 µm

Drain line L = 600 µm

W= 9 µm

Area (mm²) 0.5x1.5

Common source distributed amplifier (2)

-15

-10

-5

0

5

10

0 10 20 30 40

Frequency (GHz)

S2

1, S

11 (

dB

)

S21

S11

-15

-10

-5

0

5

10

0 10 20 30 40

Frequency (GHz)

S2

1, S

11 (

dB

)

S21

S11

130 nm SOI CSDA

S21 (dB) 4.5±1.2

S11/S22 (dB) <-7.9/ <-6.7

BW (GHz) 0.4-30

Area (mm²) 0.5x1.5

NF (dB) 4.6 - 7.0

Vdd (V) 1.4

Pdc (mW) 66

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-15

-10

-5

0

5

10

0 10 20 30 40

Frequency (GHz)

NF

, S

22 (

dB

)

NFS22

-15

-10

-5

0

5

10

0 10 20 30 40

Frequency (GHz)

NF

, S

22 (

dB

)

NFS22

Pdc (mW) 66

Problems

Gain < 7 dB

No flat gain

Miller effect

Cascode pair

S2

D2G2

• MOSFET : important Miller effect Consequence : ripple on the gain

Solution : cascode pair

.

• Microstrip lines: high losses

Consequence : fast decrease of the gain

Solution : cascode pair + additional lines

S2

D2G2

Lsd

Lcg

EMIC Laboratory

S1

D1G1

( ) ( )ZeCRC

g1

RCω1R

Ze gs2ds2ds2gs2

m22ds2

2ds2

2ds2

D2 ℜ+

−

+=ℜ

. Solution : cascode pair + additional lines

Output impedance at drain D2 :

Negative resistance=

Trade-off between loss compensation and stability

S1

D1G1

Aim: have a flatter gain !

Cascode distributed amplifier (1)

InputRF pad

OutputRF pad

Drain Line DC biasRF pad

Cd

InputRF pad

OutputRF pad

Drain Line DC biasRF pad

Cd

130 nm SOI CSDA

4 stages, cascode

Drain line loss compensation

technique

Transmission lines: TFMS with Cu-6

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Gate Line CgGate Line Cg

Cdec

Lcg

T2

T1Gate line

Lsd

Drain line

Biasing of T2’s GateCdec

Lcg

T2

T1Gate line

Lsd

Drain line

Biasing of T2’s Gate

130 nm SOI CSDA

Transistors Floating Body

WT = 30 x 2

Fmax = 125 GHz


W= 2 µm

Drain line L = 380 µm

W= 2 µm

Area (mm²) 0.5x1.5

Cascode distributed amplifier (2)

-30

-20

-10

0

10

0 10 20 30 40

Frequency (GHz)

S21, S

11 (

dB

)

FBDA

BCDA

S21

S11

-30

-20

-10

0

10

0 10 20 30 40

Frequency (GHz)

S21, S

11 (

dB

)

FBDA

BCDA

S21

S11130 nm SOI This work

FB CSDAThis workFB CDA

S21 (dB) 4.5±1.2 6.8±1.0

S11/S22 (dB) <-7.9/ <-6.7 <-6.2/ <-6.7

BW (GHz) 0.4-30 0.4-27

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Frequency (GHz)

-30

-20

-10

0

10

0 10 20 30 40

Frequency (GHz)

S22, N

F (

dB

)FBDABCDA

NF

S22

Frequency (GHz)

-30

-20

-10

0

10

0 10 20 30 40

Frequency (GHz)

S22, N

F (

dB

)FBDABCDA

NF

S22

BW (GHz) 0.4-30 0.4-27

Area (mm²) 0.5x1.5 0.5x1.5

NF (dB) 4.6 - 7.0 6.4-7.8

Vdd (V) 1.4 1.4

Pdc (mW) 66 55

BCDA designed by Dr. C. Pavageau (IEMN)

State-of-the art

Gain, Matching, Bandwidth, Area, Noise Figure, Linearity, DC Power for state-of-the art DA

Technology S21 (dB)

S11/S22(dB)

Bandwidth(GHz)

Area(mm²)

N.F(dB)

OP1dB(dBm)

Vdd (V)

PDC(mW)

0.18µm Bulk CMOS

7.3±±±±0.8 <-8/<-9 0.6 –22 0.90 X 1.50 4.3 – 6.1 - 1.3 52

InAlAs HBT 5.1±±±±1.2 <-5/<-5 2.0 –50 1.80 X 1.20 - - 4 89

InP HEMT 14±±±±0.8 <-9/<-10 1.0 – 90 2.50 X 1.10 8.0 – 9.0 - - -

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GaAs HEMT 6.0±±±±1.0 <-13/<-4 2.0 –50 1.97 X 1.25 - 22 15 1900

0.12µm SOI-7stg

7.3±±±±1.3 <-7/<-7 4.0 –86 1.46 X 0.72 5.0 – 3.6 10 2.6 130

0.12µm SOI-5stg

4.0±±±±1.2 <-7/<-7 4.0 –91 1.11 X 0.72 6.2 – 4.2 9 2.6 90

This work FBCDA-4stg

7.1±±±±1.1 <-6.2/<-6.7 1 –26 0.50 X 1.50 6.4 – 7.8 6.2 1.4 55

This work BCDA-4stg

5.4±±±±1.4 <-7.9/<-6.7 1 –20 0.50 X 1.50 6.5 – 7.5 6.2 1.4 58

Cascode DA: FB and BC

-30

-25

-20

-15

-10

-5

0

5

10

S21 (

dB

)

4

5

6

7

8

9

10

11

12

NF

(d

B)

Body ContactFloating Body

TransistorBody-

contactFloating-Body

Fmax (GHz) 76 125

Gain (dB) 5.4±1.4 7.1±1.1

BW (GHz) 1-20 1-26

S11/S22 (dB) < -8 < -6

Summary of the best performances of our designs

EMIC Laboratory

-30

0 10 20 30 40Frequency (GHz)

4

NF (dB)6.5-7.5

6-20 GHz

Line losses deeply reduce gain and bandwidth !!!

Problem

- Main contributor to the losses in the DA

Losses in the TFMS lines.

- How to decrease the losses:

CPW on HR silicon substrate. W SW SW S

Passive performances

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STD-Si substrate

(20 ΩΩΩΩ.cm) OR

HR-Si substrate(>1000 ΩΩΩΩ.cm)

BOX (400 nm)

0.9 µm Cu

Oxide (SiO2)(2.2 µm)

Dielectric(770 nm)

STD-Si substrate

(20 ΩΩΩΩ.cm) OR

HR-Si substrate(>1000 ΩΩΩΩ.cm)

BOX (400 nm)

0.9 µm Cu

Oxide (SiO2)(2.2 µm)

Dielectric(770 nm)

CPW on High resistivity substrates

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- Performances

TFMS with M6 : 1 dB/mm @20GHz.

TFMS with M6+ALUCAP : 0.75 dB/mm @20GHz.

CPW on HR : ~ 0.3 dB/mm on HR-1kΩ@ 20 GHz.

Distributed amplifier with CPW lines (1)

InputRF pad

Gate line

Drain line

VbiasRF pad

Cg

Cd

Cdec

OutputRF pad

InputRF pad

Gate line

Drain line

VbiasRF pad

Cg

Cd

Cdec

OutputRF pad

InputRF pad

Gate line

Drain line

VbiasRF pad

Cg

Cd

CdecCdec

OutputRF pad

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CPW_CDA designed by Dr. C. Pavageau (IEMN)

Gate line

Drain line

T1

Cdec

T2

Bias transmission line

Connexion gnd-gnd-(Metal -1)

Gate line

Drain line

T1

Cdec

T2



Gate line

Drain line

T1

Cdec

T2




Connexion gnd-gnd-(Metal -1)Connexion gnd-gnd-(Metal -1)

Layout area: 675 x 2180 µm²


Floating-BodyTransistor

125F (GHz)

TFMS wo ALUCAP

CPW on HR substrate

Lines

1st run 2nd run

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125Fmax (GHz)

1-401-26BW (GHz)

7.1±1.1

61

7.1±±±±1.6Gain (dB)

98GBW (GHz)

1.50.75Area (mm²)

7555Pdc (mW)


• Using high resistivity substrate enables low loss CPW transmission lines.

• Using the same architecture as for TFMS lines

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~ 50% increase of the bandwidth !

SOI @ high temperature

Advantages of SOI over bulk CMOS:

• absence of thermally-activated

latch up.

• reduced leakage current.

Application Temperatures

Well logging 75-600C

Oil Wells 75-175C

Gas Wells 150-225C

Steam injection 200-300C

Geothermal energy 200-600C

Automotive 150-600C

Underhood 50-600C

Engine sensors up to 600C

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Engine sensors up to 600C

Combustion and exhaustsensors

up to 600C

ABS up to 600C

Aircraft 150-600C

Internal equipment 150-250C

Engine monitoring 300-600C

Surface controls 300-600C

Satellites (Venus probe) 150-600C

Commercial nuclear 30-550C

Increase temperature operation !

J.-P. Colinge, “Silicon-on-Insulator Technology: Materials to VLSI”, Kluwer Academic Publishers. 2nd Ed. 1997.

Performances vs. high temperature

5

6

7

8

9

10

|S2

1|

(dB

)

T=25°C

T=50°C

T=100°C

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0

1

2

3

4

0 10 20 30

Frequency (GHz)

|S2

1|

(dB

)

T=100°C

T=150°C

T=200°CT=250°C

Gain & Bandwidth vs. temperature

Temperature S21@ midband (dB)

Cut-off frequency @ 0 dB (GHz)

Room temperature 6.8 27

50°C 6.2 27

100°C 4.3 26

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100°C 4.3 26

150°C 3.6 25

200°C 3.2 22

250°C 2.7 12

Temperature effect analysis

- The gain of the DA depends mainly on:

• The transconductance of the MOSFET gm

• Gate and drain line losses ααααg and ααααd

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- Temperature effect measurements:

• S parameters of the MOSFET vs. T

• S parameters of the microstrip line vs. T

Measured transconductance vs. temperature

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Measured lineic losses vs. temperature

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Temperature effect results

- On the MOSFET:

Decrease of 30% of the gate transconductance gm

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- On the Microstrip line:

Increase of 80% of the lineic losses

Due to the increase of the metallic losses

Contribution of passive and active devices

3

4

5

6

7

8

9

|S2

1| (d

B)

TFMS & FET effect

T=25°C

TFMS effect

FET effect

3

4

5

6

7

8

9

|S2

1| (d

B)

TFMS & FET effect

T=25°C

TFMS effect

FET effect

EMIC Laboratory

Distributed Amplifiers at high-temperature:

TFMS are the main contributor to the decrease

of the gain and the bandwidth !!!

0

1

2

3

0 5 10 15 20 25 30 35

Frequency (GHz)

TFMS & FET effect

0

1

2

3

0 5 10 15 20 25 30 35

Frequency (GHz)

TFMS & FET effect

Conclusion (1)

• SOI is a proven solution for digital applications.

SOI brings higher speed and lower power for the digital world

• Is SOI suitable for RF applications ?Yes

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SOI brings the RF Soc capabilities

• low voltage for RF design => low power

• less substrate crosstalk => digital and RF closer

• high resistivity substrate => high Q factor for passives

• mature technology for the realization of high-temperature IC’s

Conclusion (2)

• Can we do wideband circuits on SOI ?

Take advantages of the SOI technology and the distributed architecture

• low parasitic capacitances => higher Ft and Fmax

• Enhancement of the bandwidth due to the use of Distributed

Yes

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• Enhancement of the bandwidth due to the use of Distributed

Amplification.

• Distributed Amplification places CMOS – SOI in competition

with GaAs and SiGe for High Speed Microwave circuit applications

and UWB.

BUTBe careful with the passives!!!

Perspectives

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The future of interconnection technology*

*T. N. Theis, IBM J. RES. DEVELOP. VOL. 44 NO. 3 MAY 2000

Perspectives

One-chip RF Transceiver

One of the main goal for microwave designers is to build one-chip RF transceivers

One-chip RF transceiver means:

• Integration of multi-standard applications in the same device (GSM,

UMTS, Bluetooth, …)

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UMTS, Bluetooth, …)

• Portable applications

- High integration degree- Light devices- Low-power consumption- Low-voltage supply

• Mass production: low cost

Perspectives

TVTVTVTV

VCRVCRVCRVCR

DVDDVDDVDDVD

CDCDCDCD

RemoteRemoteRemoteRemote

Industrial &

Commercial

Consumer

Electronics

MonitorsMonitorsMonitorsMonitors

SensorsSensorsSensorsSensors

AutomationAutomationAutomationAutomation

ControlControlControlControl

PC

Peripherals

ZigBee: Target Market

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Low Data Rate

Radio Devices

MouseMouseMouseMouse

KeyboardKeyboardKeyboardKeyboard

JoystickJoystickJoystickJoystick

GamepadGamepadGamepadGamepad

SecuritySecuritySecuritySecurity

HVACHVACHVACHVAC

LightingLightingLightingLighting

ClosuresClosuresClosuresClosures

PETsPETsPETsPETs

GameboysGameboysGameboysGameboys

EducationalEducationalEducationalEducational

MonitorsMonitorsMonitorsMonitors

DiagnosticsDiagnosticsDiagnosticsDiagnostics

SensorsSensorsSensorsSensors

Personal

Healthcare

Toys &

Games

Home

Automation

Peripherals

Perspectives

• Very low cost, Very low cost, Very low cost, Very low cost,

• Low power consumption, Low power consumption, Low power consumption, Low power consumption,

• High Temperature EnvironmentHigh Temperature EnvironmentHigh Temperature EnvironmentHigh Temperature Environment

Motivation

Design of RF circuits for ZigBee Standard

EMIC Laboratory

• High Temperature EnvironmentHigh Temperature EnvironmentHigh Temperature EnvironmentHigh Temperature Environment

Take advantages of the SOI CMOS technology

Questions ??

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Questions ??

cmos soi technology

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