CMOS SOI Technology

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<ul><li> 1. Design of Distributed Amplifiers in 130 nm CMOS SOI Technology Mehdi SI MOUSSA EMIC Laboratory </li> <li> 2. Outline Motivations &amp; Challenges Distributed amplification Designed circuits Performances vs. Temperature Conclusions EMIC Laboratory </li> <li> 3. Why SOI CMOS Historical motivation: radiation hardness Gate - small cross section for ionizing particles Source Drain Present motivation: enhanced performance - higher speed - lower power Buried oxide New design options: - high resistivity substrates Silicon substrate) Silicon substrate - bondingAt same power consumption: to exotic substrates (e.g. quartz) Speed &gt; 15 % MOSFET transistor on Bulk CMOS MOSFET transistor on SOI At same speed: - multiple-gate (double, triple, etc.) devices Power consumption &lt; 30 % EMIC Laboratory </li> <li> 4. Where SOI is being used? EMIC Laboratory </li> <li> 5. Where SOI is being used? How about RF in SOI ??? EMIC Laboratory </li> <li> 6. Motivations (International Technology Roadmap for Semiconductors, ITRS 2003) EMIC Laboratory </li> <li> 7. Motivations Use of CMOS for full integration ( low cost ). UWB Networks require broadband circuits. High speed needed beyond 10 GHz. Increase of the cut-off frequencies in CMOS/SOI transistors. 350 CMOS Bulk [Crolles II Alliance:04] 300 CMOS SOI CMOS SOI DTMOS Fmax (GHz) ST-M. - Floating-Body 250 [Intel:04] [IBM:04] ST-M. - Body-Contact 200 [IMEC:04] 150 [ST-M.:04] 100 50 [ST-M.:04] 0 0 50 100 150 200 250 300 Lpoly (nm) EMIC Laboratory </li> <li> 8. Challenges Quality of Passive structures, key to success: High-performance passives on lossy silicon substrate. Performances vs. temperature. Goal of this work: investigate the capabilities of SOI CMOS process for wideband applications EMIC Laboratory </li> <li> 9. CMOS vs. SOI SOI Technology CMOS Bulk &amp; SOI Technology - Reduced parasitic capacitances lead to - Low-cost and mature technology. higher frequency devices. - Low-Voltage-Low-Power consumption. - Lower leakage current. - Mixed analog-digital circuits (one-chip). - High-resistivity SOI wafers Low losses. - High degree of integration. MOSFET Bulk MOSFET SOI EMIC Laboratory </li> <li> 10. Distributed Amplification (1) Wideband amplification is important for many systems: Ultra Wide Band (UWB) transceivers, optical communication Distributed Amplification would allow us to operate close to ft, enhancing CMOS microwave potential. Ld Ld Ld Ld/2 Ld/2 Termination Drain line Z0 Vout Lg Lg/2 Lg Lg/2 Vin Z0 Gate line Termination EMIC Laboratory </li> <li> 11. Distributed Amplification (2) Question : How to reduce the parasitic elements effects ? Solution : the input and output capacitances of the transistors are combined with lumped inductors to form artificial transmission lines. Birth of the Distributed Amplifier Historical invented by Percival in 1936 landmark paper by Ginzton et al. in 1948 Reappearance since about 1980 (GaAs technology) Now: CMOS implementation EMIC Laboratory </li> <li> 12. Distributed Amplification (3) Limited Gain- Bandwidth product in conventional circuit design. Placing devices in parallel manner gm but BW Cascading the active devices multiplicative gain + need of interstage circuit matching networks. Distributed Amplification adds FETs gain without combining their input capacitance. EMIC Laboratory </li> <li> 13. Distributed Amplification (4) Characteristics : Flat frequency response from DC to several GHz. Topology Two artificial transmission lines (gate and drain lines) are coupled through common-source transistor devices. Relaxed gain-bandwidth trade-off: Gain added up by active devices. Bandwidth limited by loaded transmission lines. EMIC Laboratory </li> <li> 14. Distributed Amplification (5) Vdrain Drain Line (4) Zd Output (3) Vgate Zg Input (1) (2) Gate Line Operating The forward wave (from (1) to (2)) on the gate line is amplified by each transistor. Each transistor adds power in phase to signal at each tap point on the drain line. The forward traveling wave on the gate line and the backward (to (3)) on the drain line are absorbed by terminations matched to load characteristic impedance of the gate and drain lines. EMIC Laboratory </li> <li> 15. Design Issues FETs Cgs increases with transistor size. Distributed Amplification adds FETs gain without combining their input capacitance. Absorbs input/output capacitance as part of the lumped elements of an Artificial Transmission Line Uses line delay equalization to add signals constructively at the FETs drain. Passives require high Q to minimize losses. EMIC Laboratory </li> <li> 16. Design methodology STEP 1: Specifications STEP 2 : Choose a topology STEP 3 : Choose an active device No STEP 4 : Power and noise figure matching conditions Yes Satisfied STEP 7 : specifications Final layout STEP 5 : Choose a bias circuit End STEP 6 : Basic circuit simulation and optimization EMIC Laboratory </li> <li> 17. Specifications Reference Ft/Fmax (GHz) Topology Gain (dB) BW (GHz) [Lui et al.:2003] 3 cascode stages, 70/58 7.3 0.1-22 GHz CMOS bulk 180 nm Inductances State-of-the art - CMOS technology - (2003) Gain : 7 dB. Bandwidth : 0.5 20 GHz . Number of transistors : 4. (Most of the designed DAs use 4 transistors) Active elements: 130 nm SOI Floating Body transistors. (ST Microelectronics) Passive elements : TFMS (Thin Film Micro Strip) line. Bias : use the voltage values which provide the maximum gm. EMIC Laboratory </li> <li> 18. Transmission line TFMS on 130 nm SOI CMOS Technology W ADVANTAGES Alucap 1.78 m Copper (M6) 0.9 m Electrical characteristics are independent of substrate resistivity: 2.9 m Mulilayered-dielectric (oxide/nitride) possible use of low or high resistivity substrate Copper (M1 + VIA1 + M2) STI (oxide) Buried Oxide DRAWBACKS Si Substrate High impedance (narrow conductor): high metallic losses Reduction of metallic losses with ALUCAP stacked on Cu-6 EMIC Laboratory </li> <li> 19. Common source distributed amplifier (1) 130 nm SOI CSDA Transistors Floating Body WT = 60 x 2 Fmax = 83 GHz Gate line L = 400 m W= 4.5 m Drain line Drain line L = 600 m Output RF pad W= 9 m Cg Area (mm) 0.5x1.5 Cd Input RF pad Gate line Transistors EMIC Laboratory </li> <li> 20. Common source distributed amplifier (2) 130 nm SOI CSDA 10 4.51.2 S21 (dB) 5 S21, S11 (dB) S11/S22 (dB)</li></ul>