cmos fabrication technology1

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03/12/22 03/12/22 VLSI Design course EE405 VLSI Design course EE405 1 CMOS Fabrication Technology CMOS Fabrication Technology and Design Rules and Design Rules

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cmos fabrication

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04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 11

CMOS Fabrication Technology CMOS Fabrication Technology and Design Rulesand Design Rules

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 22

CMOS Inverter CMOS Inverter

CMOS Inverter

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 44

CMOS Noise MarginsCMOS Noise Margins

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 55

CMOS TimingsCMOS Timings

Tp = (TpHL + TpLH )/2Propagation Time:

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 66

CMOS Transient ResponseCMOS Transient Response

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 77

MOS TransistorMOS Transistor

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 88

MOS CurrentMOS Current

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 99

MOS Current EquationsMOS Current Equations

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 1010

Velocity SaturationVelocity Saturation At a certain electric field, the velocity of carriers does not increase but tends to be constant.

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 1111

Velocity SaturationVelocity Saturation

Short channel devices reach velocity saturation earlier than long channel ones.

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 1212

Threshold VoltageThreshold Voltage

The minimum voltage when the device turns on is called The minimum voltage when the device turns on is called VVthth

For NMOS: VFor NMOS: Vgg > V > Vthth

For PMOS: VFor PMOS: Vgg < V < Vthth

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 1313

Body EffectBody Effect

Threshold voltage increases if the body of PMOS is not connected to Vdd or Vss for NMOS.

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 1414

Transistor LeakageTransistor Leakage

Leakage current is exponential with Vgs.

Also called Subthreshold behavior

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 1515

Leakage CurrentLeakage CurrentSubthreshold current can be calculated by:

Increasing Vth decreases Leakage current but slows down the device

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 1616

Leakage ComponentsLeakage Components1. pn junction reverse bias current2. Weak inversion3. Drain-induced barrier lowering (DIBL)4. Gate-induced drain leakage (GIDL)5. Punchthrough6. Narrow width effect7. Gate oxide tunneling8. Hot carrier injection

04/18/2304/18/23 VLSI Design course EE405VLSI Design course EE405 1717

CMOS FabricationCMOS Fabrication

Both NMOS and PMOS to be built on the same chip Both NMOS and PMOS to be built on the same chip substratesubstrate

To create both devices, special regions called wells or To create both devices, special regions called wells or tubs must be created in substratetubs must be created in substrate

A p-well is created in n-type substrate and an n-well is A p-well is created in n-type substrate and an n-well is created in p-type substrate created in p-type substrate