clu paper presentation mv

CEU Paper, M. Zahran, WSEAS PE' 07, Beijing - CHINA 1

Charge Equalization Unit for a NiCd Battery of Small Earth Observation

Satellite EPS Simulation

Dr. Mohamed Bayoumy A. ZahranDr. Mohamed Bayoumy A. ZahranAssoc. Prof. Researcher in Electronics Research Institute, &

Member in Space Program of National Authority for Remote Sensing and Space Science, SE and EPS GL of MisrSat-2,

Cairo - EGYPT

CEU Paper, M. Zahran, WSEAS PE' 07, Beijing - CHINA2

EPS Electrical Block Diagram


Functional Block Diagram of EPS


Why Charge Equalization Unit?

Protect the battery from critical modes of operation,

Help the weak cells to continue operation without deep discharging or reverse polarity,

Increase the battery lifetime, Move or shift the appearance

time of battery aging affects.


Survey of Charge Equalizer Techniques


Types of charge equalizers Dissipative Equalization

Techniques:1. Dissipative resistive shunts,2. Individual cell equalizer (ICE),3. Charge shunting,

Non-dissipative (dynamic) Equalization Techniques:

1. Flying Capacitor Charge Shuttling,

2. Charge Shuttling Between Two Cells,

3. Charge Shuttling with Several Cells,

ENERGY CONVERTERS:1. Switched Transformer,2. Charge equalization using isolated

flyback dc-to-dc converters,3. Charge equalization using bi-

directional isolated flyback dc-dc converters,

4. Shared transformer,5. Multiple Transformer,6. Charge equalization using a

centralized forward converter with a multi-winding transformer,

7. Reducing the number of secondary windings for the centralized forward converter scheme,

8. Current diverters using flyback converters with a centralized multi-winding transformer,

9. Current diverters using forward converters with a centralized


Dissipative charge equalizer

Dissipative resistive shunts

Individual cell equalizer

(ICE)

charge shunting


Non-dissipative (dynamic) Equalization Techniques

Flying Capacitor Charge Shuttling

Charge Shuttling Between Two Cells

Charge Shuttling with Several Cells


ENERGY CONVERTERS, Samples

Switched Transformer Charge equalization using isolated flyback dc-to-dc converter

Charge equalization using bi-directional isolated flyback dc-dc

converters

Shared transformer Multiple TransformerCharge equalization using a

centralized forward converter with a multi-winding transformer


Shared transformer Technique


Structure of CEU


1

Out1

v +-

Voltage Measurement

VRM-U

VRM-L

s -+

VRM Random Input VoltageVRM Output Voltage

VRM Output Current

VRM Monitoring

5

VRM Monitor

VCM MonitoringN/S

Red=black

12

VCM Monitor

VCM Input Voltage

VCM Input Current

Step1

Step

RandomNumber

Signal(s)Pulses

PWM Generator

1+

1

+2

2.1

2

Multi-WindingTransformer 9

1+

1

+2

2.1

2


1+

1

+2

2.1

2


1+

1

+2

2.1

2


1+

1

+2

2.1

2


1+

1

+2

2.1

2


gm

ds

Mosfet1

gm

ds

Mosfet Load

g

12

Ideal Switch

20

Gain1

-K-

Gain

Signal(s)Pulses

DiscretePWM Generator

Diode2

Diode1

Diode

CEU-6 Volt

CEU-6 I

CEU-5 Volt

CEU-5 I

CEU-4 Volt

CEU-4 I

CEU-3 Volt

CEU-3 I

CEU-2 Volt

CEU-2 I

CEU-1 Volt

CEU-1 I

Control Signal of CRMControl Signal of CRMControl Signal of CRMControl Signal of CRMControl Signal of CRMControl Signal of CRM

Control Signal of CRM


The VRM Results


The VCM Results 1/2


The VCM Results 2/2


CEU Simulink model and testing results with a resistive loading


CEU Simulink model and testing results with a battery cells loading

CEU Paper, M. Zahran, WSEAS PE' 07, Beijing - CHINA 24

CEU Power Circuit Design and Implementation


Push Pull Circuit and its Modes of Operation


Latest Version of the scaled up CEU to 11 Cells

L5

{Lload}

1 2

T itle

Size Docum ent Num ber Rev

Date: Sheet of

MS2 NRS CLU 002 11 <RevCode>

CLU Proj ect 2nd Stag e - NARSS-ERI Team Work

A3

1 1Friday, June 08, 2007

G-PUSH1 G-PULL1G-PUS H2 G-PULL2

TP 7 1

TP 8 1

VP-FB

TP 9 1

TP 10 1

D2MBR12035CT

TP 11 1

TP 12 1

T IR512

C6

{Cout}

IP-FB

R18

1

GND

TP 13 1

D1

MB R12035CTC2

{Cload}

TP 14 1

GND

TP 15 1

GND

TP 16 1

D3

MB R12035CT

TP 17 1

C5{Cload}

L3

{Lload}

1 2

TP 18 1

L1

{Lload}

1 2

CELL3

1.2V

HOLE1

CONN JACK

1

D4

MB R12035CT

HOLE2

CONN JACK

1

TP 19 1

C7{Cload}

HOLE3

CONN JACK

1

T IR112

TP 20 1HOLE4

CONN JACK

1

TP 21 1

L4

{Lload}

1 2

T IR212

L2

{Lout}

1 2

T IR312

R121k

21

R141k

R6

0

Power Circuit

M2IRF540

R22.5k

R13.5k

R15.5k

GND

R20

0.5k

R40

100K

13

2

R19

0.5k

Q1MOSFET N DGS

GND

GND

GNDGND

GND

Q2MOSFET N DGS

Q3

MOSFET N DGSQ4

MOSFET N DGS

PUSH2

PULL2

C9

{CT} R21 {RT}

R17

.5k

R16

.5k

24-34 V

24-34 V

2nd STAGE DC-DC CONVERTERINPUT: 20 +/- 0.5 VOUTPUT:1.2 +/- 0.05 V

Control Circuit

R26

{Rg }

R24{RD}

R28

3k

G-PUSH1

PUSH1

24-34 V

R34

{Rg }

R32{RD}

R36

3k

R38{RS}

PULL1

24-34 V

G-PULL1

Driver Circuits1st STAGE MOSFET DRIVERS

Part Reference = R30{RS}

U2

TL494

VCC12

IN1+1

IN1-2

IN2+16

IN2-15

C18

C211

COMP3

DTC4

OC13

E19

E210

CT5

VREF14 RT

6

JP4

3 21 4

JP5

1 23 4

GND

U1

TL494

VCC12

IN1+1

IN1-2

IN2+16

IN2-15

C18

C211

COMP3

DTC4

OC13

E19

E210

CT5

VREF14 RT

6

C4

{CT}

R11

{RT ]

R75k

R85k

R31M

24-34 V

JP1

1 23 4

R233k

C310n

R1

240

Ip-FBC1

.1uVp-FB

1st STAGE DC-DC CONVERTERINPUT: 21-34 VOUTPUT:20 +/- 0.5V

GND

GND

R9

0.5k

R10

0.5k

PUSH1

PULL1

R5

.5k

24-34 V

R4

.5k

JP3

1 23 4

R27

{Rg }

R25{RD}

R29

3k

R31{RS}

PUSH2

24-34 V

G-PUSH2

R35

{Rg }

R33{RD}

R37

3k

R39{RS}

24-34 V

PULL2

2nd STAGE MOSFET DRIVERS

G-PULL2

L9

{Lload}

1 2

T IR912

D6

MB R12035CTC10

{Cload}

D7

MB R12035CTC11{Cload}

L7

{Lload}

1 2

L6

{Lload}

1 2

CELL7

1.2V

D8


L8

{Lload}

1 2

T IR612

T IR712

T IR812

CELL5

1.2V

CELL6

1.2V

CELL8

1.2V

D9


L12

{Lload}

1 2

T IR1212

D10


L10

{Lload}

1 2

CELL10

1.2V

D11


L11

{Lload}

1 2T IR101

2

T IR1112

CELL9

1.2V

CELL11

1.2V

D12


JP2

3 21 4

JP6

3 21 4

TR2

Transformar

1212

77

11

22

1616

1515

88

1111

33

44

1313

99

1010

55

1414

66

T IR412

JP7

3 21 4

JP9

3 21 4

JP8

3 21 4

TP 1 1

TP 2 1

GND

M1IRF540

TP 3 1M3

IRF540

M4

IRF540

TP 4 1

Ls1

Ls2Lp2

Lp1

T R1

TP 5 1

CELL1

1.2V

CELL2

1.2V

TP 6 1

CELL4

1.2V

D5


24-34 V

GND


Real Images of the implemented CEU Circuit

Overview of the implemented circuit

Side-view of the implemented circuit


Real Images of the implemented CEU Testing with shallow loading

CLU Board and measurements instruments

Partially Loading of the CLU Circuit


Control Signals


Measured Values

Voltage and Primary Current of the CEU while shorting one of the CEU channels.

Value of the Short Circuit Current in one CEU Channel.


Thanks

?

clu paper presentation mv

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