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Clock gating

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Page 1: Clock gating
Page 2: Clock gating

Power Consumption Primitives

Characteristics of Power Consumption in

Microprocessors

Clock Gating and Power Reduction

Similar Approaches

Power Reduction Example

2

Page 3: Clock gating

P (total) = P (static) + P (dynamic)

Static Power

Currently Negligible But Considerable in Future

Dynamic Power

P (dynamic) = CL Vdd2.A.F

Major Part of Total Power (e.g. 95%)

3

Page 4: Clock gating

Clock Circuitry Power Consumption

15 to 45% of TotalP (clock circuitry) ~ Frequency

Activity of Functional Units

A (units) < 50% in Execution Time

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Page 5: Clock gating

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Clock tree consume more than 50 % of dynamic power. The components of this power are:

1)Power consumed by combinatorial logic whose values are changing on each clock edge

2) Power consumed by flip-flops and

3) The power consumed by the clock buffer tree in the design.

Clock Gating and Power Reduction

Page 6: Clock gating

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There are two types of clock gating styles available. They are:

1)Latch-based clock gating

2) Latch-free clock gating.

Page 7: Clock gating

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Latch free clock gating

Page 8: Clock gating

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Latch based clock gating

Page 9: Clock gating

Main Idea Clock Circuitry Partitioning Shutting down Unused Partitions

Implementation Creating Local Clocks Buffers or Flip-Flops with enable signal

Net Effects Reduction of Unnecessary Switching Switched Capacitance Reduction of Clock Circuitry Power Consumption Reduction

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Page 10: Clock gating

How to determine unused modules?

Dynamically in Decode StageStatically with Compiler Assistance

Disadvantages

Additional CircuitryMore Complicated Timing Analysis, Design, Test and

VerificationPossible High L x di/dt Noise

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Page 11: Clock gating

• Data Gating

– Effective in Wide Modules Like ALUs

– Complicated Design

– Possible Increase of Critical Path Delay

• Powering Down Unused Modules

– Possible Long Wake-up Times

– Need of Compiler and/or OS Support

• Using Asynchronous Systems

– Unnecessary Activity Elimination

– Harder Design

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Page 12: Clock gating

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Components - flip-flops, latches, ALU, adder, and shifter

Functions - decode, execute, and load store unit

Power Reduction Example

Page 13: Clock gating

• Clock Gating as an Architectural Technique

• Turning Unused Parts of Circuit Off

• High P(dynamic)/P (total) Ratio

• Decrease of Activity to Reduce Power

• Considerable Power Reduction (up to 25%)

• Highly Used Technique

13

Summary


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