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Clock Fundamentals

Paul KernPaul KernStaff Applications EngineerStaff Applications Engineer

January 2012January 2012

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What is a clock and what are the common frequencies?

Unlike a data waveform, a clock signal is a square wave whose frequency is usually constant.

Common frequencies include: 1 pps (pulse per second) used by GPS 8 kHz (commonly used in wired communcations) and is

commonly referred to as a BITS clock 19.44 MHz is a common reference clock in synchronous optical

(SONET) networks. 122.88 MHz is commonly used in wireless communications 125 and 156.25 MHz are common Ethernet reference clocks.

3

An Introduction to Phase-locked Loops (PLLs)

What is a phase-locked loop?

It is a control loop with an voltage-controlled oscillator (VCO) whose frequency is constantly adjusted so that the output frequency tracks the input frequency. The earliest examples of PLLs date back to the 1920s.

REF Phase /FrequencyDetector

(PFD)

R Divider

VCO OUT

N (Feedback)Divider

P (Post) Divider

ChargePump

LoopFilter

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Three types of clocking chips

Analog PLLs Simple architecture Very high performance and low noise

Digital PLLs Excellent jitter cleaning Extremely flexible Capable of very low loop bandwidths

Direct Digital Synthesis Extremely flexible frequency generation Very fast frequency sweeping and hopping Very popular in military and instrumentation applications

August 2006 ADI Confidential Information5

Analog PLL Block Diagram

Simplified PLL Block Diagram

In this diagram, Fout = Fin / R * N / P

For Example: 19.44 MHz to 156.25 MHz:

R divider=81, N=3125, P divider = 12

REFINPUT(Fin)

Phase /FrequencyDetector

(PFD)

R Divider

VCOOUTPUT

FREQUENCY (Fout)

N (Feedback)Divider

P (Post) Divider

ChargePump

LoopFilter

66

AD9553 Detailed Block Diagram

A3:0

REGISTER BANKOUTPUT MODE/ SERIAL PORT

PRECONFIGURED DIVIDER SETTINGS

REFA

XTAL

Y5:0

4

6

3

XTAL

CHARGE PUMP

VCO

AD9553

OUT1

3350-4050MHz 5 or 6

LOCKED FILTER

P0

P2

P1

2

N

PFD

LOCK DETECT

TUNING CONTROL

OUT22

20

3 10

10

P0

P2

P1

DN

UP

LOOP FILTER

BW CTRL

3

3

OUTPUT MODE

CONTROL

SPI CTRL

3

x2

RA

14

DET DET A

/5A x2A

x2

RB

14

DET DET B

/5B x2B

x2

RB

14

DET DET XO

FDBK

DN/2UP/2

FDBK/2

XO

REFERENCE SWITCHOVER

CONTROL

CLOCK MUX

CLOCK MUX

HOLD

HOLD

DET B

DET A

DET XO

REF SEL

SEL REFB

5

5

N

RA

RB

RXO

DCXO CTRL

TEST

RA, x2A, /5A

RB, x2B, /5B

RXO, DCXO CTRL

N, P0, P1, P2

REF SEL

TEST

01

0

1

01

0

1

0

1

0

1

0

1

0

1

REF DIFF

REF DIFF

REFB/REFA

XO

FREF

Digital PLL Detailed Block Diagram(AD9548 Shown)

7

TW CLAMPAND

HISTORY

PROG.DIGITAL

LOOPFILTER

TDC/PFD

÷R

÷S

DIGITAL PLL CORE

HOLDOVERLOGIC

CONTROLLOGIC

LOW NOISECLOCK

MULTIPLIER

AMP

SYSCLK PORT

INPUTREF

MONITOR

IRQ ANDSTATUSLOGIC

DIGITALINTERFACE

IRQ

SYSCLKN SYSCLKP

CLKINN

CLKINP

M0 TO M7

REFA

REFAA

OUT0P

PHASECONTROLLER

DDS/DAC

AD9548

4 OR 8

OUT0N

OUT_RSET

OUT1POUT1N

OUT2POUT2N

OUT3POUT3N

POSTDIV

POSTDIV

POSTDIV

POSTDIV

CLOCKDISTRIBUTION

REFB

REFBB

REFC

REFCC

REFD

REFDD

DIFFERENTIALOR

SINGLE-ENDED

EXTERNALANALOGFILTER

08

02

2-0

09

AD9558 Digital PLL Block Diagram

8

XO or XTAL

PFD/CP LF

Output PLL (PLL2)

VCO23.45 to 4.05

GHz.

/N2

Integer divider

PFD/CP

Sy

ste

m P

LL

(PL

L3

)

/N3

x2

XO frequencies 10MHz-180MHzXTAL 10MHz-50MHz

LF capPLL 2 STATUS

AD9558

DigitalLoopFilter

Digital PLL (PLL1)REF Monitoring Automatic Switching

/N1

R Divider (20-bit)

24b / 24b Resolution

2k

Hz t

o 1

.25

GH

z

Frac1/Mod1

17-bit Integer

2 kHz or 8 kHz Frame Sync Signal

/M2

/M3

/M3b

Out3Out3b

Out5Out5b

Ou

t0,1

,2,3

,4:

36

0 k

Hz t

o 1

.25

GH

z;

Ou

t5:

2K

Hz t

o1

.25

GH

z

Frame Sync Pulse

/2

Tuning Word

Clamp & History

REFA_PREFA_N

/2

RF Divider 1/3 to /11

Max 1.25GHz

x2

Multi-Function IO Pins(Control and Status

Read back)

M0 – M7

SPI/I²C Serial PortEEPROM

SYNC RESET PINCONTROL IRQ

SPI / I²C

/M0

/M1

/M0 - /M3b are 10-bit integer

dividers

Out0Out0b

Out1Out1b

Out2Out2b

Out4Out4b

x2Freerun

TW

ROM &

FSM

RegisterSpace

RF Divider 2/3 to /11

30

-bit N

CO

DP

FD

LF

REFA_PREFA_N

/2

REFA_PREFA_N

/2

REFA_PREFA_N

/2

Frame Sync Mode Only

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Generating Clocks using DDSLimiter

ReconstructionFilter

Fsysclock(fc) DAC out Filter out

Clock out

Ideal TimeDomain

Response

IdealFrequency

DomainResponse

"Real World"FrequencyResponse

t

0

1 1 3 5 7

Odd harmonic series

1 3 5 7

t t

f ff

ffffc

fc 2fc

2fc

DDS

The DDS chip can synchronize to a user’s reference. An on-chip clock multiplier can generate the fast clock needed to clock the NCO/DAC. A frequency tuning word may be written to set the output clock rate. External filtering removes unwanted images. A squaring function then converts sine wave to square wave.

10

Common Uses for PLLs

Frequency translation

Jitter Cleanup

Redundant clocking

Holdover

Clock Distrbution

19.44 MHz (SONET) to 156.25 MHz (10 Gb/s Ethernet): R divider=81, N=3125, P divider = 12 Phase detector frequency: 120 kHz VCO frequency: 1875 MHz

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Frequency Translation Example:

REFINPUT(Fin)

Phase /FrequencyDetector

(PFD)

R Divider

VCOOUTPUT

FREQUENCY (Fout)

N (Feedback)Divider

P (Post) Divider

ChargePump

LoopFilter

12

Jitter Clean-up

Clean signal from Clean signal from main clock boardmain clock board

BackplaneBackplane

has lots ofhas lots of

noisenoise

sourcessources Clock received by Clock received by line card is line card is contaminatedcontaminated

Clock received from back plane is Clock received from back plane is used to establish phase and used to establish phase and frequency of the outputfrequency of the output

HOW?HOW?

Digital PLL w/ a Digital PLL w/ a

ProgrammableProgrammable

Digital loop Digital loop

Filter capable ofFilter capable of

<1 Hz BW<1 Hz BW

Reference Input Switchover and Holdover :Holdover:

An ADI clock featuring holdover provides output signals even when the reference input disappears. This feature allows designers to build systems that benefit from greater uptime, while alleviating fears of intermittent or unreliable reference signals crashing the system.

Switchover:

An ADI clock featuring switchover capability has multiple reference input ports. If one of the references fails, the clock device will use one of the alternate references instead. An important aspect of all the switchover functions provided in ADI clock devices is that no runt pulses and no extra long pulses result from this change. Downstream PLLs will not lose lock as a result, of or during, switchover - even when no predefined relationship exists between the phases of the various reference input signals.

Holdover and Switchover can be initiated either as directed by a controller/processor in the system, or by using the on-chip monitoring function which will automatically perform a switchover and/or holdover when the active reference input goes quiet.

Switchover, Synchronization, and Holdover

NOTENOTE

output is synchronized to output is synchronized to primary referenceprimary reference

But what happens when the But what happens when the primary reference disappears?primary reference disappears?

The output slowly transitions until it is The output slowly transitions until it is phase with the back-up referencephase with the back-up reference

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Clock Distribution Example

Delay 1-10nsDelay 1-10ns

1:5 Fanout1:5 Fanout

BufferBuffer

Divide by 1-32Divide by 1-32LVPECL to LVPECL to

CMOSCMOS

LVPECL to LVPECL to

LVDSLVDS

225 fs RMS

225 fs RMS

350 fs RMS

1-3 ps RMS

A

RMS Jitter added

to signal at AExample: AD9512

225 fs RMS

Divide by 1-32Divide by 1-32

Divide by 1-32Divide by 1-32

Divide by 1-32Divide by 1-32

Divide by 1-32Divide by 1-32 LVPECL LVPECL BufferBuffer

LVPECL LVPECL BufferBuffer

LVPECL LVPECL BufferBuffer

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Two reference clock inputs, A/B Automatic or manual reference

switching and holdover Integer-N frequency synthesizer Voltage-Controlled Oscillator (VCO) Programmable dividers

With output-to-output phase offset

Adjustable delay lines LVPECL, LVDS/CMOS logic Up to 14 clock output drivers 5 versions: -0,1,2,3,4

On-chip VCO frequency ranges from 1.45 GHz to 2.95 GHz

14-Output Clock GeneratorWhat’s Inside

All critical timing functions integrated in a single IC at All critical timing functions integrated in a single IC at jitter levels less than 500 fs rmsjitter levels less than 500 fs rms

The World Leader in High-Performance Signal Processing Solutions

Applications forPhase-locked Loops (PLLs)

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Application – Wireless Transceiver CardADC

TRXClock Distribution IC

ADC

ADC

ADC

DDC orASIC

DAC

DUC orFPGA

DAC

User’sReference

Clock

Clock to A-D Converters

Clock to D-A Converters

Clock to Digital Chips

Critical Clock Functions on Transceiver Card:• clean-up jitter on user’s input reference• up-convert user reference frequency to highest frequency needed, usually driven by DAC clock requirements• generate multiple frequencies for RX & TX• provide low jitter clocks for converters• generate mix of LVPECL, LVDS, CMOS clocks• adjust phase or delay between clock channels• offer isolation between clock channels

TRX Cards

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DigitalCross Point

ClockGeneration/Distribution

PowerSequencing

Line Card

Switch Card

XCVRCDR

SERDES

BackplaneSwitch& EQ

DigitalEngine

Optical Transceiver

TIA

LDD

PIN

Laser

LimitingAMP

SignalConditioner

Application – Line Card

Switch Card

Line Card

Backplane

New ADI clock products such as the AD9557 and AD9548 are tailored for network applications.

Specific AD9548 example on next page

SyncE / IEEE1588 Hybrid (with Hooks for Pure IEEE1588)

Ba

ckp

lan

eB

ac

kpla

ne

Line CardLine Card

AD9557AD9557

AD9547AD9547

TCXO /TCXO /

OCXOOCXO Recovered clocks Recovered clocks from Line cardsfrom Line cards

BITSBITSGPSGPS

Timing CardTiming Card

XOXO AD9553/7AD9553/7(Optional)(Optional)

TxTx

RxRx

CPU / FPGA / DSPCPU / FPGA / DSPIEEE1588IEEE1588

Protocol / AlgorithmProtocol / Algorithm

SP

I / IS

PI / I 22

CCMAC/PHYMAC/PHY

SyncE Clock RecoveringSyncE Clock Recovering

++

IEEE1588 Time StampIEEE1588 Time Stamp

Time StampsTime Stamps

FrequencyFrequencySynchronizationSynchronization

1 PPS1 PPS

Timing Card 2Timing Card 2Line Card nLine Card n

Time of Day Offset AdjustmentTime of Day Offset Adjustment

1 PPS1 PPS

Time of DayTime of Day

Clock/Frequency ControlClock/Frequency Control

AD9548AD9548

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ADI’s Complete Clock Portfolio

Analog and Digital PLLs Used for frequency multiplication/translation Redundant Clocking and Holdover

Synthesizers Used for clock generation

Clock Distribution Used for sending the identical clock to multiple chips Also used for logic level translation (i.e., LVPECL to LVDS) May include frequency dividers (/2, /4, etc.) May include skew adjustment

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What Makes Us Special?

DDS (Direct Digital Synthesis) for synthesizers Uses a DAC for synthesizing output frequencies

Digital PLLs Dynamically reconfigurable loop BWs from 100 kHz to 10 Hz. Allows easy implementation of holdover and reference monitors

LC Tank Oscillators Much lower noise than ring oscillators

The “Phase Noise Experts” (Experience with ADC/DACs) Experience measuring jitter to < 100 fs.

We’re “Process Agnostic” We have CMOS/BiCMOS/Bipolar processes available to us. Allows us to use the best process for the job.

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Questions from audience

Upcoming FUNDAMENTAL webcasts

Printed Circuit Board Layout February 8th at 12pm (EST)

Frequency Synthesis: Part 1, PLL March 7th at 12pm (EST)

Frequency Synthesis: Part 2, DDS April 11th at 12pm (EDT)

www.analog.com/webcastwww.analog.com/webcastwww.analog.com/webcastwww.analog.com/webcast

Thank you

Paul Kern

Clock & Signal Synthesis Team

Greensboro, NC